KR20100028785A - Method of manufacturing flash memory device - Google Patents

Abstract

PURPOSE: A method of manufacturing flash memory device is provided to remove a hard mask effectively by applying a buffer film to a method of manufacturing the same. CONSTITUTION: Memory cells are formed on a substrate(100). Memory cells comprises a hard mask on top. A buffer layer fills the space between memory cells. The buffer layer covers the hard mask. The hard mask and the buffer layer is removed through etching. The surface of the memory cells is exposed to the outside. The buffer layer remains behind in the space of the memory cells. The remaining buffer layer is removed. An interlayer insulation film(194) is formed through filling the space of the memory cells. The inter-layer insulating film covers the memory cells.

Description

Manufacturing method of flash memory device {METHOD of MANUFACTURING FLASH MEMORY DEVICE}

The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of manufacturing a flash memory device having a NAND type structure.

Semiconductor memory devices generally include volatile and non-volatile memory devices that lose data over time, such as dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices. It can be divided into The nonvolatile memory device may maintain its state over time when data is input. As such a nonvolatile memory device, an EEPROM (Electrically Erasable and Programmable ROM) and a flash memory device capable of electrically inputting and outputting data have been developed. The flash memory device is an advanced form of an EEPROM device that can be electrically erased at high speed, and is an apparatus that electrically controls data input and output by F-N tunneling or hot electron injection.

Looking at the flash memory device from a circuit point of view, N cell transistors are connected in series to form a unit string, and the unit strings are connected in parallel between a bit line and a ground line. A NAND type flash memory device having a structure in which a cell structure and a cell transistor are connected in parallel between a bit line and a ground line may be classified into a NOR type flash memory device having a structure. The NOR flash device is advantageous for high speed operation, while the NAND flash memory device is advantageous for high integration.

In general, a NAND type flash memory device has a structure including one string including a plurality of cell transistors (memory cells), a ground select transistor, and a string select transistor as a basic unit. In the NAND type flash device having the above-described structure, as the integration degree of the memory cell increases, the space between the selection transistor and the cell transistors also decreases. Accordingly, there is a problem in that voids are generated in the spaces between the cell transistors during the insulating film deposition process.

Accordingly, an object of the present invention to solve the above problems is to provide a method of manufacturing a flash memory device by reducing the step by effectively removing the hard mask applied when forming a memory cell by applying a buffer layer formed by a spin coating method.

According to the method of manufacturing a flash memory device according to an embodiment of the present invention for achieving the above object of the present invention, the memory cells having a hard mask is formed on the substrate. Subsequently, a buffer layer covering the hard mask is formed while the space between the memory cells is buried. Subsequently, the hard mask is removed by etching the buffer layer and the hard mask on the entire surface until the surface of the memory cells is exposed. Subsequently, the buffer film remaining in the space between the memory cells is removed. Subsequently, an interlayer insulating film covering the memory cells is formed while sufficiently filling the space between the memory cells. The result is a flash memory device in which no voids are formed between the structures.

In the manufacture of the flash memory device, the step of forming a spacer film having a uniform thickness on the surface of the memory cells can be further performed. As an example, the hard mask and the buffer layer may include silicon oxide.

According to the flash memory device manufacturing method according to another embodiment of the present invention for achieving the above object of the present invention, a plurality of memory cell transistors and select transistors having a hard mask on the substrate is formed. A spacer film having a uniform thickness is formed on the surfaces of the memory cell transistor and the selection transistor. Subsequently, a buffer layer covering the hard mask is formed while the space between the memory cell transistor and the selection transistor is buried. Subsequently, the buffer layer and the hard mask are etched entirely until the top surfaces of the memory cell transistor and the selection transistor are exposed. Subsequently, the buffer film remaining in the space between the memory cell transistor and the selection transistor is removed. Subsequently, an interlayer insulating film that sufficiently fills the space between the memory cell transistor and the selection transistor is formed. The result is a flash memory device in which no voids are generated between the structures.

As described above, in the method of manufacturing a flash memory device, a void is formed between the memory cell transistors by forming an interlayer insulating layer after removing the hard mask existing on the memory cell transistor and the selection transistors together with the buffer layer. can do. That is, an interlayer insulating film without voids may be formed even though the space between the structures is reduced due to the increase in the degree of integration of the memory device by lowering the height of the memory cell structures formed on the substrate. Since voids are prevented from being formed in the interlayer insulating layer of the memory device, a problem in which structures are electrically connected through voids in a silicide process may be prevented.

 As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements. Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "consist of" are intended to indicate that there is a feature, number, step, operation, component or combination thereof described on the specification, but one or more other features or numbers. It is to be understood that the present invention does not exclude in advance the possibility of the presence or the addition of steps, actions, components or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

NAND Flash Memory Devices

1 illustrates a layout of a NAND flash memory device according to an embodiment of the present invention.

Referring to FIG. 1, active regions 102 in which channel and impurity regions of a cell transistor are to be formed, are spaced apart from each other by the field region 101 and extend in the Y axis in parallel to each other, and are repeatedly arranged in the X axis.

On the active region 102, n word lines (W / L ₁ , W / L ₂ ,..., W / L _n ) corresponding to conductive lines are repeatedly arranged in the Y axis while extending in the X axis, thereby floating gates. Memory cell transistors having a stacked gate structure including (not shown) and a control gate (word line) are formed. As such, high concentrations of impurity regions (not shown) are formed on the surface of the exposed active region 102 between the word lines W / L ₁ , W / L ₂ ,..., W / L _n spaced at predetermined intervals. do.

A plurality of memory cell arrays arranged in the XY direction by an array of the active region 102 extending in the Y axis and the word lines W / L ₁ , W / L ₂ ,..., W / L _n extending in the X axis. When forming a, with a ground select line (GSL) and a string select line (SSL) included in the selection transistor outside the first word line (W / L ₁ ) and the n-th word line (W / L _n ) A "string" is formed as one memory unit. The select transistor includes a ground select transistor and a string select transistor. In the string, n memory cell transistors are connected in series while sharing an impurity region. As an example, the conductive line may include a selection line.

Select transistors constituting the ground select line (GSL) and the string select line (SSL) have a floating gate and a control in the field region 101 between each input / output (I / O) to prevent signal delay caused by a resistor. Butting contacts (not shown) for connecting the gates are provided. Thus, the select transistors operate as MOS transistors having electrically one gate.

One side of the string select line SSL is provided with a bit line contact. On the word lines W / L ₁ , W / L ₂ ,..., W / L _n , k bit lines B / L _k , B repeated on the X-axis while extending in the Y-axis so as to be orthogonal to the word lines. / L _k-1 , B / L _k-2 , ...) are formed. Another outer side of the "string" is provided with a common source contact extending in the X-axis direction between adjacent ground select lines GSL.

FIG. 2 is a cross-sectional view illustrating a NAND type flash memory device according to an exemplary embodiment of the present invention taken along the direction of Y-Y '.

Referring to FIG. 2, the NAND type flash memory device of the present exemplary embodiment includes a plurality of memory cells formed on the substrate 100, a spacer layer 175, and an interlayer insulating layer 194 insulating the same. The plurality of memory cells may include a memory cell transistor 150 and select transistors 130 and 170. The memory cell transistor 150 is a stacked memory cell including a dielectric layer, and the select transistor includes a ground select transistor 130 and a string select transistor 170.

The substrate 100 includes a cell transistor region B and select transistor regions A and C. Referring to FIG. For example, the substrate may include selection transistor regions A and C having an upper surface having a different height from that of the cell transistor region B. Referring to FIG. The substrate 100 may be divided into an active region (not shown) and a field region (not shown) by an isolation layer (not shown).

Select transistor regions A and C of the substrate include a string select transistor region C and a ground select transistor region A. FIG. As an example, the ground select transistor region A is located at one side of the cell transistor region B. On the other hand, the string select transistor region C is located on the other side of the cell transistor region B.

The ground select transistor 130 is formed in the ground select transistor region A of the substrate 100 and has a first impurity region formed in the first gate structure 120 and the substrate adjacent to the first gate structure 120. And 125.

For example, the first gate structure 120 may have a structure including an insulating layer pattern 112a, a first conductive layer pattern 114a, a dielectric layer pattern 116a, and a second conductive layer pattern 118a. . In this case, the first conductive layer pattern 114a and the second conductive layer pattern 118a have a structure electrically connected by trenches (not shown) formed in the dielectric layer.

As another example, the first gate structure 120 may have a structure in which an insulating layer pattern and a gate electrode are stacked. In addition, the impurity region 125 of the ground select transistor 120 is electrically connected to a source contact (not shown).

The memory memory cell transistor 150 includes second gate structures 140 formed in the cell transistor region B of the substrate 100. In addition, the second impurity regions 145 may be adjacent to the second gate structures 140. For example, the second gate structures 140 may include a tunnel insulating layer pattern 112b, a floating gate 114b, a dielectric layer pattern 116b, and a control gate 118b. As another example, the second gate structure 140 may include a tunnel insulation pattern, a charge trap body pattern, a blocking pattern, and an electrode.

The string select transistor 170 is formed in the string select transistor region C of the substrate and includes a third gate structure 160 and third impurity regions 165 of the substrate adjacent to the third gate structure.

As an example, although not shown in the drawing, the third gate structure 160 may have a fin FET structure or a planar structure. As an example, the third gate structure 160 may have a structure in which an insulating layer pattern and a gate electrode are stacked.

As another example, the third gate structure 160 may have a structure including an insulating layer pattern 112c, a first conductive layer pattern 114c, a dielectric layer pattern 116c, and a second conductive layer pattern 118c. . In this case, the first conductive layer pattern 114c and the second conductive layer pattern 118c of the third gate structure 160 have a structure electrically connected by a trench (not shown) formed in the dielectric layer pattern 116c. The third impurity region 165 of the string select transistor 170 is electrically connected to a bit line contact (not shown).

The spacer layer 175 is formed on sidewalls of the memory cell transistor 130 and the selection transistors 150 and 170, and thereafter, when the insulating layer is buried to form a space between the memory cell transistor and the selection transistor, no buried effect is formed. Serves to increase. As an example, the first intermediate temperature oxide film may be formed to a thickness of 5 to 50 kPa.

The interlayer insulating layer 194 is formed to cover the memory cell transistor and the selection transistor while isolating the memory cell transistor and the selection transistor on which the spacer layer 175 is formed. The interlayer insulating film is sufficiently buried between the cell transistor and the selection transistor so that no void is present. Examples of the insulating layer 140 may include a BPSG oxide film, a PSG oxide film, an SGO oxide film, a medium temperature oxide film, and the like. The insulating film may be formed by performing chemical vapor deposition, spin coating, or a medium temperature oxide film forming process.

In the present embodiment, a hard mask does not exist on the string select transistor and the memory cell transistor. Accordingly, the string select transistor and the memory cell transistor have a relatively low level with respect to the surface of the substrate compared with the conventional memory device. That is, even when the integration degree of the process is increased and the formation intervals of the string selection transistor and the memory cell transistor are narrowed, an insulating film which does not generate voids can be formed.

Fabrication of NAND Flash Memory Devices

3 through 8 are cross-sectional views illustrating a method of manufacturing the NAND type flash memory device illustrated in FIG. 2. 3 to 8, the same reference numerals are used for the same members as in FIG. 3.

Referring to FIG. 3, a substrate 100 including a ground select transistor region A, a cell transistor region B, and a string select transistor region C is prepared. The substrate 100 may be divided into an active region and a field region because an isolation layer (not shown) is formed.

Next, a first oxide film 112 is formed on the substrate 100. The first oxide film 112 may be formed by performing a thermal oxidation process. In this case, the first oxide layer 112 is formed on the silicon substrate exposed to the device isolation layer corresponding to the active region.

Here, the first oxide film 112 formed in the ground select transistor region A of the substrate is used as the gate oxide film of the ground select transistor, and the first oxide film 112 formed in the cell transfer region B of the substrate. ) Is used as the tunnel oxide film of the memory cell transistor, and the first oxide film 112 formed in the string select transistor region C of the substrate is used as the gate oxide film of the string select transistor. Therefore, the gate oxide film and the tunnel oxide film can be simultaneously formed on the substrate in one oxidation process.

Subsequently, a preliminary conductive film having a substantially uniform thickness is formed on the substrate on which the first oxide film 112 is formed. The preliminary conductive layer may be formed of polysilicon and a metal material including impurities using a chemical vapor deposition process. As another example, a silicon nitride film, which is a charge trap body, may be formed instead of the conductive film. Thereafter, the preliminary conductive layer is patterned in parallel with the device isolation layer (ie, perpendicular to the word line direction). As a result, the preliminary conductive film is formed of the first conductive film 114 existing only on the active region.

Here, the first conductive film 114 formed on the ground select transistor region A of the substrate is used as an electrode of the ground select transistor, and the first conductive film formed on the cell transistor region B of the substrate ( 114 is used as a floating gate of the memory cell transistor, and the first conductive film 114 formed on the string select transistor region C of the substrate is used as an electrode of the string select transistor.

Subsequently, a dielectric film 116 having a uniform thickness is formed on the first conductive film 114. The dielectric layer 116 may have an ONO structure in which oxides / nitrides / oxides are sequentially stacked. In addition, the dielectric layer 116 may be formed using a material having a high dielectric constant so as to reduce leakage current generated through the dielectric layer while maintaining a thin equivalent oxide thickness (EOT). In this case, the dielectric layer 116 may be formed using hafnium oxide, zirconium oxide, tantalum oxide, aluminum oxide, titanium oxide, rubidium oxide, magnesium oxide, strontium oxide, boron oxide, lead oxide or calcium oxide.

In addition, the dielectric layer 116 may have a multilayer structure in which thin films made of a silicon oxide layer, a silicon nitride layer, and a material having a high dielectric constant are sequentially stacked. As an example, the dielectric layer 116 may be used as a blocking layer when the first conductive layer is a silicon nitride layer that is a charge trapping body.

Thereafter, a trench (not shown) is formed in the dielectric layer 116 formed on the ground select transistor region A and the string select transistor region C of the substrate to expose the surface of the first conductive layer 114. The trench is a butting contact that allows a second conductive layer formed in a subsequent process to be electrically connected to the first conductive layer to be used as a gate electrode of the selection transistor.

Subsequently, a second conductive layer 118 is formed on the dielectric layer 116. The second conductive layer 118 includes a conductive material for forming a gate electrode or a control gate. The conductive material may include polysilicon or a metal having a work function of about 4.0 eV or more. According to an embodiment of the present invention, the first conductive film may have a single layer structure of a polysilicon film doped with impurities or a multilayer structure including a polysilicon film and a metal film doped with impurities.

Subsequently, a hard mask 155 is formed on the second conductive film 118. The hard mask 155 may include silicon oxide or silicon nitride, and may form regions of the first gate structure 120 of the ground select transistor, the second gate structure of the memory cell transistor, and the third gate structure of the string select transistor. define. As an example, the hard mask 155 may have a thickness higher than that of the second conductive layer.

Referring to FIG. 4, the second conductive layer 118, the dielectric layer 116, the first conductive layer 114, and the first insulating layer 112 exposed to the hard mask 155 are sequentially patterned. As a result, the first gate structure 120, the second gate structure 140, and the third gate structure 160 having the hard mask 155 thereon are formed on the substrate. The first gate structure 120 corresponds to a ground select line of a ground select transistor, the second gate structure 140 corresponds to a word line of a memory cell transistor, and the third gate structure 160 selects a string. Corresponds to the string select line of the transistor.

For example, the first gate structure 120 may include an insulating layer pattern 112a, a first conductive layer pattern 114a, a dielectric layer pattern 116a, and a second conductive layer pattern 118a. In this case, the first conductive layer pattern 114a and the second conductive layer pattern 118a of the first gate structure may have a structure electrically connected by a trench formed in the dielectric layer pattern 116a. As another example, the second gate structure 140 may include a tunnel insulation layer pattern 112b, a floating gate 114b, a dielectric layer pattern 116b, and a control gate 118b. As another example, the third gate structure 160 may include an insulating layer pattern 112c, a first conductive layer pattern 114c, a dielectric layer pattern 116c, and a second conductive layer pattern 118c. In this case, the first conductive layer pattern 114c and the second conductive layer pattern 118c may have a structure electrically connected by a trench formed in the dielectric layer pattern 116c.

Subsequently, an ion implantation process is performed to form the impurity regions 125, 145, and 165. The impurity region includes a first impurity region 125 formed in the silicon substrate adjacent to the first gate structure 120. As an example, the first impurity region 125 is a common source region. In addition, the impurity region is formed on the surface of the silicon substrate exposed between the second gate structures 140 and includes a second impurity region 145 connecting the memory cells in series. In addition, the impurity region includes a third impurity region 165 formed in the silicon substrate adjacent to the third gate structure 160. As an example, the third impurity region 165 includes a drain region. Through the above method, the ground select transistor 130, the memory cell transistor 150, and the string select transistor 170 having a fin structure are formed on the substrate 100.

Referring to FIG. 5, a spacer layer 175 having a uniform thickness is formed on surfaces of gate structures of the memory cell transistor and the selection transistor.

For example, the spacer layer 175 may be formed to have a uniform thickness on the surfaces of the first gate structure 120, the second gate structure 140, and the third gate structure 160 where the hard mask 155 is present. do. The spacer film 175 is a medium temperature oxide film and is formed to a thickness of about 5 to about 50 microns. Here, the spacer layer 175 has a function of allowing the layer insulating layer to be more easily buried in the spaces between the gate structures when the interlayer insulating layer is deposited.

Referring to FIG. 6, a buffer layer 177 is formed to cover the hard mask 155 while filling a space between gate structures included in the plurality of memory cell transistors and the selection transistor. As an example, the buffer layer is formed by spin coating a layer including silicon oxide or silicon nitride having an etching ratio similar to that of the hard mask. That is, the buffer layer 177 has a flat upper surface while buried enough space between the gate structures. A SOH (Spin On Hardmask) film was used as the buffer film 177 of this embodiment.

Referring to FIG. 7, the buffer layer 177 and the hard mask are all etched until the top surfaces of the memory cell transistor and the selection transistor are exposed. As a result, the hard mask existing on the gate structure included in the memory cell transistor and the selection transistor can be removed.

As an example, since the buffer layer and the hard mask have substantially the same etching ratio, an upper portion of the hard mask and the buffer layer 177 may be removed when the entire dry etching process is performed without applying a mask. The buffer layer 177 having an upper portion removed through the front surface dry etching process is left in the space between the plurality of memory cell transistors and the selection transistor.

Referring to FIG. 8, the buffer layer remaining in the space between the memory cell transistor and the selection transistor is removed. As an example, the residual buffer layer may be removed by performing an etching process using an oxygen plasma by applying the gate structures as an etching mask. As the residual buffer layer is removed, a space between the first gate structure 120, the second gate structure 140, and the third gate structure 160 is exposed again.

Thereafter, an interlayer insulating film 194 is formed to sufficiently fill the space between the memory cell transistor and the selection transistor from which the hard mask is removed. As a result, as shown in FIG. 2, voids are not generated inside the interlayer insulating film formed by the step difference of the memory cell transistors lowered due to the removal of the hard mask. The interlayer insulating film 194 may be formed using silicon oxide such as BPS, PSG, USG, SG, or medium temperature oxide. According to an embodiment, the interlayer insulating layer 194 may be formed using a medium temperature oxide film or SOG, which may easily fill a space between the first to third gate structures.

9 illustrates another embodiment to which the flash memory device of the present invention is applied.

As shown in FIG. 9, the embodiment includes a memory 510 connected to a memory controller 520. The memory 510 may be a NAND memory device including a memory cell transistor as shown in FIG. 2. That is, the memory 510 may be any flash memory device manufactured according to an embodiment of the present invention. The memory controller 520 provides an input signal for controlling the operation of the memory. For example, the memory controller 520 provides a command (CMD) signal, an address (ADD) signal and an I / O signal, which are input signals of a DRAM device. The memory controller may control data on the DRAM device based on an input signal.

10 illustrates another embodiment to which the flash memory device of the present invention is applied.

As shown in FIG. 10, this embodiment includes a memory 510 coupled to the host system 700. The memory 510 may be any flash memory device manufactured according to an exemplary embodiment of the present invention. The host system 700 includes electronic products such as a personal computer, a camera, a mobile device, a game machine, a communication device, and the like. The host system 700 applies an input signal for controlling and operating the memory 510, and the memory 510 is used as a data storage medium.

11 illustrates another embodiment in which the flash memory device of the present invention is applied.

As shown in FIG. 11, this embodiment represents a portable device 600. The portable device 600 may be an MP3 player, a video player, a multifunction device of video and audio player, or the like. As shown, portable device 600 includes a memory 510 and a memory controller 520. The memory 510 may be any flash memory device manufactured according to an exemplary embodiment of the present invention. The portable device 600 may also include an encoder / decoder 610, a display member 620, and an interface 630. Data (audio, video, etc.) is inputted and outputted from the memory 510 by the encoder / decoder 610 via the memory controller 520.

12 shows another embodiment to which the flash memory device of the present invention is applied.

As shown in FIG. 12, the memory 510 is connected to a central processing unit (CPU) 810 within the computer system 800. For example, the computer system 800 may be a personal computer, a personal data assistant, or the like. The memory 510 may be directly connected to the CPU or may be connected through a bus. The memory 510 may be any DRAM device manufactured according to an exemplary embodiment of the present invention. Although each element is not sufficiently shown in FIG. 12, each element may be included in the computer system 800.

As described above, according to the method of manufacturing the flash memory of the present invention, a void is formed between the memory cell transistors by forming an interlayer insulating layer after removing the hard mask existing on the memory cell transistor and the selection transistors. have. That is, an interlayer insulating film without voids may be formed even though the space between the structures is reduced due to the increase in the degree of integration of the memory device by decreasing the height of the structure of the memory cell formed on the substrate. Since voids are prevented from being formed in the interlayer insulating layer of the memory device, a problem in which structures are electrically connected through voids in a silicide process may be prevented.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be modified in various ways without departing from the spirit and scope of the invention described in the claims below. And can be changed.

1 illustrates a layout of a NAND flash memory device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a NAND type flash memory device according to an exemplary embodiment of the present invention taken along the direction of Y-Y '.

3 to 8 are cross-sectional views illustrating a method of manufacturing the NAND type flash memory device illustrated in FIG. 2.

9 illustrates another embodiment to which the flash memory device of the present invention is applied.

10 illustrates another embodiment to which the flash memory device of the present invention is applied.

11 illustrates another embodiment in which the flash memory device of the present invention is applied.

12 shows another embodiment to which the flash memory device of the present invention is applied.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 120 first gate structure

130: ground select transistor 140: second gate structure

150: memory cell transistor 160: third gate structure

170: string select transistor 155: hard mask

175: spacer film 177: buffer film

Claims (8)

Forming memory cells with a hard mask on the substrate; Forming a buffer layer covering the hard mask while filling the space between the memory cells; And Removing the hard mask by etching the buffer layer and the hard mask on the entire surface until the surface of the memory cells is exposed; Removing the buffer film remaining in the spaces between the memory cells; And Forming an interlayer insulating film covering the memory cells while sufficiently filling the space between the memory cells. The method of claim 1, further comprising forming a spacer layer having a uniform thickness on the surfaces of the memory cells. The method of claim 1, wherein the hard mask comprises silicon oxide. The method of claim 1, wherein the buffer layer is formed by spin coating silicon oxide. The method of claim 1, wherein the residual buffer layer is removed by performing a dry etching process using an oxygen plasma. Forming a plurality of memory cell transistors and select transistors having a hard mask thereon on the substrate; Forming a spacer film having a uniform thickness on surfaces of the messel shell transistor and the selection transistor; Forming a buffer layer covering the hard mask while filling the space between the memory cell transistor and the selection transistor; Etching the buffer layer and the hard mask on the entire surface until the top surfaces of the memory cell transistor and the selection transistor are exposed; Removing the buffer film remaining in the space between the memory cell transistor and the selection transistor; And And forming an interlayer insulating film sufficiently buried between the memory cell transistor and the selection transistor. The method of claim 6, wherein the spacer layer is formed by depositing mesophilic oxide to a thickness of 5 to 50 GPa. The method of claim 6, wherein the hard mask and the buffer layer comprise silicon oxide.

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