KR20100025728A - Method of manufacturing an epitaxial wafer and the epitaxial wafer applying the same and semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing an epitaxial wafer, the epitaxial wafer thereby and a semiconductor device using the epitaxial wafer are provided to prevent the penetration of an oxygen precipitate into an epi-layer by annealing a wafer substrate prior to the formation of the epi-layer. CONSTITUTION: A wafer substrate with a first doping concentration is prepared(S210). The wafer substrate is pre-annealed in a first gas atmosphere(S220). In a nitrogen atmosphere or the atmosphere of a mixed gas of the nitrogen and an oxygen, the wafer substrate is annealed(S230). An oxide layer formed during the annealing process is removed(S240). One or more epi-layers are formed on the annealed wafer substrate(S250).

Description

Method of manufacturing an epitaxial wafer and the epitaxial wafer applying the same and semiconductor device

The present invention relates to a method for manufacturing an epitaxial wafer, an epitaxial wafer and a semiconductor device to which the same is applied, and more particularly, to a method for manufacturing an epitaxial wafer having an epitaxial layer formed on a silicon wafer substrate and an epitaxial wafer to which the same is applied.

Epitaxial wafers are used in the production of semiconductor components that require very clean wafers, such as CMOS image sensors or DRAMs.

Commercial epitaxial wafers used in CMOS optical sensors are manufactured by growing a low concentration epitaxial layer on a wafer substrate doped with boron at a high concentration. Commercial epitaxial wafers are backsealed with polysilicon on the backside of the wafer substrate to reduce metal contamination in the active area.

 However, this is insufficient to getter the metal ions of the silicon wafer substrate, so that the metal ions penetrate into the active region during the actual product manufacturing, thereby deteriorating the operation of the device. In particular, in the case of a device sensitive to metal contamination such as a CMOS optical sensor, when the concentration of these metals is increased, a dark current increases and a bad pixel increases.

Metal contamination can be analyzed in many ways, but wafer manufacturers use a device called Surface Photo Voltage (SPV) Spectroscopy. However, since the metal contamination is not easy to manage, even if the epitaxial wafers are manufactured by the same manufacturer, the electrical properties are often different depending on the ingot or the same ingot. As a result, the dark bad pixels of the CMOS optical sensor may bunch only in the case of a wafer manufactured from a specific ingot.

Accordingly, there is a demand for a method of further reducing the metal ions of the epitaxial wafer.

The present invention has been made to solve the above problems, an object of the present invention, to further reduce the metal ions of the epitaxial wafer, the wafer substrate is pre-annealed in the atmosphere of the first gas (pre an epitaxial wafer manufacturing method which is annealed in a nitrogen atmosphere or a mixed gas atmosphere of nitrogen and oxygen after annealing, and forms at least one epitaxial layer on the annealed wafer substrate, and an epitaxial wafer manufacturing apparatus using the same. An epitaxial wafer is provided.

An epitaxial wafer manufacturing method according to the present invention for achieving the above object comprises the steps of preparing a wafer substrate having a first doping concentration; A pre-anneal step of annealing the wafer substrate in an atmosphere of a first gas; Annealing the pre-annealed wafer substrate in a nitrogen atmosphere or a mixed gas atmosphere of nitrogen and oxygen; And forming at least one epitaxial layer on the annealed wafer substrate.

In addition, the first gas preferably includes at least one gas selected from the group consisting of nitrogen (N ₂ ), argon (Ar), and hydrogen (H ₂ ).

Moreover, it is preferable that the said 1st gas further contains oxygen.

The pre-annealing step is preferably performed by any one of a rapid thermal annealing (RTA) method, a furnace annealing method, and a plasma treatment method.

In addition, the pre-annealing step, when performed by the Rapid Thermal Anneal (RTA) method or the Furnace (Furnace) annealing method, it is preferably carried out at 800 ℃ to 1200 ℃.

And, the pre-annealing step, when performed by the plasma (Plasma) treatment method, it is preferably carried out at 600 ℃ to 800 ℃.

In addition, the annealing step, the nucleation step of generating a nucleus of the oxygen precipitate; And a growth step of growing the oxygen precipitates.

The nucleation step is preferably performed at 550 ° C. to 850 ° C.

In addition, the growth step is preferably performed at 900 ℃ to 1200 ℃.

In addition, the annealing step is preferably performed in a digital (DZ: Denuded Zone) annealing manner.

The method may further include removing the oxide film generated in the annealing step after the annealing step.

In addition, the oxide film removing step, it is preferable to remove the oxide film using a HF aqueous solution or a buffered oxide etchant (BOE: Buffered Oxide Etcher).

The epitaxial layer forming step may include forming a first epitaxial layer having a second doping concentration on the wafer substrate.

The epi layer forming step may further include forming a second epi layer having a third doping concentration on the first epi layer.

In addition, it is preferable that the second doping concentration of the first epitaxial layer is higher than the first doping concentration, and the third doping concentration of the second epitaxial layer is lower than the second doping concentration.

The first epitaxial layer forming step and the second epitaxial layer forming step are preferably performed in-situ with each other.

The epi layer forming step may further include forming a third epi layer having a fourth doping concentration on the second epi layer.

The third epitaxial layer forming step is preferably performed in-situ with the second epitaxial layer forming step.

Meanwhile, the epitaxial wafer according to the embodiment of the present invention is preferably manufactured using the above-described epitaxial wafer manufacturing method.

Meanwhile, the semiconductor device according to the embodiment of the present invention is preferably manufactured using the epitaxial wafer manufactured by the above-described epitaxial wafer manufacturing method.

According to various embodiments of the present invention, after pre-annealing the wafer substrate in an atmosphere of a first gas, the wafer substrate is annealed in a nitrogen atmosphere or a mixed gas atmosphere of nitrogen and oxygen, and then on the annealed wafer substrate. It is possible to provide an epitaxial wafer manufacturing method for forming at least one epitaxial layer and an epitaxial wafer to which the same is applied, thereby further reducing metal ions of the epitaxial wafer and manufacturing a high quality epitaxial wafer.

Hereinafter, with reference to the drawings will be described the present invention in more detail.

1 is a cross-sectional view of an epitaxial wafer according to an embodiment of the present invention. As shown in FIG. 1, the epitaxial wafer includes a wafer substrate 110, a first epitaxial layer 120, and a second epitaxial layer 130.

In the present specification, the wafer substrate 110 means a bulk wafer made of single crystal silicon, but the present invention can be applied to wafers such as gallium in addition to single crystal silicon. A single crystal silicon wafer is manufactured by forming an ingot using a single crystal silicon seed in a silicon melt, and cutting the ingot thinly.

Specifically, silicon, which is used as the wafer material for integrated circuits, is an element that exists naturally about 28% of the surface, and is mainly present in the form of oxide (silica) or silicate. When silica is mainly composed of silica and coke, together with an electric furnace, is melted and chemically treated to obtain silicon in powder form of about 98% purity, called metalloid silicon. When the powdered silicon is converted into gaseous silicon and heat-treated, polycrystalline silicon having approximately 99% purity is obtained.

Since silicon wafers used in integrated circuit fabrication must be single crystals, physical crystallization methods are used to convert polycrystalline silicon into single crystal silicon. The most common method used to make polycrystalline silicon into single crystal silicon is the Czochralski method.

Briefly, the Czochralski method is as follows. First, the high purity silicon melt in the quartz crucible is maintained at a temperature slightly above the melting point by high frequency induction heating. In order to grow single crystal silicon, a single crystal piece of silicon called seed-crystal is placed on the surface of the rotating shaft and brought up while rotating the shaft at a speed of about 50 to 100 mm every hour. The silicon solution grows in the same crystalline direction as the seed crystals, forming a cylindrical silicon mass called an ingot.

The cylindrical ingot grown by the Czochralski method is thinly cut into discs using a cutter, and then the surface is polished by a chemical mechanical method to make a thin wafer. At this time, the type of wafer is determined by the type and amount of added impurities. If dopants such as phosphorus (Phosphorus, P) or arsenic (Arsenic, As), which are periodic group 5 materials, are doped, they are transferred to the n-type wafer. When dop-type impurities such as boron (B), a periodic group III material, are doped, they are made into a p-type wafer. Impurities should be evenly distributed throughout the silicon wafer, and the resistance value of the substrate depends on the concentration of the impurity.

The wafer substrate 110 has a first doping concentration. Here, the wafer substrate 110 of the first doping concentration may be a low doped wafer or a high doped wafer. In the present specification, the low concentration wafer has a specific resistance of 1 to 50 Ω · cm, and the high concentration wafer is 10 to ⁵ to 10 ⁻¹ Ω · cm. In addition, the wafer substrate 110 may be an n-type wafer, a p-type wafer, or an intrinsic wafer.

The wafer substrate 110 is called a 'p + substrate' for a high concentration p-type wafer, a p-type substrate for a p-type wafer having a higher p + concentration, and a 'p + substrate' for a lower concentration p-type wafer than p +. Substrate. Similarly, when the wafer substrate 110 is an n-type wafer, it is also referred to as an 'n + substrate', an 'n ++ substrate' and an 'n- substrate'. Such a name is applied not only to the wafer substrate 110 but also to the epi layer.

The wafer substrate 110 is contaminated by heavy metals such as iron (Fe), copper (Cu), nickel (Ni), etc. during the manufacturing process. If the heavy metal penetrates into the active layer, the device malfunctions or shortens its lifespan. Therefore, in order to prevent this, the wafer substrate 110 is subjected to a gettering process.

Gathering includes intrinsic gettering and extrinsic gettering. Exogenous gathering is a method of deliberately applying mechanical distortion on the back surface of a silicon wafer or depositing polycrystalline silicon to form a back seal, which is a distortion layer, and trapping heavy metal impurities using the distortion layer as a capture base.

In contrast, intrinsic gathering is annealed (ie, heat treated) to a silicon wafer to form an internal micro defect (hereinafter referred to as "BMD"), which is an oxygen precipitate (Oxygen Precipitate) in the wafer, and a BMD. Is a gathering method for capturing heavy metal impurities using as a capture base for heavy metals.

In this embodiment, the wafer substrate 110 is subjected to intrinsic gathering. The wafer substrate 110 is pre-annealed in an atmosphere of a first gas and then annealed in a nitrogen atmosphere or a mixed gas atmosphere of nitrogen and oxygen.

Here, the first gas includes at least one gas selected from the group consisting of nitrogen (N ₂ ), argon (Ar), and hydrogen (H ₂ ). In addition, oxygen may be further included. In other words, the first gas may be any one of nitrogen (N ₂ ), argon (Ar), and hydrogen (H ₂ ), or may be a mixed gas of at least two gases of nitrogen, argon, hydrogen, and oxygen.

As shown in Figs. 5A to 5C, although a large amount of oxygen precipitates are generated even in argon and hydrogen atmospheres, since most oxygen precipitates are observed when pre-annealing is performed in a nitrogen atmosphere, a nitrogen atmosphere is most preferable. Do.

The wafer substrate 110 is pre-annealed by any one of a rapid thermal annealing (RTA) method, a furnace annealing method, and a plasma processing method. In addition, when the wafer substrate 110 is pre-annealed by the rapid heat treatment method or the furnace annealing method, the wafer substrate 110 is pre-annealed at 800 ° C to 1200 ° C. On the other hand, when the wafer substrate 110 is pre-annealed by a plasma treatment method, the wafer substrate 110 is pre-annealed at 600 ° C to 800 ° C. That is, by the plasma treatment method, it is possible to pre-anneal at a relatively low temperature. In addition, it may be pre-annealed at a temperature other than the above temperature, but the effect of pre-annealing is inadequate.

Thereafter, the wafer substrate 110 is annealed in a nitrogen atmosphere or a mixed gas atmosphere of nitrogen and oxygen. The wafer substrate 110 is annealed in a digitized zone (DZ) annealing manner. Specifically, the wafer substrate 110 is annealed through a nucleation step of generating nuclei of oxygen precipitates and a growth step of growing the oxygen precipitates. As shown in FIG. 1, the wafer substrate 110 may confirm that oxygen precipitates are generated.

Nucleation step is carried out at 550 ℃ to 850 ℃. The nucleation step is the process of generating nuclei to generate oxygen precipitates at relatively low temperatures. If the nucleation step is performed at other temperatures, the degree of nucleation is insufficient.

And the growth step is carried out at 900 ℃ to 1200 ℃. The growth stage is a process of growing a nucleus generated in the nucleation stage at a high temperature. If the growth step is performed at a lower temperature than this, the growth of the oxygen precipitates is insufficient.

The oxide film generated during the annealing of the wafer substrate 110 is removed by an etching solution. For example, the etching solution may be an aqueous HF solution or a buffered oxide etchant (BOE).

As such, the wafer substrate 110 is pre-annealed in an atmosphere such as nitrogen gas before being annealed, thereby generating more oxygen precipitates in the annealing process. In addition, the more oxygen precipitates are generated in the wafer substrate 110, the more metal ions can be removed during intrinsic gathering. That is, a cleaner wafer substrate 110 can be obtained by going through the pre-annealing step.

After the annealing of the wafer substrate 110 is completed, the first epitaxial layer 120 and the second epitaxial layer 130 are formed on the wafer substrate 110. In detail, the first epitaxial layer 120 is formed on the wafer substrate 110, and the second epitaxial layer 130 is formed on the first epitaxial layer 120.

The first epitaxial layer 120 and the second epitaxial layer 130 are formed by epitaxial growth or epitaxial. Epitaxial growth or epitaxial growth refers to a process of forming a new high purity crystal layer by matching crystal orientation on a single crystal silicon wafer surface grown by Czochralski method. The layer thus formed is referred to as an epitaxial layer or an epi-layer.

The epitaxial process proceeds in two steps with a silicon wafer loaded into a deposition chamber and then seated on a susceptor. First, the first step is to "pre-bake" a cleaning gas, such as hydrogen or H ₂ / HCl mixed gas, on the wafer surface at about 1150 ° C and clean the silicon wafer surface. And remove all native oxides formed on the wafer surface so that the epitaxial silicon layer is continuously and evenly grown on the surface. In the second step of the epitaxial method, a silicon vapor source such as silane or trichlorosilane is applied to a wafer surface at a temperature of about 1000 ° C. or higher, and a silicon layer is deposited on the surface. It is to grow.

Through this process, the first epitaxial layer 120 and the second epitaxial layer 130 are formed on the wafer substrate 110.

In addition, the first epitaxial layer 120 and the second epitaxial layer 130 are formed using low plasma chemical vapor deposition (LPCVD), ultra high vacuum chemical vapor deposition (UHVCVD), or remote plasma chemical vapor deposition (RPCVD) equipment. May be

In addition, the first epitaxial layer 120 and the second epitaxial layer 130 may be a high concentration epi layer or a low concentration epi layer, and may be both n-type and p-type. That is, each of the first epitaxial layer 120 and the second epitaxial layer 130 may be any one of p ++ epitaxial layer, p + epitaxial layer, p− epitaxial layer, n ++ epitaxial layer, n + epitaxial layer, and n− epitaxial layer. have. However, it is preferable that the first epitaxial layer 120 and the second epitaxial layer 120 have different doping concentrations.

The first epitaxial layer 120 and the second epitaxial layer 130 are formed under a pressure of 10 to 760 Torr at a temperature of 900 to 1200 degrees Celsius. In addition, the process of forming the first epitaxial layer 120 may be formed in-situ with the process of forming the second epitaxial layer 130. When the first epitaxial layer 120 and the second epitaxial layer 130 are formed in-situ, since the formation process of the two layers is connected by vacuum, an oxide film or the like is not formed between the two layers and the first epitaxial layer 120 is formed. After the formation, the second epitaxial layer 130 can be formed.

The wafer substrate 110, the first epitaxial layer 120, and the second epitaxial layer 130 may have various doping concentrations and polarities. For example, the second doping concentration of the first epitaxial layer 120 is higher than the first doping concentration of the wafer substrate 110, and the third doping concentration of the second epitaxial layer 130 is the first epitaxial layer 120. It can be prepared lower than the second doping concentration of.

Specifically, the wafer substrate 110 may be manufactured to have a doping concentration of p −, a first epi layer 120 having a p ++ doping concentration, and a second epi layer 130 having a p − doping concentration. Since the epitaxial wafer manufactured as described above uses a p- substrate, it is possible to easily manage and remove metal contamination, thereby making it possible to manufacture a cleaner epitaxial wafer. In addition, since the first epitaxial layer 120 has a p ++ doping concentration and the second epitaxial layer 130 has a p− doping concentration, it can be used as a substitute for commercial epitaxial wafers.

However, in addition to this, epitaxial wafers having various structures may be manufactured, and the epitaxial wafers having various structures will be described later.

A process for manufacturing the epitaxial wafer as described above will be described below with reference to FIG. 2. 2 is a flowchart illustrating an epitaxial wafer manufacturing method according to an embodiment of the present invention.

First, a wafer substrate 110 having a first doping concentration is prepared (S210). The wafer substrate 110 is preferably a single crystal silicon bulk wafer manufactured by the Chocoralski method or the like.

Thereafter, the wafer substrate 110 is pre-annealed in the atmosphere of the first gas (S220). Here, the first gas may be any one of nitrogen (N 2), argon (Ar), and hydrogen (H 2). In addition, the first gas may be a mixed gas of at least two gases of nitrogen, argon, hydrogen, and oxygen. However, it is more preferable to pre-anneal in a nitrogen atmosphere.

Specifically, FIGS. 5A to 5C are diagrams showing the amount of oxygen precipitates according to the gas injected during pre-annealing according to one embodiment of the present invention. FIG. 5A shows oxygen precipitates generated after pre-annealing in a nitrogen atmosphere followed by denuded zone (DZ) annealing. 5B shows oxygen precipitates generated after annealing in DZ (Denuded Zone) after pre-annealing in hydrogen atmosphere and FIG. 5C. Black dots in FIG. 5A to FIG. 5C indicate oxygen precipitates.

As shown in Figure 5a to 5c, it can be seen that the oxygen precipitates in the order of nitrogen> argon> hydrogen. In other words, when nitrogen gas is injected at the time of pre-annealing, more oxygen precipitates are generated and more metal contamination can be removed.

The pre-annealing step may be performed by any one of a rapid thermal annealing (RTA) method, a furnace annealing method, and a plasma treatment method. In addition, when pre-annealing is performed by the rapid heat treatment method or the furnace annealing method, pre-annealing is performed at 800 ° C to 1200 ° C. On the other hand, when pre-annealing is performed by a plasma treatment method, pre-annealing is performed at 600 ° C to 800 ° C.

After pre-annealing the wafer substrate 110, the wafer substrate 110 is annealed in a nitrogen atmosphere or a mixed gas atmosphere of nitrogen and oxygen (S230). Here, the annealing step is carried out in a Denimed Zone (DZ) annealing manner. Specifically, the annealing step includes a nucleation step of generating nuclei of oxygen precipitates and a growth step of growing the oxygen precipitates.

Nucleation step is carried out at 550 ℃ to 850 ℃. This is the process of generating nuclei for generating oxygen precipitates at relatively low temperatures. And the growth step is carried out at 900 ℃ to 1200 ℃. The growth stage is a process of growing a nucleus generated in the nucleation stage at a high temperature.

Through such an annealing process, metal precipitates are removed by generating oxygen precipitates on the wafer substrate 110. The characteristics and properties of the annealing process will be described in detail below with reference to FIGS. 3, 4, 6a, and 6b.

3 is a diagram illustrating oxygen precipitates formed in a wafer substrate when the wafer substrate is annealed in a nitrogen atmosphere or a mixed gas atmosphere of nitrogen and oxygen according to one embodiment of the present invention. That is, FIG. 3 corresponds to a photograph of a cross section of the wafer substrate 110 on which the DZ annealing is completed.

As shown in FIG. 3, the annealed wafer substrate 110 is separated into a denuded zone 210 and a region 220 where oxygen precipitates are generated. Here, the denuded zone 210 corresponds to a region where oxygen precipitates do not exist.

The amount of oxygen precipitates produced by the annealing process depends on the initial oxygen concentration of the wafer substrate 110, the temperature at which the annealing is performed, and the time at which the annealing is performed. This will be described with reference to FIGS. 4, 6A, and 6B.

4 is a view showing the degree of generation of oxygen precipitates by annealing according to the initial oxygen concentration according to an embodiment of the present invention. 4 shows the wafer substrate 110 having a higher initial oxygen concentration toward the right side.

As shown in FIG. 4, as the initial oxygen concentration of the wafer substrate 110 increases, more oxygen precipitates may be generated. Therefore, by increasing the initial oxygen concentration during the wafer substrate 110 manufacturing, it is possible to increase the amount of oxygen precipitates produced.

6A is a graph showing the nucleation rate of oxygen precipitates according to an annealing temperature according to an embodiment of the present invention. Specifically, Figure 6a is a diagram showing the rate of nucleation according to the temperature at which the nucleation step is performed during the DZ annealing process.

As shown in FIG. 6A, experiments were performed at 650 degrees Celsius, 750 degrees Celsius, and 850 degrees Celsius, and the nuclei of the most oxygen precipitates were produced at 750 degrees Celsius. Therefore, the nucleation step is carried out at 550 degrees Celsius to 850 degrees Celsius, it can be seen that the most oxygen precipitates occur when performed at 750 degrees Celsius.

6B is a graph showing the density of oxygen precipitates with time of annealing according to an embodiment of the present invention. FIG. 6B illustrates the density of oxygen precipitates according to annealing time for the wafer substrate 110 having an initial oxygen concentration of 8.2 PPM, 10.4 PPM, and 11.8 PPM, respectively.

6b, it can be seen that as the initial oxygen concentration is higher, more oxygen precipitates are produced. In addition, for a certain time interval, the longer the annealing time, the more oxygen precipitates are generated, and after that, it can be confirmed that the saturated state.

As such, it can be seen that the amount of generated oxygen precipitates in the annealing step depends on the initial oxygen concentration, the annealing temperature, and the annealing time. In addition, it was also confirmed that the amount of oxygen precipitates produced in the annealing step depends on whether or not pre-annealed.

Thereafter, the oxide film generated in the annealing step of the wafer substrate 110 is removed using an etching solution (S240). For example, the etching solution may be an aqueous HF solution or a buffered oxide etchant (BOE).

As such, by pre-annealing in an atmosphere such as nitrogen gas before annealing the wafer substrate 110, more oxygen precipitates are generated in the annealing step. In addition, the more oxygen precipitates are generated in the wafer substrate 110, the more metal ions can be removed during intrinsic gathering. In other words, by going through the pre-annealing step, a cleaner wafer substrate 110 free of metal contamination can be obtained.

However, it is a matter of course that the annealing step may be performed without passing through the pre-annealing step. However, when the pre-annealing step is not performed, less oxygen precipitates are generated in the wafer substrate 110.

Thereafter, at least one epitaxial layer is formed on the annealed substrate (S250). The epi layer may be one layer or two or more layers.

The epi layer may be formed using LPCVD (Low Plasma Chemical Vapor Deposition), UHVCVD (Ultra High Vacuum Chemical Vapor Deposition) or RPCVD (Remote Plasma Chemical Vapor Deposition) equipment.

In addition, at least one epi layer may be a high concentration epi layer or a low concentration epi layer, and both n-type and p-type are possible. That is, the epi layer may each be any one of a p ++ epi layer, a p + epi layer, a p− epi layer, an n ++ epi layer, an n + epi layer, and an n− epi layer.

At least one epi layer is formed under a pressure of 10-760 Torr at a temperature of 900 degrees Celsius to 1200 degrees Celsius. In addition, the formation process of each epi layer may be formed in-situ. When the epi layers are formed in-situ with each other, since the formation process of the two layers is connected by vacuum, it is possible to form each epi layer without forming an oxide film or the like between the two layers.

As in the manufacturing method described above, by annealing the wafer substrate 110 before forming the epi layer, it is possible to prevent the oxygen precipitates from penetrating into the epi layer. In addition, since the wafer substrate 110 is annealed after pre-annealing, more oxygen precipitates can be generated.

Through this process, it is possible to manufacture a clean epitaxial wafer with little metal contamination.

In addition, the epitaxial wafer manufacturing apparatus can manufacture the epitaxial wafer using the above-described manufacturing method.

Hereinafter, a process of manufacturing an epitaxial wafer by applying the manufacturing method of FIG. 2 will be described with reference to FIGS. 7A to 7D. 7A to 7D illustrate a process of manufacturing an epitaxial wafer including a p- wafer substrate, a p ++ epi layer, and a p- epi layer, according to an embodiment of the present invention.

As shown in FIG. 7A, first, a p− substrate 710 is prepared as a wafer substrate 110. Then, when the p-substrate 710 is pre-annealed in a first gas atmosphere, and then annealed in a nitrogen atmosphere or a mixed gas atmosphere of nitrogen and oxygen, oxygen is supplied to the p-substrate 710 as shown in FIG. 7B. Precipitates will be generated.

Thereafter, as shown in FIG. 7C, the p ++ epitaxial layer 720 is formed on the p− substrate 710 as the first epitaxial layer 120. As shown in FIG. 7D, the p− epi layer 730 is formed on the p ++ epi layer 720 as the second epi layer 130.

Through this process, it is possible to manufacture an epitaxial wafer composed of a p- substrate 710, a p + + epi layer 720, a p-epi layer 730. In addition, the epitaxial wafer thus manufactured contains almost no metal contaminants in the p ++ epitaxial layer 720 and the p− epitaxial layer 730. In addition, since the p ++ epitaxial layer 720 and the p- epi layer 730 of FIG. 7D can act as a p ++ substrate and a p- epi layer of a commercial epitaxial wafer, they can be used for the same purposes as commercial epitaxial wafers. It becomes possible.

Therefore, the epitaxial wafer manufactured through the above-described process can reduce the dark current or the number of defective pixels when used in the manufacture of a CMOS optical sensor or DRAM requiring a clean wafer.

Meanwhile, in the present exemplary embodiment, the annealing is performed after the pre-annealing process to generate oxygen precipitates on the p-substrate 710 of FIG. 7B. However, the present invention is not directly subjected to the pre-annealing process. It is of course possible to produce oxygen precipitates on the p- substrate.

Hereinafter, epitaxial wafers having various structures other than those of FIGS. 7A to 7D will be described. 8-12 show an epitaxial wafer comprising two epilayers.

8 is a diagram illustrating an epitaxial wafer including an n-wafer substrate 810, an n ++ epitaxial layer 820, and an n− epitaxial layer 830 according to an embodiment of the present invention. Here, the n- wafer substrate 810 is subjected to a pre-annealing step followed by an annealing step to generate more oxygen precipitates, thereby removing more metal contaminants. Therefore, the epitaxial wafer including the n- wafer substrate 810, the n ++ epitaxial layer 820, and the n- epitaxial layer 830 with less metal contamination may be manufactured using the manufacturing method of FIG.

9 is a diagram illustrating an epitaxial wafer including a p ++ wafer substrate 910, a p + epi layer 920, and a p − epi layer 930, according to an embodiment of the present disclosure. Here, the p ++ wafer substrate 910 undergoes a pre-anneal step followed by an anneal step to produce more oxygen precipitates, thereby removing more metal contaminants. Accordingly, the epitaxial wafer including the p ++ wafer substrate 910, the p + epitaxial layer 920, and the p − epitaxial layer 930 having less metal contamination may be manufactured using the manufacturing method of FIG. 2.

FIG. 10 is a diagram illustrating an epitaxial wafer including a p ++ wafer substrate 1010, a p + epi layer 1020, and an n− epi layer 1030, according to an embodiment of the present disclosure. Here, the p ++ wafer substrate 1010 is subjected to a pre-anneal step followed by an anneal step to produce more oxygen precipitates, thereby removing more metal contaminants. Therefore, by using the manufacturing method of FIG. 2, an epitaxial wafer composed of a p ++ wafer substrate 1010, a p + epilayer 1020, and an n− epilayer 1030 having less metal contamination may be manufactured.

FIG. 11 illustrates an epitaxial wafer including an n ++ wafer substrate 1110, an n + epitaxial layer 1120, and an n− epitaxial layer 1130, according to an embodiment of the present disclosure. Here, the n ++ wafer substrate 1110 is subjected to a pre-annealing step followed by an annealing step to generate more oxygen precipitates, thereby removing more metal contaminants. Accordingly, an epitaxial wafer composed of an n ++ wafer substrate 1110, an n + epitaxial layer 1120, and an n− epitaxial layer 1130 may be manufactured using the manufacturing method of FIG. 2.

FIG. 12 is a diagram illustrating an epitaxial wafer including an n ++ wafer substrate 1210, an n + epitaxial layer 1220, and a p− epitaxial layer 1230, according to an embodiment of the present disclosure. Here, the n ++ wafer substrate 1210 is subjected to a pre-anneal step followed by an anneal step to produce more oxygen precipitates, thereby removing more metal contaminants. Therefore, by using the manufacturing method of FIG. 2, an epitaxial wafer composed of an n ++ wafer substrate 1210, an n + epitaxial layer 1220, and a p − epitaxial layer 1230 may be manufactured.

In this manner, an epitaxial wafer including a wafer substrate and two epilayers can be produced.

Hereinafter, epitaxial wafers having a structure including a wafer substrate and one epitaxial layer will be described with reference to FIGS. 13 to 18.

FIG. 13 illustrates an epitaxial wafer including a p- wafer substrate 1310 and a p- epi layer 1320 according to an embodiment of the present invention. Here, the p- wafer substrate 1310 is subjected to an annealing step after the pre-annealing step, so that more oxygen precipitates are generated, thereby removing more metal contaminants. Therefore, by using the manufacturing method of FIG. 2, an epitaxial wafer composed of a p- wafer substrate 1310 and a p- epi layer 1320 with less metal contamination can be manufactured.

14 illustrates an epitaxial wafer composed of a p- wafer substrate 1410 and an n- epi layer 1420, according to one embodiment of the present invention. Here, the p- wafer substrate 1410 is subjected to a pre-annealing step followed by an annealing step to generate more oxygen precipitates, thereby removing more metal contaminants. Therefore, the epitaxial wafer composed of the p- wafer substrate 1410 and the n- epi layer 1420 with less metal contamination may be manufactured using the manufacturing method of FIG.

FIG. 15 is a diagram illustrating an epitaxial wafer composed of an n− wafer substrate 1510 and an n− epilayer 1520 according to an embodiment of the present invention. Here, the n- wafer substrate 1510 is subjected to a pre-annealing step followed by an annealing step to generate more oxygen precipitates, thereby removing more metal contaminants. Therefore, the epitaxial wafer formed of the n- wafer substrate 1510 and the n- epi layer 1520 with little metal contamination can also be manufactured using the manufacturing method of FIG.

FIG. 16 illustrates an epitaxial wafer composed of an n− wafer substrate 1610 and a p− epi layer 1620 according to an embodiment of the present invention. Here, the n- wafer substrate 1610 is subjected to a pre-annealing step followed by an annealing step to generate more oxygen precipitates, thereby removing more metal contaminants. Therefore, the epitaxial wafer formed of the n- wafer substrate 1610 and the p- epi layer 1620 with little metal contamination can also be manufactured using the manufacturing method of FIG.

FIG. 17 illustrates an epitaxial wafer composed of a p ++ wafer substrate 1710 and a p− epi layer 1720 according to an embodiment of the present invention. Here, the p ++ wafer substrate 1710 is subjected to a pre-anneal step followed by an anneal step to produce more oxygen precipitates, thereby removing more metal contaminants. Therefore, an epitaxial wafer composed of a p ++ wafer substrate 1710 and a p− epi layer 1720 with less metal contamination may be manufactured using the manufacturing method of FIG. 2.

FIG. 18 illustrates an epitaxial wafer comprised of an n ++ wafer substrate 1810 and an n− epi layer 1820 according to one embodiment of the invention. Here, the n ++ wafer substrate 1810 undergoes a pre-annealing step followed by an annealing step to produce more oxygen precipitates, thereby removing more metal contaminants. Therefore, by using the manufacturing method of FIG. 2, an epitaxial wafer composed of an n ++ wafer substrate 1810 and an n− epilayer 1820 having less metal contamination may be manufactured.

In this manner, an epitaxial wafer including a wafer substrate and one epitaxial layer may be manufactured.

Hereinafter, an epitaxial wafer including a wafer substrate and three epi layers will be described with reference to FIGS. 19 to 22.

FIG. 19 illustrates an epitaxial wafer comprised of a p− wafer substrate 1910, a p ++ epilayer 1920, a p + epilayer 1930, and a p− epilayer 1940, in accordance with an embodiment of the present invention. to be. Here, the p- wafer substrate 1910 is subjected to a pre-anneal step followed by an anneal step to generate more oxygen precipitates, thereby removing more metal contaminants. Accordingly, by using the manufacturing method of FIG. 2, an epitaxial wafer composed of a p- wafer substrate 1910, a p ++ epitaxial layer 1920, a p + epitaxial layer 1930, and a p− epitaxial layer 1940 is formed. It can also manufacture.

20 illustrates an epitaxial wafer including a p− wafer substrate 2010, a p ++ epitaxial layer 2020, a p + epitaxial layer 2030, and an n− epitaxial layer 2040, according to one embodiment of the invention. to be. Here, the p- wafer substrate 2010 undergoes a pre-annealing step followed by an annealing step to produce more oxygen precipitates, thereby removing more metal contaminants. Therefore, by using the manufacturing method of FIG. 2, an epitaxial wafer composed of a p- wafer substrate 2010, a p ++ epitaxial layer 2020, a p + epitaxial layer 2030, and an n− epitaxial layer 2040 having low metal contamination is fabricated. It can also manufacture.

FIG. 21 illustrates an epitaxial wafer composed of an n− wafer substrate 2110, an n ++ epitaxial layer 2120, an n + epitaxial layer 2130, and an n− epitaxial layer 2140, in accordance with an embodiment of the present invention. to be. Here, the n- wafer substrate 2110 is subjected to a pre-annealing step followed by an annealing step to generate more oxygen precipitates, thereby removing more metal contaminants. Therefore, by using the manufacturing method of FIG. 2, an epitaxial wafer composed of an n− wafer substrate 2110, an n ++ epitaxial layer 2120, an n + epitaxial layer 2130, and an n− epitaxial layer 2140 having low metal contamination is fabricated. It can also manufacture.

FIG. 22 illustrates an epitaxial wafer comprised of an n− wafer substrate 2210, an n ++ epilayer 2220, an n + epilayer 2230, and a p− epilayer 2240, according to one embodiment of the invention. to be. Here, the n- wafer substrate 2110 is subjected to a pre-annealing step followed by an annealing step to generate more oxygen precipitates, thereby removing more metal contaminants. Therefore, by using the manufacturing method of FIG. 2, an epitaxial wafer composed of an n− wafer substrate 2210, an n ++ epitaxial layer 2220, an n + epitaxial layer 2230, and a p− epitaxial layer 2240 having low metal contamination is fabricated. It can also manufacture.

In this manner, an epitaxial wafer having a structure including a wafer substrate and three epilayers may be manufactured.

An epitaxial wafer manufactured in accordance with various embodiments of the present invention may be used in the manufacture of various semiconductor devices. For example, the present invention can be used to manufacture a charge coupled device (CCD), a CMOS image sensor (CIS), an LCD driver IC (LDI) device, various system ICs, direct random access memory (DRAM), and a flash memory device.

In addition, although the preferred embodiment of the present invention has been shown and described above, the present invention is not limited to the specific embodiments described above, but the technical field to which the invention belongs without departing from the spirit of the invention claimed in the claims. Of course, various modifications can be made by those skilled in the art, and these modifications should not be individually understood from the technical spirit or the prospect of the present invention.

1 is a cross-sectional view of an epitaxial wafer, in accordance with an embodiment of the present invention;

2 is a flowchart illustrating an epitaxial wafer manufacturing method according to an embodiment of the present invention;

3 is a diagram illustrating oxygen precipitates formed in a wafer substrate when the wafer substrate is annealed in a nitrogen atmosphere or a mixed gas atmosphere of nitrogen and oxygen according to one embodiment of the present invention;

4 is a view showing the degree of generation of oxygen precipitates by annealing according to the initial oxygen concentration, according to an embodiment of the present invention,

5A illustrates the amount of oxygen precipitates in a wafer substrate when pre-annealed in a nitrogen atmosphere, in accordance with one embodiment of the present invention;

5B illustrates the amount of oxygen precipitates in a wafer substrate when pre-annealed in an argon atmosphere, in accordance with one embodiment of the present invention;

5C illustrates the amount of oxygen precipitates on a wafer substrate when pre-annealed in a hydrogen atmosphere, in accordance with one embodiment of the present invention;

Figure 6a is a graph showing the density of the production of the nucleus of oxygen precipitates according to the annealing temperature, according to an embodiment of the present invention,

6b is a graph showing the density of oxygen precipitates with time of annealing, according to an embodiment of the invention;

7A to 7D illustrate a process of manufacturing an epitaxial wafer including a p- wafer substrate, a p ++ epi layer, and a p- epi layer, according to an embodiment of the present invention;

8 illustrates an epitaxial wafer composed of an n- wafer substrate, an n ++ epi layer, and an n- epi layer, according to an embodiment of the present invention;

9 illustrates an epitaxial wafer composed of a p ++ wafer substrate, a p + epi layer, and a p− epi layer, according to an embodiment of the present invention;

FIG. 10 illustrates an epitaxial wafer composed of a p ++ wafer substrate, a p + epi layer, and an n− epi layer, according to an embodiment of the present invention; FIG.

FIG. 11 illustrates an epitaxial wafer composed of an n ++ wafer substrate, an n + epilayer, and an n− epilayer, in accordance with an embodiment of the present invention; FIG.

12 illustrates an epitaxial wafer composed of an n ++ wafer substrate, an n + epi layer, and a p− epi layer, according to an embodiment of the present invention;

FIG. 13 illustrates an epitaxial wafer composed of a p- wafer substrate and a p- epi layer, according to an embodiment of the present invention;

14 illustrates an epitaxial wafer composed of a p- wafer substrate and an n- epi layer, according to an embodiment of the present invention;

15 illustrates an epitaxial wafer composed of an n- wafer substrate and an n- epi layer, according to an embodiment of the present invention;

16 illustrates an epitaxial wafer composed of an n- wafer substrate and a p- epi layer, according to an embodiment of the present invention;

FIG. 17 illustrates an epitaxial wafer composed of a p ++ wafer substrate and a p− epi layer, according to an embodiment of the present invention; FIG.

18 illustrates an epitaxial wafer composed of an n ++ wafer substrate and an n− epilayer, according to an embodiment of the present invention;

19 illustrates an epitaxial wafer composed of a p- wafer substrate, a p ++ epitaxial layer, a p + epitaxial layer, and a p- epitaxial layer, according to an embodiment of the present invention;

FIG. 20 illustrates an epitaxial wafer composed of a p- wafer substrate, a p ++ epi layer, a p + epi layer, and an n- epi layer, according to an embodiment of the present invention;

21 illustrates an epitaxial wafer composed of an n− wafer substrate, an n ++ epitaxial layer, an n + epitaxial layer, and an n− epitaxial layer, according to an embodiment of the present invention;

FIG. 22 illustrates an epitaxial wafer including an n− wafer substrate, an n ++ epitaxial layer, an n + epitaxial layer, and a p− epitaxial layer, according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

110 wafer substrate 120 first epi layer

130: second epi layer

Claims (20)

Preparing a wafer substrate having a first doping concentration; A pre-anneal step of annealing the wafer substrate in an atmosphere of a first gas; Annealing the pre-annealed wafer substrate in a nitrogen atmosphere or a mixed gas atmosphere of nitrogen and oxygen; And Forming at least one epitaxial layer on the annealed wafer substrate. The method of claim 1, The first gas, An epitaxial wafer manufacturing method comprising at least one gas selected from the group consisting of nitrogen (N ₂ ), argon (Ar) and hydrogen (H ₂ ). The method of claim 2, The first gas, An epitaxial wafer manufacturing method further comprising oxygen. The method of claim 1, The pre-annealing step, Epitaxial wafer manufacturing method characterized in that performed by any one of a rapid thermal annealing (RTA) method, furnace (Furnace) annealing method and plasma (Plasma) processing method. The method of claim 4, wherein The pre-annealing step, When the rapid thermal annealing (RTA) method or the furnace (Furnace) annealing method, epitaxial wafer manufacturing method characterized in that performed at 800 ℃ to 1200 ℃. The method of claim 4, wherein The pre-annealing step, When performed by the plasma (Plasma) processing method, epitaxial wafer manufacturing method characterized in that performed at 600 ℃ to 800 ℃. The method of claim 1, The annealing step, A nucleation step of generating nuclei of oxygen precipitates; And And a growth step of growing the oxygen precipitates. The method of claim 7, wherein The nucleation step, Epitaxial wafer manufacturing method characterized in that carried out at 550 ℃ to 850 ℃. The method of claim 7, wherein The growth stage, Epitaxial wafer manufacturing method characterized in that carried out at 900 ℃ to 1200 ℃. The method of claim 1, The annealing step, DZ (Denuded Zone) epitaxial wafer manufacturing method characterized in that performed in an annealing manner. The method of claim 1, And removing the oxide film generated in the annealing step after the annealing step. The method of claim 11, The oxide film removing step, An epitaxial wafer manufacturing method comprising removing an oxide film using an etching solution. The method of claim 1, The epi layer forming step, And forming a first epitaxial layer having a second doping concentration on the wafer substrate. The method of claim 13, The epi layer forming step, Forming a second epitaxial layer having a third doping concentration on the first epitaxial layer; epitaxial wafer manufacturing method further comprising. The method of claim 14, The second doping concentration of the first epitaxial layer is higher than the first doping concentration, And a third doping concentration of the second epitaxial layer is lower than the second doping concentration. The method of claim 14, Wherein the first epitaxial layer forming step and the second epitaxial layer forming step are performed in-situ with each other. The method of claim 14, The epi layer forming step, And forming a third epitaxial layer having a fourth doping concentration on the second epitaxial layer. The method of claim 17, And the third epitaxial layer forming step is performed in-situ with the second epitaxial layer forming step. An epitaxial wafer manufactured using the epitaxial wafer manufacturing method according to any one of claims 1 to 18. A semiconductor device manufactured using an epitaxial wafer manufactured using the epitaxial wafer manufacturing method of any one of claims 1 to 18.

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