KR20100025218A - Semiconductor device and fabricating method thereof - Google Patents

Abstract

PURPOSE: A semiconductor device and a method for manufacturing the same are provided to reduce the generation of noise signal by maintaining conductive wires with a constant length. CONSTITUTION: A substrate(110) includes an insulation layer(111), a land(112) which is exposed to the lower surface of the insulation layer and a redistribution layer(113). One end of the redistribution layer is electrically connected to the land through the insulating layer. The other end of the redistribution layer is routed along the upper side of the insulating layer. A semiconductor die(120) is attached on the upper side of the substrate. A conductive wire(130) electrically connected to the redistribution layer and the semiconductor die. An encapsulant(140) is formed on the upper side of the substrate to cover the semiconductor die.

Description

Semiconductor Device and Fabrication Method Thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to easily dissipate heat from a semiconductor die to the outside, and to have excellent electrical performance, to be small in size and thin in thickness, and to route wire bonding pad positions. A semiconductor device and a method of manufacturing the same.

As society becomes more advanced, a large number of semiconductor devices are used for electronic products. In addition, while it is required to reduce the size and thickness of the product, it is required to increase the electrical thermal performance and the number of input output terminals.

In the case of Ball Grid Arrays (BGAs), which are widely used in the field of semiconductor devices, multilayer PCB substrates are used. In the case of the PCB substrate, since the multilayer structure is possible, the wire bonding pad position can be routed using the redistribution layer, thereby reducing the length of the bonded wire and increasing the number of input / output terminals. However, there is a disadvantage in that the heat dissipation performance is low due to the substrate structure.

On the other hand, in the case of the lead frame substrate, the die attach pad is made of copper having excellent heat dissipation performance, and has a heat dissipation performance because the structure can be easily dissipated to the outside of the semiconductor device. However, there are disadvantages in that the size and thickness of the semiconductor device are large and there is a limit in increasing the number of input / output terminals.

In order to solve the shortcomings of the recent lead frame substrate, the copper plate is plated to implement patterns for input / output terminals, die attach pads, wire bonding pads, and the like, and then the copper plate is subjected to semiconductor die attach, wire bonding, and encapsulation. Substrate and semiconductor manufacturing processes are being developed that can be removed by etching to maintain high heat dissipation performance and can dramatically increase the number of input / output terminals. However, this substrate has a fatal disadvantage in that routing is impossible and the wire bonding length is greatly increased. Currently, gold is mostly used as a wire material, and as the wire bonding length increases, manufacturing cost increases significantly.

SUMMARY OF THE INVENTION The present invention is to overcome the above-mentioned conventional problems, and an object of the present invention is to easily dissipate heat from a semiconductor die to the outside, and to have excellent electrical performance while being small in size and thin, and capable of routing bonding pad positions. The present invention provides a semiconductor device and a method of manufacturing the same.

In order to achieve the above object, a semiconductor device according to the present invention includes an insulating layer, a land exposed to a lower surface of the insulating layer, one end of which is electrically connected to the land by passing through the insulating layer with the same cross-sectional area as the land, and the other end thereof. A substrate comprising a redistribution layer routed along an upper surface of the insulating layer, a semiconductor die affixed on top of the substrate, a conductive wire electrically connecting the redistribution layer and the semiconductor die, and to surround the semiconductor die It may include an encapsulant formed on the substrate.

Here, the insulating layer may be formed of a solder mask.

The land may include a first metal layer exposed to the bottom surface of the insulating layer and a second metal layer formed on the first metal layer.

In addition, the first metal layer may be made of gold, and the second metal layer may be made of nickel.

In addition, the redistribution layer may be made of copper.

In addition, one end of the redistribution layer may be formed at the same height as the insulating layer, and the other end of the redistribution layer may be formed to extend around the semiconductor die along an upper surface of the insulating layer.

In addition, a bonding layer protruding from the redistribution layer may be further formed on the other end of the redistribution layer.

In addition, the bonding layer may include a first metal layer formed on the redistribution layer and a second metal layer formed on the first metal layer.

In addition, the first metal layer of the bonding layer may be formed of nickel, and the second metal layer may be formed of at least one selected from gold, silver, and palladium / gold.

In addition, the substrate may further include a heat dissipation layer formed to correspond to the lower portion of the semiconductor die.

In addition, a bonding layer may be further formed on the heat dissipation layer of the substrate.

The bonding layer of the heat dissipation layer may include a first metal layer formed on the heat dissipation layer and a second metal layer formed on the first metal layer, wherein the first metal layer is made of nickel, and the second metal layer is Stir selected from gold, silver and palladium / gold can be made of either.

In addition, a land exposed to the lower surface of the substrate may be further formed under the heat dissipation layer.

In addition, at least one of the redistribution layer may be formed while filling the insulating layer only on the upper portion of the land, and a bonding layer may be further formed on the redistribution layer.

In addition, in order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes an insulating layer, a land exposed to the lower surface of the insulating layer, one end of which is electrically connected to the land by passing through the insulating layer with the same cross-section as the land. A substrate comprising a redistribution layer connected at the other end and routed along an upper surface of the insulating layer, the substrate having a substrate attached to an upper portion of the metal carrier, and a semiconductor attaching a semiconductor die to the upper portion of the substrate. A die attaching step, a wire bonding step of electrically connecting the substrate and the semiconductor die by bonding a conductive wire, an encapsulation step of forming an encapsulant on the substrate to surround the semiconductor die, and the And removing the metal carrier to remove the metal carrier. Can be.

The substrate providing step may include a metal carrier providing the plate-shaped metal carrier, an insulating layer forming step of forming a patterned insulating layer on the metal carrier, and a land between the patterns of the insulating layer. Forming a land, forming a seed layer by plating a metal on the insulating layer and the land, and forming a DFR (Dry Film Resist) on the seed layer; The method may include an electroplating step of forming a pre-rewiring layer by electroplating using the seed layer, a DFR removal step of removing the DFR, and a flash etching step of forming a redistribution layer by flash etching the pre-rewiring layer. .

Further, between the electrolytic plating step and the DFR removing step, an auxiliary DFR forming step of forming an auxiliary DFR on the preliminary redistribution layer and a bonding layer forming step of forming a bonding layer by plating between the auxiliary DFRs are further performed. Can be done.

In addition, the step of providing the metal carrier may be provided with the metal carrier made of a copper material.

In addition, the land forming step may be to form a first metal layer formed of gold between the insulating layer, and to form a second metal layer formed of nickel on the first metal layer.

In addition, the seed layer forming step may be made of electroless plating.

In addition, the electrolytic plating step may be to form the pre-redistribution layer by plating copper on the exposed top of the seed layer using an electrolytic plating method.

In addition, the bonding layer forming step may be to form the bonding layer on the exposed top of the DFR and the auxiliary DFR.

The bonding layer forming step may be to form the bonding layer by forming a first metal layer formed on the preliminary redistribution layer and a second metal layer on the first metal layer.

In addition, the flash etching step may be to form the redistribution layer electrically independent of each other by etching the pre-rearrangement layer made of copper.

As described above, the semiconductor device according to the present invention includes a redistribution layer in which one end is connected to a land and the other end is rewired to the upper surface of the insulating layer so that the semiconductor device extends to the periphery of the semiconductor die. It is possible to keep the noise signal from being generated, and to reduce the manufacturing cost by reducing the length of the conductive wire.

In addition, the semiconductor device according to the present invention can be provided with a larger number of lands because the position of the land is independent of the length of the conductive wire.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the present invention.

Hereinafter, the configuration of the semiconductor device 100 according to an embodiment of the present invention will be described.

1A is a plan view illustrating a substrate 110 used in a semiconductor device 100 according to an embodiment of the present invention. 1B is a bottom view illustrating the substrate 110 used in the semiconductor device 100 according to an embodiment of the present invention. FIG. 1C is a cross-sectional view of the semiconductor device 100 according to an exemplary embodiment of the present invention and is developed in the direction of AA ′ of FIG. 1A.

1A to 1C, a semiconductor device 100 according to an exemplary embodiment may include a substrate 110, a semiconductor die 120 attached to an upper portion of the substrate 110, and the substrate ( A conductive wire 130 connecting the 110 and the semiconductor die 120 includes an encapsulant 140 formed to surround the semiconductor die 120.

The substrate 110 provides a basis for the semiconductor device 100 according to an embodiment of the present invention. The substrate 110 is generally provided in a substantially flat shape in the horizontal direction. The substrate 110 has an upper portion connected to the semiconductor die 120, and a lower portion connected to a solder ball or a printed circuit board (PCB, not shown) and the like.

The substrate 110 is connected to the insulating layer 111 formed flat in the horizontal direction, a plurality of lands 112 exposed to the bottom surface of the insulating layer 111, and the lands 112 and the insulating layer 111. It includes a plurality of redistribution layer 113 extending along the upper surface of the), the bonding layer 114 formed on the redistribution layer 113. In addition, the substrate 110 may include a central land 115 formed at an approximately center region of the insulating layer 111, a heat dissipation layer 116 formed on the center land 115, and a heat dissipation layer 116. It may further include a center bonding layer 117 formed on the top.

The insulating layer 111 is formed flat in the horizontal direction. In addition, the insulating layer 111 is formed in a pattern. The insulating layer 111 is formed of an electrically insulating material. To this end, the insulating layer 111 may be formed as a solder mask or a solder mask of a film type. The insulating layer 111 forms a basis for providing the substrate 110 of the semiconductor device 100 according to an embodiment of the present invention.

The land 112 is formed between the patterns of the insulating layer 111. The land 112 is exposed to the bottom surface of the insulating layer 111. Therefore, the land 112 may be electrically connected to a solder ball (not shown) or an external printed circuit board (not shown) through the lower surface of the insulating layer 111.

In addition, the land 112 may include a first metal layer 112a exposed to the bottom surface of the insulating layer 111 and a second metal layer 112b formed on the first metal layer 112a. The first metal layer 112a is directly connected to the solder ball or the PCB. The first metal layer 112a may be formed using gold, which is widely used for surface mounting plating of semiconductor devices. The second metal layer 112b is formed on the first metal layer 112a. The second metal layer 112b may be formed using nickel to prevent copper diffusion.

The redistribution layer 113 is electrically connected to the land 112. One end of the redistribution layer 113 is formed to have the same cross-sectional area as the land 112 and penetrates the insulating layer 111. The redistribution layer 113 may contact the second land 112b of the land 112. One end of the redistribution layer 113 is connected to the land 112, and the other end thereof is patterned along the upper surface of the insulating layer 111.

The redistribution layer 113 is formed such that the other end reaches the periphery of the semiconductor die 120. That is, the redistribution layer 113 redistributes an electrical path connected to the land 112 to the periphery of the semiconductor die 120. In addition, the redistribution layer 113 may be redistributed so that the distance from the semiconductor die 120 to the redistribution layer 113 is maintained constant. Therefore, the conductive wire 130 reaching from the semiconductor die 120 to the redistribution layer 113 may be formed to have a constant length regardless of the position of the land 112. As a result, the land 112 may be provided in plurality because the position is not limited in the substrate 110. In addition, since the conductive wire 130 only needs to be formed up to the redistribution layer 113, not the land 112, the length of the conductive wire 130 can be reduced compared to the existing one, and the conductive wire 130 can be formed in the same length. It is possible to lower the manufacturing cost of the. In addition, since the conductive wire 130 may be formed in the shortest path, the noise signal through the conductive wire 130 may be reduced.

The bonding layer 114 is formed on the redistribution layer 113. The bonding layer 114 is formed on the other end of the redistribution layer 113. The bonding layer 114 is formed to improve the bonding force between the conductive wire 130 and the redistribution layer 113. To this end, the bonding layer 114 may include a first metal layer 114a formed on the redistribution layer 113 and a second metal layer 114b formed on the first metal layer 114a. In addition, the first metal layer 114a may be formed of nickel, and the second metal layer 114b may be formed of at least one selected from gold, silver, and palladium / gold.

The central land 115 may be formed in an area corresponding to the semiconductor die 120 of the substrate 110. The central land 115 is formed between the patterns of the insulating layer 111. In addition, the central land 115 is exposed through the lower surface of the substrate 110. The central land 115 may include a first metal layer 115a exposed through the bottom surface of the substrate 110 and a second metal layer 115b formed on the first metal layer 115b. The first metal layer 115a may be formed of gold, and the second metal layer 115b may be formed of nickel.

The heat dissipation layer 116 may be formed on the central land 115. The heat dissipation layer 116 may be provided in a plate shape formed along the upper surface of the central land 115. The heat dissipation layer 116 is in surface contact with the semiconductor die 120 attached thereon. In addition, the heat dissipation layer 116 is formed of a copper material to easily absorb the heat of the semiconductor die 120, and dissipates the heat through the central land (115). In addition, the heat dissipation layer 116 may form an electrical connection path connected to the central land 115 to provide a path for applying a voltage to the semiconductor die 120. In addition, the voltage may be a ground voltage. Therefore, the heat dissipation layer 116 can stably supply the ground voltage to the semiconductor die 120.

The center bonding layer 117 may be formed on the heat dissipation layer 116. The center bonding layer 117 is formed between the electrical paths of the semiconductor die 120 and the heat dissipation layer 116 to facilitate coupling of the heat dissipation layer 116 to the conductive wire 130. The center bonding layer 117 may include a first metal layer 117a disposed above the heat dissipation layer 116 and a second metal layer 117b disposed above the first metal layer 117a. In this case, the first metal layer 117a may be formed of nickel, and the second metal layer 117b may be formed of at least one selected from gold, silver, and palladium / gold.

The semiconductor die 120 is attached to the top of the substrate 110. The semiconductor die 120 is positioned at an approximately center upper portion of the substrate 110, and a bottom surface thereof is attached to the substrate 110 through an adhesive 121. The semiconductor die 120 has a plurality of bond pads 122 formed thereon. Although the bond pad 122 is illustrated as protruding from the top surface of the semiconductor die 120, the bond pad 122 may be formed inside the semiconductor die 120.

The conductive wire 130 electrically connects the substrate 110 and the semiconductor die 120. The conductive wire 130 electrically connects the bonding layer 114 of the substrate 110 and the bond pad 122 of the semiconductor die 120. The conductive wire 130 electrically connects the center bonding layer 117 and the bond pad 122 of the semiconductor die 120.

The encapsulant 140 is formed on the substrate 110 to surround the semiconductor die 120 and the conductive wire 130. The encapsulant 140 protects the semiconductor die 120 and the conductive wire 130 from external shock. The encapsulant 140 uses an electrical insulation material, and is generally formed of an epoxy resin. However, the material of the encapsulant 140 is not limited to the contents of the present invention.

As described above, in the semiconductor device 100 according to the exemplary embodiment of the present invention, a redistribution layer in which one end is connected to the land 112 and the other end of the semiconductor device 100 is redistributed to the upper surface of the insulating layer 111 is formed. By providing the 113 to extend to the periphery of the semiconductor die 120, the length of the conductive wire 130 is kept constant to reduce the occurrence of noise signals. In addition, the manufacturing cost can be reduced by reducing the length of the conductive wire 130. In addition, since the location of the land 112 is not limited to the length of the conductive wire 130, more lands 112 may be provided.

Hereinafter, the configuration of the semiconductor device 200 according to another embodiment of the present invention will be described.

2 is a cross-sectional view illustrating a semiconductor device 200 according to another embodiment of the present invention. Parts having the same configuration and operation have been given the same reference numerals and will be described below with focus on differences.

As shown in FIG. 2, a semiconductor device 200 according to another embodiment of the present invention includes a substrate 210, a semiconductor die 120, a conductive wire 130, and an encapsulant 140.

The substrate 210 includes an insulating layer 111, a land 112, a redistribution layer 113, a bonding layer 114, a central land 115, a heat dissipation layer 116, a central bonding layer 117, and An inner redistribution layer 213 formed on the land 112 and an inner bonding layer 214 formed on the inner redistribution layer 213 are included.

One end of the inner redistribution layer 213 is connected to the land 112, and the other end thereof is electrically connected to the semiconductor die 120. The inner redistribution layer 213 may be formed at the same height as the insulating layer 111. In this case, the inner redistribution layer 213 may be formed on the land 112 adjacent to the semiconductor die 120 among the lands 112. That is, the inner redistribution layer 213 is formed while filling the insulating layer 111. Therefore, the inner redistribution layer 213 adjacent to the semiconductor die 120 may not be redistributed, thereby reducing the amount of metal forming the inner redistribution layer 213. In addition, since the land 112 may be adjacent to the semiconductor die 120, more lands 112 may be provided.

The inner bonding layer 214 may be formed on the inner redistribution layer 213. The inner bonding layer 214 may be formed in an unrewired region of the inner redistribution layer 213. The inner bonding layer 214 may be formed to include a first metal layer 214a and a second metal layer 214b. The first metal layer 214a may be nickel, and the second metal layer 214b may be gold or silver. And palladium / gold.

As described above, in the semiconductor device 200 according to another exemplary embodiment of the present invention, the land 112 may be formed on the semiconductor die 120 by preventing the inner redistribution layer 213 from filling the insulating layer 111. It can be located closer. Therefore, the semiconductor device 200 according to another exemplary embodiment of the present invention may include a larger number of lands 112 and reduce manufacturing costs by reducing metal forming the redistribution layer 113.

Hereinafter, a method of manufacturing the semiconductor device 100 according to an embodiment of the present invention will be described.

3A is a flowchart for describing a method of manufacturing the semiconductor device 100 according to an embodiment of the present invention. FIG. 3B is a flowchart for describing in detail the substrate providing step S1 of the method of manufacturing the semiconductor device 100 according to the exemplary embodiment of the present inventive concept. 4A to 4N are cross-sectional views illustrating a method of manufacturing the semiconductor device 100 in accordance with an embodiment of the present invention.

Referring to FIG. 3A, a method of manufacturing a semiconductor device 100 according to an embodiment of the present invention may include a substrate providing step S1, a semiconductor die attaching step S3, a wire bonding step S5, and an encapsulation step. (S7), the metal carrier removing step (S9). Hereinafter, each step of FIG. 3A will be described with reference to FIGS. 4A to 4N.

The substrate providing step (S1) is a step of providing a substrate that is the basis of the semiconductor device 100 according to an embodiment of the present invention. Referring to FIG. 3B, the substrate providing step S1 includes a metal carrier providing step S11, an insulating layer forming step S12, a land forming step S13, a seed layer forming step S14, and a DFR forming step. (S15), electrolytic plating step (S16), DFR removal step (S19), flash etching step (S20). In addition, an auxiliary DFR forming step S17 and a bonding layer forming step S18 may be further formed between the electrolytic plating step S16 and the DFR removing step S19.

Referring to FIGS. 3B and 4A, a metal carrier providing step S11 including a plate-shaped metal carrier 10 made of metal is performed. The metal carrier 10 may serve as a steel sheet for manufacturing the semiconductor device 100 according to an embodiment of the present invention, or may be used as a seed layer of electroplating. The metal carrier 10 may be formed of copper.

3B and 4B, an insulating layer forming step S12 of forming an insulating layer 111 on the metal carrier 10 is performed. The insulating layer 111 is made of an electrically insulating material. The insulating layer 111 may be formed of a conventional solder mask. The insulating layer 111 is formed in a pattern. That is, the film-type solder mask may be laminated on the metal carrier 10, and then the insulating layer 111 may be formed through exposure, development, and curing processes. Therefore, a structure such as a land and a redistribution layer may be formed while filling the patterns of the insulating layer 111.

In the insulating layer forming step S12, a dry film resist (DFR) 20 may be formed on the bottom surface of the metal carrier 10. Therefore, the metal is prevented from being plated on the lower surface of the metal carrier 10 in the subsequent land forming process.

3B and 4C, a land forming step S13 of forming a land 112 by plating a metal between the patterns of the insulating layer 111 is performed. In this case, an electroplating method may be used as the plating method, and the metal carrier 10 may be used as a seed layer of electroplating. In addition, the land 112 may include a first metal layer 112a formed on the metal carrier 10 and a second metal layer 112b formed on the first metal layer 112a. In this case, the first metal layer 112a may be formed of gold, which is widely used for surface mounting of a semiconductor device, and the second metal layer 112b may be formed using nickel to prevent copper diffusion. . At this time, copper may be further plated directly on the second metal layer 112b. Therefore, oxidation on the surface of the nickel layer forming the second metal layer 112b can be prevented.

Referring to FIGS. 3B and 4D, a seed layer forming step S14 is performed to plate the metal on the insulating layer 111 and the land 112 to form the seed layer 31. Electroless plating may be used as the plating method. The seed layer 31 is entirely formed on the insulating layer 111 and the land 112, and is then used as a seed layer of electroplating for forming a redistribution layer. At this time, the seed layer 31 may be formed using copper, which is the same material as the metal forming the redistribution layer.

3B and 4E, a DFR forming step (S15) of forming a DFR 40 on the seed layer 31 is performed. The DFR 40 is applied in the form of a film on top of the seed layer 31. After the DFR 40 is applied on the seed layer 31, the DFR 40 may further include a pattern through exposure, development, and the like. Since the DFR 40 is electrically insulated, when the redistribution layer is formed through the electroplating method, the metal part is not plated by the part covered by the DFR 40.

Referring to FIGS. 3B and 4F, electroplating using the seed layer 31 to form a preliminary redistribution layer 32 in which a portion of the seed layer 31 is thickened (S16). ) Is done. The preliminary redistribution layer 32 may be formed by plating copper on the seed layer 31 having the same material as the seed layer 31. Of course, at this time, plating is not performed in the region of the seed layer 31 covered by the DFRs 20 and 40. In addition, the preliminary redistribution layer 32 until the electrolytic plating step S16 has a structure electrically connected to each other due to the configuration of the seed layer 31.

3B and 4G, the auxiliary DFR forming step S17 is performed to form the auxiliary DFR 50 on an upper portion of the preliminary redistribution layer 32 and the DFR 40. The auxiliary DFR 50 is made of the same method and material as the DFR 40, the auxiliary DFR 50 is also applied over the upper front surface of the pre-redistribution layer 32 and DFR 40, Patterned through exposure and development. The auxiliary DFR 50 is then formed only in the region except for the region where the bonding layer 114 and the center bonding layer 116 are formed.

3B and 4H, a bonding layer forming step (S18) is performed to form a bonding layer 114 by plating a metal between the patterns of the auxiliary DFR 50. As a method of plating a metal on the pattern of the auxiliary DFR 50, an electroplating method may be performed. In this case, the pre-distribution layer 32 may be used as a seed layer. In order to form the bonding layer 114, first, a first metal layer 114a is formed by plating nickel on the redistribution layer 32, and gold, silver, and palladium on the first metal layer 114a. At least one selected from / gold may be plated to form the second metal layer 114b.

3B and 4I, a DFR removal step S19 for removing the DFR 40 and the auxiliary DFR 50 is performed. In addition, the DFR removal step (S19) is also removed with the DFR (20) formed on the lower surface of the metal carrier (10).

3B and 4J, a flash etching step (S20) of performing a flash etching of the pre-distribution layer 32 to form a redistribution layer 113 used in the semiconductor device 100 according to an embodiment of the present invention. Is done. The flash etching is performed by selectively etching the copper components constituting the preliminary redistribution layer 32, and as a result, the redistribution layer 32 is etched from the top. Thus, the formed redistribution layer 113 may be electrically independent of each other patterned. In addition, as described above, the substrate 110 used in the semiconductor device 100 according to the exemplary embodiment of the present invention is formed.

3A and 4K, a semiconductor die attaching step S3 is performed to attach the semiconductor die 120 to the upper portion of the substrate 110. The semiconductor die 120 is attached to the center of the substrate 110 using an adhesive 121. In addition, the semiconductor die 120 may be attached to an upper portion of the heat dissipation layer 116 among the substrate 110.

3A and 4L, a wire bonding step S5 is performed to electrically connect the substrate 110 and the semiconductor die 120 through the conductive wire 130. One end of the conductive wire 130 forms a ball bonding layer 131 on the bond pad 122 of the semiconductor die 120, and then a stitch bonding layer 132 on the bonding layer 114 of the substrate 110. It can be formed using a forward folded loop method forming a). In addition, although not separately illustrated, the conductive wire 130 is provided with a ball bonding layer in advance in the bonding layer 114 of the substrate 110, and ball bonding of the bond pad 122 of the semiconductor die 120. It may also be formed using a backward folded loop scheme that connects the layers.

3A and 4M, an encapsulation step (S7) of forming an encapsulant 140 on the substrate 110 to surround the semiconductor die 120 and the conductive wire 130 is performed. Is done. The encapsulant 140 may be formed of a conventional epoxy resin.

3A and 4N, a metal carrier removing step S9 is performed to remove the metal carrier 10 under the substrate 110. The metal carrier 10 may be removed using a selective wet chemical etch method. As a result, the land 112 may be exposed to the lower surface of the substrate 110. As described above, the semiconductor device 100 according to the exemplary embodiment may be manufactured.

1A is a plan view of a substrate used in a semiconductor device according to one embodiment of the present invention.

1B is a bottom view of a substrate used in a semiconductor device in accordance with one embodiment of the present invention.

1C is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

3A is a flowchart for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

3B is a flowchart for explaining in detail a step of providing a substrate in the method of manufacturing a substrate according to an embodiment of the present invention.

4A to 4N are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100, 200; Semiconductor device according to the invention

110; Substrate 111; Insulation layer

112; Land 113; Redistribution Layer

114; Bonding layer 115; Central land

116; Heat dissipation layer 117; Center bonding layer

120; Semiconductor die 130; Conductive wire

140; Encapsulant

Claims (24)

An insulating layer, a land exposed to a lower surface of the insulating layer, and a redistribution layer having one end electrically connected to the land through the insulating layer having the same cross-sectional area as the land and having the other end routed along the upper surface of the insulating layer. Substrate; A semiconductor die attached to the top of the substrate; A conductive wire electrically connecting the redistribution layer and the semiconductor die; And And an encapsulant formed on top of the substrate to enclose the semiconductor die. The method of claim 1, And the insulating layer is formed of a solder mask or a film type solder mask. The method of claim 1, And the land includes a first metal layer exposed to a lower surface of the insulating layer and a second metal layer formed on the first metal layer. The method of claim 3, wherein And wherein the first metal layer is made of gold and the second metal layer is made of nickel. The method of claim 1, And wherein said redistribution layer is made of copper. The method of claim 1, Wherein one end of the redistribution layer is formed at the same height as the insulating layer, and the other end of the redistribution layer extends around the semiconductor die along an upper surface of the insulating layer. The method of claim 1, And a bonding layer formed on the other end of the redistribution layer to protrude from the redistribution layer. The method of claim 7, wherein And said bonding layer comprises a first metal layer formed on top of said redistribution layer and a second metal layer formed on top of said first metal layer. The method of claim 8, And the first metal layer of the bonding layer is formed of nickel, and the second metal layer is formed of at least one selected from gold, silver, and palladium / gold. The method of claim 1, And the substrate further comprises a heat dissipation layer formed corresponding to the lower portion of the semiconductor die. The method of claim 10, And a bonding layer is further formed on the heat dissipation layer of the substrate. The method of claim 11, The bonding layer of the heat dissipation layer includes a first metal layer formed on the heat dissipation layer and a second metal layer formed on the first metal layer, the first metal layer is made of nickel, and the second metal layer is gold, And at least one selected from silver and palladium / gold. The method of claim 11, And a land further exposed to a lower surface of the substrate under the heat dissipation layer. The method of claim 1, At least one of the redistribution layer is formed while filling the insulating layer only on the upper portion of the land, and a bonding layer is further formed on the redistribution layer. An insulating layer, a land exposed to a lower surface of the insulating layer, a redistribution layer having one end electrically connected to the land through the insulating layer having the same cross-sectional area as the land, and the other end being routed along the upper surface of the insulating layer; A substrate comprising a substrate attached to the top of the metal carrier; Attaching a semiconductor die on top of the substrate; Bonding a conductive wire to electrically connect the substrate and the semiconductor die; An encapsulation step of forming an encapsulant on top of the substrate to surround the semiconductor die; And And removing the metal carrier to remove the metal carrier. The method of claim 15, The substrate providing step Providing a metal carrier having the metal carrier in a plate shape; An insulating layer forming step of forming a patterned insulating layer on the metal carrier; Forming a land between the patterns of the insulating layer; A seed layer forming step of forming a seed layer by plating a metal on the insulating layer and the land; Forming a DFR (Dry Film Resist) on the seed layer; An electroplating step of forming a pre-rewiring layer by electroplating using the seed layer; A DFR removal step of removing the DFR; And And flash etching said preliminary redistribution layer to form a redistribution layer. The method of claim 16, Between the electrolytic plating step and the DFR removing step An auxiliary DFR forming step of forming an auxiliary DFR on the preliminary redistribution layer; And And a bonding layer forming step of forming a bonding layer by plating between the auxiliary DFRs. The method of claim 16, And the step of providing the metal carrier comprises the metal carrier made of a copper material. The method of claim 16, The land forming step includes forming a first metal layer made of gold between the insulating layers, and forming a second metal layer made of nickel on the first metal layer. The method of claim 16, And the seed layer forming step is performed by electroless plating. The method of claim 17, The electroplating step is a method of manufacturing a semiconductor device, characterized in that to form the pre-redistribution layer by plating copper on the exposed top of the seed layer using an electrolytic plating method. The method of claim 17, And wherein said forming of said bonding layer forms said bonding layer on the exposed top of said DFR and auxiliary DFR. The method of claim 22, The bonding layer forming step includes forming the bonding layer by forming a first metal layer formed on the preliminary redistribution layer and forming a second metal layer on the first metal layer. The method of claim 22, And the flash etching step includes etching the pre-rearrangement layer made of copper to form the redistribution layers that are electrically independent of each other.

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