KR20100023132A - Flash memory device and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A flash memory device and a manufacturing method thereof are provided to prevent a bridge between a contact plugs by forming a even group contact plug, a pad contact plug, and an odd group contact plug. CONSTITUTION: A flash memory device comprises a first contact plug(124a), a second contact plug(124b), a first and second conductive pads(130a,130b), a first and second pad contact plugs(138a,138b), and a first bit line(BL1) and a second bit line(BL2). The first contact plugs are formed on the semiconductor substrate(100). The second contact plugs is higher than first contact plugs. The first and second conductive pads are connected to the first contact plug. The first bit lines are connected to the first and second pad contact plugs. The second bit lines are connected to the second contact plugs.

Description

Flash memory device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device and a method of manufacturing the same, and more particularly, to a flash memory device and a method of manufacturing the same, which can prevent the occurrence of bridges between contact plugs and improve the buried characteristics of the contact plugs.

Recently, researches on semiconductor memory devices for high integration and improved performance have been actively conducted. Hereinafter, a problem of the high integration will be described in detail by taking a NAND flash memory device having high integration and low manufacturing cost in semiconductor memory devices as an example.

NAND flash memory devices are composed of a plurality of cell strings. The cell string includes a source select transistor, a plurality of memory cells, and a drain select transistor connected in series. The source of the source select transistor is connected to the common source line, and the drain of the drain select transistor is connected to the bit line. The gates of the source select transistors are connected to form a source select line, the gates of the drain select transistors are connected to form a drain select line, and the gates of the memory cells are connected to form a word line.

The gate pattern including the word line, the source select line, and the drain select line is formed in a structure in which a tunnel insulating film, a floating gate, a dielectric film, and a control gate are sequentially stacked. A contact hole exposing the floating gate is formed in the dielectric film included in the drain select line and the source select line. The floating gate is electrically connected to the control gate through the contact hole.

The lower structure of the flash memory including the gate pattern is covered with an insulating layer to be isolated from the upper structure including the common source line and the bit line, and is separated from the upper structure by a contact plug formed in the contact hole penetrating the insulating layer. Electrically connected.

Recently, as the integration of memory devices is accelerated, contact margins are further miniaturized due to the miniaturization of cell size, and thus the process margin is very insufficient in forming contact holes. Hereinafter, a drain contact plug forming process of a general flash device will be briefly described. A plurality of string structures are formed in the semiconductor substrate including a source select transistor, a plurality of memory cells, and a drain select transistor. Subsequently, a source contact plug is formed through a predetermined process, an interlayer insulating layer is formed thereon, and contact holes are formed to expose the drain of the drain select transistor. Thereafter, tungsten (W) is deposited on the interlayer insulating layer including the contact hole and then planarized to form a drain contact plug filling the contact hole.

In the above process, when the drain contact hole is formed, the thickness of the interlayer insulating layer to be etched is so thick that when the bottom CD of the drain contact hole is secured to a certain level, a bowing phenomenon occurs in which the intermediate depth of the contact hole is widened. Accordingly, contact holes may be connected at the portion where bowing is generated during wet cleaning, and contact plugs formed therein may be connected to each other to generate a bridge.

If the hole is formed by suppressing the bridge between holes as much as possible, the size of the opened hole is so small that the aspect ratio becomes large, resulting in a poor filling of the contact plug such as a void, thereby causing an electrical short circuit.

In addition, the hole is formed by suppressing the inter-hole bridge as much as possible, and even if the contact plug is well buried, the fine defects generated during the deposition of the interlayer insulating film are removed by the subsequent wet cleaning process. Generate a bridge. This problem is difficult to solve because it is not detected at the in-line (in-line) inspection because it is not a bridge generated in the upper part of the hole.

The present invention provides a contact plug which forms contact plugs belonging to an even or odd group of contact plugs, forms a pad contact plug, and then forms contact plugs belonging to the remaining group of contact plugs. The present invention provides a flash memory device and a method for manufacturing the same, which can prevent the occurrence of bridges between contact plugs and improve the buried characteristics of the contact plugs by applying a formation scheme.

The flash memory device according to an embodiment of the present invention alternately with the first contact plugs formed on the semiconductor substrate between the gate patterns and the first contact plug higher than the height of the first contact plug on the semiconductor substrate between the gate patterns. Disposed second contact plugs, first and second conductive pads respectively connected to the first contact plug on the first contact plug, and first and second pads formed respectively over the extended edges of the first and second conductive pads. Contact plugs, first bit lines respectively connected to the first and second pad contact plugs, and second bit lines respectively connected to the second contact plugs.

In the above description, a flash memory device according to an embodiment of the present invention may include a first insulating layer in which a first contact hole is formed and a region in which first and second conductive pads are formed. A second insulating film having first and second pad holes formed therein and a third insulating film having first and second pad contact holes defining regions in which the first and second pad contact plugs are formed.

In the above, the second contact plug is formed in the second contact hole penetrating the first, second and third insulating layers.

The spacer may further include a spacer on at least one sidewall of the first contact hole, the second contact hole, the first pad contact hole, and the second pad contact hole.

The spacer may be formed of a material having an etch selectivity different from that of the first, second and third insulating layers.

The spacer is formed of a nitride based material.

In the above, the first and second contact plugs are connected to the drain junction region formed on the semiconductor substrate between the gate patterns.

In the above, the first contact plug and the first and second conductive pads are formed separately or integrally.

A method of manufacturing a flash memory device according to a first exemplary embodiment of the present invention includes providing a semiconductor substrate on which junction regions are formed between gate patterns and a first insulating layer covering the gate patterns. Forming first contact plugs connected to the first bonding regions belonging to the group, respectively, in the first insulating layer; first and second conductive pads respectively connected to the first contact plugs on the first contact plug and the first insulating layer Forming a second insulating film including a second insulating film including a second insulating film on the first and second conductive pads and the second insulating film, and being connected to second bonding regions belonging to a remaining group of the bonding areas, respectively, A second contact plug alternately disposed with the first contact plug is formed inside the first, second and third insulating films and connected to the extended edges of the first and second conductive pads. Forming first and second pad contact plugs inside the third insulating layer, and first bit lines connected to the first and second pad contact plugs and intersecting the gate pattern, and second contact plugs, respectively. Forming a second bit line disposed alternately with the first bit line.

In the method of manufacturing a flash memory device according to the second embodiment of the present invention, a semiconductor substrate having junction regions formed between gate patterns is provided, sequentially forming first and second insulating films on the semiconductor substrate, and bonding. Forming first and second pad holes exposing a first insulating layer corresponding to the first bonding regions belonging to the even or odd group among the regions, and exposing the first bonding regions through the exposed first insulating layer. Forming a first contact hole, forming first and second conductive pads in the first and second pad holes, respectively, forming a first contact plug in the first contact hole, and first and second conductivity Forming a third insulating film on the pad, and connecting the second contact plugs alternately disposed with the first contact plugs to be connected to the second bonding regions belonging to the remaining group of the bonding regions. Forming first and second pad contact plugs inside the third insulating film, the first and second pad contact plugs being formed inside the third insulating film and connected to the extended edges of the first and second conductive pads, and the first and second pad contact plugs; Forming a first bit line connected to each other and crossing the gate pattern, and a second bit line connected to the second contact plug and disposed alternately with the first bit line.

In the above, the gate pattern is formed of a drain select line.

In the above, the first and second conductive pads are alternately formed, and extend in directions opposite to each other.

In the above, the first and second conductive pads extend to the upper part of the word line by crossing the gate pattern.

In the above, the width of the first and second conductive pads connected with the first and second pad contact plugs is wider than the width of the first and second conductive pads connected with the first contact plug.

In the above, the height of the second contact plug is formed to be equal to the sum of the height of the first contact plug, the height of the first and second conductive pads, and the height of the first and second pad contact plugs.

In the method of manufacturing a flash memory device according to the first embodiment, before forming the first contact plug, forming a first contact hole defining a region in which the first contact plug is to be formed in the first insulating plug, and The method may further include forming a first spacer on sidewalls of the first contact hole.

In the method of manufacturing a flash memory device according to the first embodiment, before forming the second contact plug, a second contact hole defining a region in which the second contact plug is to be formed is formed in the first, second, and third insulating layers. Forming first and second pad contact holes in the third insulating layer to define regions in which the first and second pad contact holes are to be formed, and forming the second contact holes and the first and second pad contacts. And forming a second spacer on the sidewall of the hole.

In the method of manufacturing a flash memory device according to the second embodiment, the method may further include forming a first spacer on sidewalls of the first contact hole and the first and second pad holes before forming the first contact plug.

In the method of manufacturing a flash memory device according to the second embodiment, before forming the second contact plug, a second contact hole defining a region in which the second contact plug is to be formed is formed in the first, second, and third insulating layers. Forming first and second pad contact holes in the third insulating layer to define regions in which the first and second pad contact holes are to be formed, and forming the second contact holes and the first and second pad contacts. And forming a second spacer on the sidewall of the hole.

The present invention has the following effects.

First, it is possible to increase the contact etching margin by lowering the height of the interlayer insulating layer to be etched when forming the contact hole as much as possible, and to improve the buried characteristic of the contact plug by reducing the aspect ratio of the contact hole.

Second, when forming a contact plug, contact formation is performed by forming contact plugs belonging to an even or odd group of contact plugs, forming a pad contact plug, and then forming contact plugs belonging to the remaining group of contact plugs. By applying a scheme, contact plugs having different heights may be alternately disposed to sufficiently secure the bottom line width of the contact hole while preventing bridges between adjacent contact plugs due to bowing.

Third, a contact structure for connecting the bit line and the junction region is formed by dividing the contact plug and the pad contact plug, and alternately forming conductive pads connected to contact plugs belonging to an even or odd group among the contact plugs alternately. By forming a distance between the contact plugs belonging to the other group of the contact plugs and the pad contact plug, a bridge between adjacent contact plugs can be prevented.

Fourth, spacers may be further formed on the sidewalls of the contact holes to prevent bridges between contact plugs due to voids or defects generated during the deposition of the interlayer insulating film.

Fifth, since bit lines share contact holes one-to-one, but bit lines and neighboring contact plugs are far apart, it is advantageous in terms of preventing bridges between bit lines and contact plugs.

Sixth, since the bottom line width of the contact hole having a relatively high aspect ratio is secured while preventing bridges between adjacent contact plugs, it is possible to prevent a defect in which the junction area under the contact hole is electrically better open.

Seventh, it is possible to improve the yield by reducing the defect of the device as described above.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various other forms, and only the present embodiments are provided to those skilled in the art to complete the present disclosure. It is provided to fully inform the category.

Flash memory device according to an embodiment of the present invention includes a plurality of cell array. Multiple cell arrays include multiple cell strings. Each cell string includes a source select transistor, a plurality of memory cells, and a drain select transistor connected in series. The source of the source select transistor is connected to the common source line, and the drain of the drain select transistor is connected to the bit line. Gates of the source select transistors are connected to become source select lines, and gates of the drain select transistors are connected to become drain select lines, and gates of memory cells are connected to become word lines. The word line is formed between the drain select line and the source select line, and the bit line is formed to cross the word line.

1A to 1F are layout views showing process steps in order to explain a method of manufacturing a flash memory device according to a first embodiment of the present invention, and FIGS. 2A to 2F are lines A- of FIGS. 1A to 1F. In order to explain the manufacturing method of the state cut | disconnected by A ', it is process sectional drawing shown in process order, and FIG. 3A-FIG. 3F are the manufacturing methods of the state cut | disconnected by the line B-B' of FIG. 4A to 4F are cross-sectional views of the process sequence, and FIGS. 4A to 4F are cross-sectional views of the process sequence in order to explain the manufacturing method of the state taken along the line C-C 'of FIGS. 1A to 1F. Like numbers refer to like elements throughout the specification.

1A, 2A, 3A, and 4A, a semiconductor substrate 100 on which gate patterns 112 and junction regions 101a and 101b are formed is provided. The gate pattern 112 is formed in a structure in which the tunnel insulating layer 102, the floating gate 104, the dielectric layer 106, and the control gate 108 are sequentially stacked, and a hard mask layer is formed on the control gate 108. 110 may be further stacked. The control gates 108 of the cells formed on different strings of the gate patterns 112 are connected to become word lines, source select lines, or drain select lines. The gate pattern 112 illustrated in the drawing is a portion where the control gate 108 is connected to become a drain select line DSL and a word line WL. The dielectric layer 106 included in the drain select line DSL and the source select line of the gate pattern 112 includes a contact hole exposing the floating gate 104, and thus, the drain select line DSL and the source select line. In FIG. 3, the floating gate 104 and the control gate 108 are electrically connected to each other through a contact hole.

The junction regions 101a and 101b are formed by implanting ions into the semiconductor substrate 100 using the gate pattern 112 as a mask. The junction regions 101a and 101b are separated by the device isolation layer 114. In addition, the junction regions 101a and 101b include a drain region 101a formed between the drain select line DSL, a source region formed between the source select line, and a cell junction region 101b formed between the word line.

On the semiconductor substrate 100 including the gate patterns 112, a first etch stop layer 116 and a first interlayer insulating layer 118 called a self alignment contact (SAC) nitride layer are formed. The first interlayer insulating layer 118 is formed of an oxide-based material.

Hereinafter, an example of a process of forming the first contact holes 120a belonging to an even or odd group of the contact holes 120a or 120b will be described in detail. First, a first etch stop layer 116 and a first interlayer insulating layer 118 are formed on the semiconductor substrate 100 on which the gate patterns 112 and the junction regions 101a and 101b are formed. In this case, the first interlayer insulating layer 118 may be formed by lowering the height as much as possible in order to increase a subsequent contact etch margin.

A drain contact mask pattern (not shown) is formed on the first interlayer insulating layer 118 to expose the first interlayer insulating layer 118 corresponding to the first drain regions 101a belonging to the even or odd group of the drain regions 101a. ). Thereafter, the exposed first interlayer insulating layer 118 and the lower portion of the first etch stop layer 116 are etched using the drain contact mask pattern as a mask. Ibn of the contact holes exposing the first drain regions 101a belonging to the even or odd group of the drain regions 101a at portions where the first interlayer insulating layer 118 and the first etch stop layer 116 are removed. First contact holes 120a belonging to the odd group are formed. The first contact holes 120a define the formation region of the first contact plug to be formed in a subsequent process. When forming the first contact holes 120a, the bowing does not occur because the thickness of the first interlayer insulating layer 118 to be etched is low. Thereafter, the drain contact mask pattern is removed through a strip process and a cleaning process.

Subsequently, first spacers 122 are formed on sidewalls of the first contact holes 120a. The first spacer 122 is formed by depositing a liner-type insulating film (not shown) to fill a portion of the first contact holes 120a and then etching the insulating film by a spacer etching process. As a result, the horizontal portion of the insulating layer is removed, and the vertical portion formed thicker than the horizontal portion remains on the sidewall of the first contact hole 120a to form the first spacer 122. The first spacer 122 is formed of a material having an etching selectivity different from that of the first interlayer insulating layer 118. Preferably, the first spacer 122 may be formed of a nitride-based material such as silicon nitride layer Si ₃ N ₄ or silicon oxynitride layer SiON.

Typically, when the first interlayer insulating layer 118 is formed, defects and / or voids may be generated during the deposition process. Such a defect material is removed during the cleaning process to cause a random bridge between the holes and the holes after the subsequent formation of the contact plug (not shown). In addition, the void generates a bridge by connecting the hole and the hole after the cleaning process. However, when the first spacer 122 is formed on the sidewall of the first contact hole 120a belonging to the even or odd group of the contact holes, the bridge between the hole and the hole may be prevented as in the present invention. Furthermore, a bridge between the drain select lines DSL may be prevented by preventing sidewall loss of the first interlayer insulating layer 118 due to excessive etching of the first interlayer insulating layer 118 during the cleaning process before depositing the conductive film for contact plug. It can prevent.

1B, 2B, 3B, and 4B, first contact plugs 124a belonging to an even or odd group of contact plugs are formed in the first contact holes 120a. The first contact plugs 124a are formed on the junction regions 101a between the gate patterns (eg, drain select line (DSL)) 112. Hereinafter, an example of a process of forming the first contact plugs 124a will be described in detail. First, a conductive film (not shown) is formed on the first spacer 122 including the first contact holes 120a and the first interlayer insulating layer 118 so that the first contact holes 120a are filled. The conductive film can be formed of polysilicon, tungsten or the like. Subsequently, a chemical mechanical polishing (CMP) process is performed to expose the first interlayer insulating layer 118, so that the first contacts belonging to the even or odd group of the contact plugs are respectively inside the first contact holes 120a. The plugs 124a are formed.

1C, 2C, 3C, and 4C, a second interlayer including alternately disposed first conductive pads 130a and second conductive pads 130b connected to the first contact plugs 124a. An insulating film 126 is formed.

In more detail, the second interlayer insulating layer 126 is formed on the first contact plugs 124a and the first interlayer insulating layer 118. The second interlayer insulating layer 126 is formed of an oxide-based material. The second interlayer insulating layer 126 may be formed by lowering the height as much as possible to increase subsequent contact etching margins. Thereafter, a pad mask pattern (not shown) defining a region in which the first and second conductive pads 130a and 130b are to be formed is formed on the second interlayer insulating layer 126.

Then, the exposed second interlayer insulating layer 126 is removed by an etching process using the pad mask pattern as a mask. As a result, first pad holes 128a and second pad holes 128b that are alternately disposed while exposing the first contact plug 124a are formed in a portion where the second interlayer insulating layer 126 is removed. That is, the first and second pad holes 128a and 128b may extend from the first contact plug 124a toward the drain select line DSL to the upper portion of the word line WL. Each of the first and second pad holes 128a and 128b defines a region in which the first and second conductive pads to be formed in a subsequent process are formed.

The first and second pad holes 128a and 128b are formed to extend in opposite directions with respect to the first contact plug 124a so as not to be connected to each other. That is, the first pad holes 128a extend in one direction based on the first contact plug 124a, and the second pad holes 128b extend in the other direction based on the first contact plug 124a. Thereafter, the remaining pad mask pattern is removed through a strip process and a cleaning process.

Meanwhile, during the etching process for removing the second interlayer insulating layer 126, the first interlayer insulating layer 118 and the second interlayer may be interposed to prevent the first interlayer insulating layer 118 from being removed to damage the gate pattern 112. A second etch stop layer (not shown) having a different etching selectivity from the second interlayer insulating layer 126 may be further formed between the insulating layers 126. When the second etch stop layer is formed, the first and second pad holes 128a and 128b are formed through the second etch stop layer.

Subsequently, a conductive film (not shown) is formed on the second interlayer insulating layer 126 including the first and second pad holes 128a and 128b to fill the first and second pad holes 128a and 128b. The conductive film can be formed of tungsten or the like. Thereafter, a CMP process is performed to expose the second interlayer insulating layer 126 to form first and second conductive pads 130a and 130b in the first and second pad holes 128a and 128b, respectively.

As a result, the first conductive pads 130a may be connected to the first contact plug 124a to cross the drain select line DSL in one direction, and the second conductive pads 130b may be formed of the first contact plugs. It is connected to the 124a is formed to cross the drain select line (DSL) in the other direction. As such, the first and second conductive pads 130a and 130b are alternately disposed and extend in directions facing each other. The first and second conductive pads 130a and 130b may extend from the first contact plug 124a toward the drain select line DSL to the upper portion of the word line WL.

For the stability of the process, the width W2 of the first and second conductive pads 130a and 130b to be connected to the first and second pad contact plugs formed in a subsequent process may be defined by the first and second contact plugs 124a and the first and second conductive pads 130a and 130b. The second conductive pads 130a and 130b are formed to be wider than the width W1.

1D, 2D, 3D, and 4D, the remaining group of drain regions 101a is disposed between the first contact holes 120a in the first to third interlayer insulating layers 118, 126, and 132. Second contact holes 120b are formed to expose the second drain regions 101a belonging to each other. In addition, first and second pad contact holes 134a and 134b are formed in the third interlayer insulating layer 132 to expose end portions (ie, extended portions) of the first and second conductive pads 130a and 130b. do. Hereinafter, a method of forming the third interlayer insulating layer 132 including the second contact holes 120b and the first and second pad contact holes 134a and 134b will be described in detail.

First, a third interlayer insulating layer 132 is formed on the second interlayer insulating layer 126 including the first and second conductive pads 130a and 130b. The third interlayer insulating layer 132 is formed of an oxide-based material. The third interlayer insulating layer 132 may be formed by lowering the height as much as possible in order to increase subsequent contact etching margins. Thereafter, a drain pad contact mask pattern (not shown) defining a region in which the second contact holes 120b and the first and second pad contact holes 134a and 134b are to be formed is formed on the third interlayer insulating layer 132. Is formed.

Then, the exposed insulating layers are etched using the drain pad contact mask pattern as a mask. The second contact hole 120b is formed by etching the exposed third interlayer insulating layer 132 and the second and first interlayer insulating layers 126 and 118 below, and the first and second pad contact holes 134a, 134b is formed by etching only the exposed third interlayer insulating film 132. As a result, the second drain regions 101a belonging to the remaining group of the drain regions 101a are exposed through the second contact hole 120b. The second contact holes 120b are formed to sufficiently secure a bottom critical dimension (CD) to prevent not open failure. The ends of the first and second conductive pads 130a and 130b are exposed through the first and second pad contact holes 134a and 134b. Each of the first and second pad contact holes 134a and 134b defines a region in which the first and second pad contact plugs to be formed in a subsequent process are to be formed. The second contact hole 120b defines a region in which a second contact plug to be formed in a subsequent process is to be formed.

Although not shown in the drawing, the thicknesses of the first to third interlayer insulating films 118, 126, and 132 to be etched when the second contact holes 120b are formed are so thick that the contact is made at the intermediate depth of the second contact hole 120b. A bowing phenomenon occurs in which the width of the hole is widened. However, in the present invention, since the heights of the first to third interlayer insulating films 118, 126, and 132 are formed as low as possible, the bowing of the second contact hole 120b is performed. Not only can the phenomenon be alleviated, but also the aspect ratio can be reduced.

The first and second pad contact holes 134a and 134b are formed as far as possible from the second contact hole 120b in order to suppress bridge generation due to bowing between the second contact plug and the pad contact plug to be formed later. do. That is, the first and second pad contact holes 134a and 134b are formed on the ends of the first and second conductive pads 130a and 130b that are far from the first contact plug 124a. In this case, when forming the first and second pad contact holes 134a and 134b, an alignment margin may be secured. Thereafter, the drain pad contact mask pattern is removed through a strip process and a cleaning process.

Subsequently, second spacers 136 are formed on sidewalls of the second contact holes 120b and the first and second pad contact holes 134a and 134b. The second spacer 136 is formed by depositing a liner-type insulating film (not shown) to fill a portion of the second contact hole 120b and the first and second pad contact holes 134a and 134b. It is formed by etching. As a result, the horizontal portion of the insulating layer is removed, and the vertical portion formed thicker than the horizontal portion remains on the sidewalls of the second contact holes 120b and the first and second pad contact holes 134a and 134b, thereby leaving the second spacer 136. Is formed. The second spacer 136 is formed of a material having an etching selectivity different from that of the first to third interlayer insulating layers 118, 126, and 132. Preferably, the second spacer 136 may be formed of a nitride-based material such as silicon nitride film Si ₃ N ₄ or silicon oxynitride film SiON.

Like the first spacer 122 described above, the second spacer 136 may also have holes between the holes due to voids and defects generated during the deposition of the first, second, and third interlayer insulating films 118, 126, and 132. Prevents bridge generation and serves as an etch barrier layer in the subsequent wet cleaning process.

1E, 2E, 3E, and 4E, a second contact plug 124b belonging to the remaining group of contact plugs is formed in the second contact hole 120b, and the first and second pad contacts are formed. First and second pad contact plugs 138a and 138b are formed in the holes 134a and 134b, respectively. The second contact plugs 124b are formed on the junction region 101a between the gate patterns (eg, the drain select line DSL) 112. Hereinafter, a method of forming the second contact plugs 124b and the first and second pad contact plugs 138a and 138b will be described in detail.

First, the second contact holes 120b and the first and second pad contact holes 134a and 134b are filled so that the second contact holes 120b and the first and second pad contact holes 134a and 134b are filled. A conductive film (not shown) is formed on the third interlayer insulating film 132 included. The conductive film can be formed of polysilicon, tungsten or the like.

Thereafter, a CMP process is performed to expose the third interlayer insulating layer 132 to form second contact plugs 124b in the second contact holes 120b. Here, the height h4 of the second contact plug 124b includes the height h1 of the first contact plug 124a, the height h2 of the first and second conductive pads 130a and 130b, and the third interlayer insulating film. It is equal to the sum of the height h3 of 132. As a result, the height h4 of the second contact plug 124b is higher than the height h1 of the first contact plug 124a. In addition, the second contact plugs 124b are alternately disposed at different heights from the first contact plugs 124a. In addition, when the CMP process is performed to expose the third interlayer insulating layer 132, first and second pad contact plugs 138a and 138b are formed in the first and second pad contact holes 134a and 134b. The first pad contact plugs 138a and the second pad contact plugs 138b are alternately connected to the first contact plug 124a and are formed to face in directions opposite to each other. That is, the first pad contact plugs 138a are formed to face in one direction based on the first contact plug 124a, and the second pad contact plugs 138b are in the other direction based on the first contact plug 124a. It is formed to face.

In the present invention, since the second contact hole 120b is formed with a reduced aspect ratio, when the second contact plug 124b is formed, the second contact plug 124b may be formed without voids by improving the buried property of the contact hole. In addition, in the present invention, the heights of the first contact plugs 124a alternately formed with the second contact plugs 124b are different from each other. Accordingly, even when the second contact plug 124b is formed inside the second contact hole 120b having the bowing, the second contact adjacent to the first contact plug 124a having a relatively low height and no bowing is generated. The bridge between the plug 124b and the first contact plug 124a can be prevented.

Furthermore, a contact structure for connecting the bit line and the junction region 101a to be formed later is formed by the first and second contact plugs 124a and 124b and the first and second pad contact plugs 138a and 138b. It is formed by dividing, but by forming a distance between the second contact plug 124b and the first and second pad contact plugs 138a, 138b to prevent the bridge between the adjacent first and second contact plugs (124a, 124b) can do.

1F, 2F, 3F, and 4F, a plurality of connected to first and second pad contact plugs 138a and 138b, respectively, belonging to an even or odd group crossing the drain select line DSL. First bit lines 140a of the plurality of second bit lines 140a are formed, are connected one-to-one to the second contact plugs 124b, and cross the drain select line DSL to belong to the remaining group of bit lines. ) Is formed. Hereinafter, a method of forming the first and second bit lines 140a and 140b will be described in detail.

First, a metal layer (not shown) is formed on the second contact plugs 124b and the first and second pad contact plugs 138a and 138b. The metal layer is formed of a material having a low specific resistance. For example, tungsten or the like is used. Thereafter, a bit line mask pattern (not shown) is formed on the metal layer to cover the region where the bit line is to be formed. The exposed metal layer is then etched using the bit line mask pattern as a mask. Thereafter, the remaining bit line mask pattern is removed through a strip process and a cleaning process.

After etching the metal layer, a plurality of first bit lines BL1 connected to the first and second pad contact plugs 138a and 138b and crossing the drain select line DSL and belonging to the even or odd group are formed. do. In addition, the metal layer is etched and then connected to the second contact plug 124b, and crosses the drain select line DSL to form a second bit line BL2 belonging to the remaining group of the even or odd group. As a result, the first and second bit lines BL1 and BL2 are alternately arranged.

The first and second pad contact plugs 138a and 138b electrically connect the first and second conductive pads 130a and 130b and the first bit line BL1. Therefore, the first bit lines BL1 and the first drain regions 101a belonging to the even or odd group of the drain regions 101a are electrically connected to each other. The second bit lines BL2 are electrically connected to the second drain regions 101a belonging to the remaining group of the drain regions 101b through the second contact plug 124b.

In the present invention, the first and second bit lines BL1 and BL2 overlap each of the first and second contact holes 120a and 120b, but the first contact plug 124a adjacent to the second bit line BL2. Is far away, which is advantageous in terms of preventing bridge generation between the second bit line BL2 and the first contact plug 124a.

5A to 5F are layout views showing process steps in order to explain a method of manufacturing a flash memory device according to a second exemplary embodiment of the present invention, and FIGS. 6A to 6F are lines A- of FIGS. 5A to 5F. In order to explain the manufacturing method of the state cut | disconnected by A ', it is process sectional drawing shown in order of a process, and FIG. 7A-FIG. 7F are the manufacturing methods of the state cut | disconnected by the line B-B' of FIGS. 5A-5F. 8A to 8F are cross-sectional views illustrating process steps in order to explain a manufacturing method of a state cut along the line C-C ′ of FIGS. 5A to 5F.

5A, 6A, 7A, and 8A, a first etch stop layer 116 and a first interlayer are formed on a semiconductor substrate 100 including gate patterns 112 and junction regions 101a and 101b. The second interlayer insulating layer 126 including the insulating layer 118 and the first and second pad holes 128a and 128b is sequentially formed. Description of the gate pattern 112, the junction regions 101a and 101b, the first etch stop layer 116, and the first interlayer insulating layer 118 is the same as described above with reference to FIGS. 1A, 2A, 3A, and 4A. Do. The description of the second interlayer insulating film 126 is the same as described above with reference to FIGS. 1C, 2C, 3C, and 4C. The formation structure of the first and second pad holes 128a and 128b is the same as described above with reference to FIGS. 1C, 2C, 3C, and 4C. The first and second pad holes 128a and 128b are alternately formed in directions facing each other, and overlap the drain region 101a belonging to the even and odd groups.

However, in the manufacturing method illustrated in FIGS. 5A, 6A, 7A, and 8A, no contact hole is formed in the first interlayer insulating layer 118.

Although not shown, a second etch stop layer may be further formed between the first interlayer insulating layer 118 and the second interlayer insulating layer 126.

5B, 6B, 7B, and 8B, a first belonging to an even or odd group of contact holes exposing first drain regions 101a belonging to an even or odd group among the drain regions 101a may be described. The first interlayer insulating layer 118 including the contact holes 120a is formed.

The regions overlapping the first drain regions 101a of the first interlayer insulating layer 118 exposed through the first and second pad holes 128a and 128b are exposed between the photoresist patterns formed through the photolithography process. . Thereafter, the exposed first interlayer insulating layer 118 is removed through an etching process to form first contact holes 120a belonging to an even or odd group among the contact holes exposing the first drain regions 101a. Then, the photoresist pattern is removed. When forming the second etch stop layer, the first contact holes 120a are formed through the second etch stop layer.

First spacers 122 are formed on sidewalls of the first contact holes 120a and the first and second pad holes 128a and 128b. Hereinafter, a method of forming the first spacer 122 will be briefly described. The first contact holes 120a and the first and second pad holes 128a on the second interlayer insulating layer 126 including the first contact holes 120a and the first and second pad holes 128a and 128b. After depositing a liner-type insulating film (not shown) to fill a portion of the 128b, the insulating film is etched by a spacer etching process. As a result, the horizontal portion of the insulating layer is removed, and the vertical portion formed thicker than the horizontal portion remains on the sidewalls of the first contact holes 120a and the first and second pad holes 128a and 128b, thereby forming the first spacer 122. Is formed. The first spacer 122 is formed of a material having an etching selectivity different from that of the first and second interlayer insulating layers 118 and 126. Preferably, the first spacer 122 may be formed of a nitride-based material such as silicon nitride layer Si ₃ N ₄ or silicon oxynitride layer SiON.

The first spacer 122 prevents bridges between holes and holes due to voids and defects generated during the deposition of the first and second interlayer insulating films 118 and 126, and the etching barrier layer may be formed in a subsequent wet cleaning process. Play a role.

5C, 6C, 7C, and 8C, first contact plugs 124a belonging to an even or odd group of contact plugs are formed in the first contact holes 120a. In addition, first and second conductive pads 130a and 130b are formed in the first and second pad holes 128a and 128b and are connected to the first contact plug 124a and extend in one and the other directions. . The structures of the first contact plugs 124a are the same as those described above with reference to FIGS. 1B, 2B, 3B, and 4B, and the structures of the first and second conductive pads 130a and 130b are illustrated in FIGS. 1C, 2C, and FIG. 3c and the same as described above in Fig. 4c.

The first contact plugs 124a and the first and second conductive pads 130a and 130b are integrally formed at the same time. In detail, the first contact holes 120a and the first and second pad holes 128a and 128b may be filled to fill the first contact holes 120a and the first and second pad holes 128a and 128b. A conductive film is formed on the included second interlayer insulating film 126. The conductive film can be formed of polysilicon, tungsten or the like. Thereafter, a CMP process is performed to expose the second interlayer insulating layer 126 to form first contact plugs 124a belonging to an even or odd group among the contact plugs in the first contact hole 120a. At the same time, first conductive pads 130a connected to the first contact plugs 124a and extending in one direction are formed in the first and second pad holes 128a and 128b and the first contact plugs 124a are formed. Second conductive pads 130b extending in the other direction are formed. As such, the first and second conductive pads 130a and 130b are electrically connected to the first contact plugs 124a.

5D, 6D, 7D, and 8D, the first to third interlayer insulating layers 118, 126, and 132 are alternately disposed with the first contact holes 120a to form a gate pattern (eg, Second contact holes 120b exposing the junction regions 101a between the drain select lines DSLs 112 are formed. At the same time, first and second pad contact holes 134a and 134b exposing end portions (ie, extended portions) of the first and second conductive pads 130a and 130b are formed in the third interlayer insulating layer 132. Is formed. The descriptions of the second contact holes 120b and the first and second pad contact holes 134a and 134b are the same as described above with reference to FIGS. 1D, 2D, 3D, and 4D.

A second spacer 136 is formed on sidewalls of the second contact holes 120b and the first and second pad contact holes 134a and 134b. The description of the second spacer 136 is the same as described above with reference to FIGS. 1D, 2D, 3D, and 4D.

5E, 6E, 7E, and 8E, second contact plugs 124b are formed in the second contact holes 120b, and the first and second pad contact holes 134a and 134b. First and second pad contact plugs 138a and 138b are formed therein, respectively. The descriptions of the second contact plugs 124b and the first and second pad contact plugs 138a and 138b are the same as described above with reference to FIGS. 1E, 2E, 3E, and 4E.

Referring to FIGS. 5F, 6F, 7F, and 8F, a plurality of connected to the first and second pad contact plugs 138a and 138b, respectively, belonging to an even or odd group crossing the drain select line DSL. First bit lines 140a are formed, connected to the second contact plugs 124b, and crossing the drain select line DSL, a plurality of second bit lines 140b belonging to the remaining group of bit lines are formed. Is formed. The first and second pad contact plugs 138a and 138b electrically connect the first and second conductive pads 130a and 130b and the first bit line BL1. Therefore, the first bit lines BL1 and the first drain regions 101a belonging to the even or odd group of the drain regions 101a are electrically connected to each other. The second bit lines BL2 are electrically connected to the second drain regions 101a belonging to the remaining group of the drain regions 101a through the second contact plug 124b. Description of the first and second bit lines BL1 and BL2 is the same as described above with reference to FIGS. 1F, 2F, 3F, and 4F. As described above, the same effect as in the first embodiment can be obtained in the second embodiment of the present invention.

The present invention is not limited to the above-described embodiments, but can be implemented in various forms, and the above embodiments make the disclosure of the present invention complete and complete the scope of the invention to those skilled in the art. It is provided to inform you. Therefore, the scope of the present invention should be understood by the claims of the present application.

1A to 1F are layout views showing a process order to explain a method of manufacturing a flash memory device according to a first embodiment of the present invention.

2A to 2F are cross-sectional views showing process steps in order to explain a manufacturing method cut along the line A-A 'of FIGS. 1A to 1F.

3A to 3F are cross-sectional views showing process steps in order to explain the manufacturing method of the state taken along the line BB ′ of FIGS. 1A to 1F.

4A to 4F are cross-sectional views showing process steps in order to explain a manufacturing method cut along the line C-C 'of FIGS. 1A to 1F.

5A through 5F are layout views showing a process order to explain a method of manufacturing a flash memory device according to a second exemplary embodiment of the present invention.

6A to 6F are cross-sectional views showing process steps in order to explain a manufacturing method taken along the line A-A 'of FIGS. 5A to 5F.

7A to 7F are cross-sectional views showing process steps in order to explain the manufacturing method of the state taken along the line BB ′ of FIGS. 5A to 5F.

8A to 8F are cross-sectional views showing process steps in order to explain a manufacturing method cut along the line CC ′ of FIGS. 5A to 5F.

<Explanation of symbols for the main parts of the drawings>

100: semiconductor substrate 101a, 101b: junction region

112: gate pattern 114: device isolation film

116: first etch stop film 118: first interlayer insulating film

120a: first contact hole 120b: second contact hole

122: first spacer 124a: first contact plug

124b: second contact plug 126: second interlayer insulating film

128a: first pad hole 128b: second pad hole

130a: first conductive pad 130b: second conductive pad

132: third interlayer insulating film 134a: first pad contact hole

134b: second pad contact hole 136: second spacer

138a: first pad contact plug 138b: second pad contact plug

BL1: first bit line BL2: second bit line

Claims (24)

First contact plugs formed on the semiconductor substrate between the gate patterns; Second contact plugs alternately disposed with the first contact plug on the semiconductor substrate between the gate patterns and higher than a height of the first contact plug; First and second conductive pads respectively connected to the first contact plug on the first contact plug; First and second pad contact plugs respectively formed on an extended edge of the first and second conductive pads; First bit lines connected to the first and second pad contact plugs, respectively; And And second bit lines connected to the second contact plugs, respectively. The method of claim 1, And the gate pattern is formed as a drain select line. The method of claim 1, The first and second conductive pads are alternately formed, and extend in a direction opposite to each other. The method of claim 1, And the first and second conductive pads intersect the gate pattern and extend up to a word line. The method of claim 1, And a width of the first and second conductive pads connected with the first and second pad contact plugs wider than the width of the first and second conductive pads connected with the first contact plug. The method of claim 1, The height of the second contact plug is the same as the sum of the height of the first contact plug, the height of the first and second conductive pads and the height of the first and second pad contact plugs. The method of claim 1, A first insulating film having a first contact hole defining a region in which the first contact plug is formed; A second insulating film having first and second pad holes defining a region in which the first and second conductive pads are formed; And And a third insulating film having first and second pad contact holes defining an area in which the first and second pad contact plugs are formed. The method of claim 7, wherein The second contact plug is formed in the second contact hole penetrating the first, second and third insulating film. The method of claim 8, And a spacer on at least one sidewall of the first contact hole, the second contact hole, the first pad contact hole, and the second pad contact hole. The method of claim 9, And the spacer is formed of a material having an etch selectivity different from that of the first, second and third insulating layers. The method of claim 10, The spacer is a flash memory device formed of a nitride-based material. The method of claim 1, And the first and second contact plugs are connected to a drain junction region formed on the semiconductor substrate between the gate patterns. The method of claim 1, And the first contact plug and the first and second conductive pads are formed separately or integrally. Providing a semiconductor substrate having junction regions formed between the gate patterns and having a first insulating film covering the gate patterns; Forming a first contact plug inside the first insulating layer, the first contact plug being connected to first junction regions belonging to an even or odd group among the junction regions; Forming a second insulating film on the first contact plug and the first insulating film, the second insulating film including first and second conductive pads connected to the first contact plug, respectively; Forming a third insulating film on the first and second conductive pads and the second insulating film; The second contact plugs connected to the second bonding regions belonging to the remaining group of the bonding regions and alternately disposed with the first contact plugs are formed in the first, second and third insulating layers, respectively. Forming first and second pad contact plugs connected to the extended edges of the first and second conductive pads in the third insulating film; And A first bit line connected to the first and second pad contact plugs and crossing the gate pattern, and a second bit line connected to the second contact plug and alternately disposed with the first bit line. Forming a flash memory device comprising the step of forming. Providing a semiconductor substrate having junction regions formed between the gate patterns; Sequentially forming a first and a second insulating film on the semiconductor substrate; Forming first and second pad holes exposing the first insulating layer corresponding to first bonding regions belonging to an even or odd group among the bonding regions; Forming a first contact hole penetrating the exposed first insulating layer to expose the first junction regions; Forming first and second conductive pads in the first and second pad holes, respectively, while forming a first contact plug in the first contact hole; Forming a third insulating film on the first and second conductive pads; The second contact plugs connected to the second bonding regions belonging to the remaining group of the bonding regions and alternately disposed with the first contact plugs are formed in the first, second and third insulating layers, respectively. Forming first and second pad contact plugs connected to the extended edges of the first and second conductive pads in the third insulating film; And First bit lines connected to the first and second pad contact plugs and intersecting the gate patterns, and second bit lines connected to the second contact plugs and alternately disposed with the first bit lines. A method of manufacturing a flash memory device comprising the step of. The method according to claim 14 or 15, And the gate pattern is formed of a drain select line. The method according to claim 14 or 15, The first and second conductive pads are alternately formed, and extend in a direction opposite to each other. The method according to claim 14 or 15, The first and second conductive pads are formed to extend to the upper portion of the word line to cross the gate pattern. The method according to claim 14 or 15, A method of manufacturing a flash memory device in which a width of the first and second conductive pads connected to the first and second pad contact plugs is wider than a width of the first and second conductive pads connected to the first contact plug. . The method according to claim 14 or 15, The height of the second contact plug is the same as the sum of the height of the first contact plug, the height of the first and second conductive pads and the height of the first and second pad contact plugs. . The method of claim 14, wherein before forming the first contact plug, Forming a first contact hole in the first insulating layer to define a region in which the first contact plug is to be formed; And The method of claim 1, further comprising forming a first spacer on a sidewall of the first contact hole. The method of claim 14, wherein before forming the second contact plug, The first and second pad contact holes may be formed in the third insulating layer while forming a second contact hole defining a region in which the second contact plug is to be formed in the first, second and third insulating layers. Forming first and second pad contact holes defining a region to be formed; And And forming a second spacer on sidewalls of the second contact hole and sidewalls of the first and second pad contact holes. The method of claim 15, wherein before forming the first contact plug, And forming a first spacer on sidewalls of the first contact hole and sidewalls of the first and second padholes. The method of claim 15, wherein before forming the second contact plug, The first and second pad contact holes may be formed in the third insulating layer while forming a second contact hole defining a region in which the second contact plug is to be formed in the first, second and third insulating layers. Forming first and second pad contact holes defining a region to be formed; And And forming a second spacer on sidewalls of the second contact hole and sidewalls of the first and second pad contact holes.

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