KR20100022784A

KR20100022784A - Nonvolatile memory device using variable resistive element

Info

Publication number: KR20100022784A
Application number: KR1020080081462A
Authority: KR
Inventors: 최병길
Original assignee: 삼성전자주식회사
Priority date: 2008-08-20
Filing date: 2008-08-20
Publication date: 2010-03-03

Abstract

PURPOSE: A nonvolatile memory device using a variable resistive element is provided to improve the performance of a reading operation by overlapping the discharge section of a writing global bit-line and the disable section of word lines. CONSTITUTION: Memory banks(110_1 to 110_8) include the matrixes of a nonvolatile memory cell. The matrixes of the nonvolatile memory cell have different resistance levels based on data to be saved. A writing global bit line(WGBL0) is arranged to be shared in the memory banks. The write global bit line is used when data is written in the memory banks. A word line(WLm) is coupled with the row of the nonvolatile memory cell in the memory banks.

Description

Nonvolatile memory device using variable resistive element

The present invention relates to a nonvolatile memory device using a resistor.

Nonvolatile memory devices using a resistance material include a phase change random access memory (PRAM), a resistive RAM (RRAM), a magnetic memory device (MRAM), and the like. Dynamic RAM (DRAM) or flash memory devices use charge to store data, while nonvolatile memory devices using resistors are the state of phase change materials such as chalcogenide alloys. Data is stored using change (PRAM), resistance change (RRAM) of the variable resistor, resistance change (MRAM) of the magnetic tunnel junction (MTJ) thin film according to the magnetization state of the ferromagnetic material.

Here, when the phase change memory device is described as an example, the phase change material is changed to a crystalline state or an amorphous state while being heated and cooled, and the phase change material in the crystalline state has a low resistance and the phase change material in the amorphous state has a high resistance. . Therefore, the decision state may be defined as set data or zero data, and the amorphous state may be defined as reset data or one data.

Meanwhile, as the nonvolatile memory device has increased in capacity and high integration, the nonvolatile memory device has a hierarchical bit line structure using a global bit line and a local bit line. In particular, a global bit line including a read global bit line that reads data from a nonvolatile memory cell and a write global bit line that writes data to a nonvolatile memory cell is further substituted for and more integrated. It is becoming. Recently, in a nonvolatile memory device having such a structure, read methods for accurately reading data stored in each memory cell have been researched and developed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile memory device having improved performance during a read operation.

Problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

One aspect of the nonvolatile memory device of the present invention for achieving the above object is a plurality of memory banks, each memory bank comprising a plurality of non-volatile memory cells having a different resistance level according to the data to be stored Memory banks, multiple write global bit lines, each write global bit line arranged to be shared by multiple memory banks, and multiple write global bit lines and multiple words used when writing data in multiple memory banks As a line, each word line includes a plurality of word lines coupled with rows of the plurality of nonvolatile memory cells in the memory bank, and write global bit lines when writing data to the nonvolatile memory cells using write pulses. After receiving the light pulse and occupies a certain level, Charge is, the disabling of a write period and a display period word lines occupy a global bit line is at least some overlap.

Another aspect of the nonvolatile memory device of the present invention for achieving the above object is a plurality of memory banks, each memory bank comprising a matrix of a plurality of nonvolatile memory cells having different resistance levels according to the data to be stored Memory banks, multiple write global bit lines, each write global bit line arranged to be shared by multiple memory banks, multiple write global bit lines used when writing data in multiple memory banks, multiple words As a line, each word line is a plurality of word lines coupled with a row of a plurality of nonvolatile memory cells in a memory bank, and writes a write pulse to a write global bit line in response to a write signal when data is written to the nonvolatile memory cell. Provides write driver and word line select signal and la And in response to the bit signal, a row decoder for determining the level of the word line.

Other specific details of the invention are included in the detailed description and drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

When an element is referred to as being "connected to" or "coupled to" with another element, it may be directly connected or coupled to another element or through another element in between. This includes all cases. On the other hand, when one device is referred to as "directly connected to" or "directly coupled to" with another device indicates that no other device is intervened. Like reference numerals refer to like elements throughout. “And / or” includes each and all combinations of one or more of the items mentioned.

Although the first, second, etc. are used to describe various elements, components and / or sections, these elements, components and / or sections are of course not limited by these terms. These terms are only used to distinguish one element, component or section from another element, component or section. Therefore, the first device, the first component, or the first section mentioned below may be a second device, a second component, or a second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, “comprises” and / or “comprising” refers to the presence of one or more other components, steps, operations and / or elements. Or does not exclude additions.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used in a sense that can be commonly understood by those skilled in the art. In addition, the terms defined in the commonly used dictionaries are not ideally or excessively interpreted unless they are specifically defined clearly.

Hereinafter, embodiments of the present invention will be described using a phase change random access memory (PRAM). However, it will be apparent to those skilled in the art that the present invention can be applied to both a nonvolatile memory device using a resistor, such as a resistive memory device (RRAM) and a ferroelectric RAM (FRAM).

1 and 2 are block diagrams and circuit diagrams for describing a nonvolatile memory device according to example embodiments. For convenience of description, the drawing includes eight memory banks and four local bit lines are selectively coupled to each global bit line, but the present invention is not limited thereto. The number of memory banks and the number of local bit lines coupled to each global bit line may vary depending on the designer's needs.

1 and 2, a nonvolatile memory device according to example embodiments may include a plurality of memory banks 110_1 to 110_8, a local bit line selection circuit 150, a global bit line selection circuit 130, A row decoder 120, an input / output circuit 140, and the like.

Each memory bank 110_1 to 110_8 includes a matrix of a plurality of nonvolatile memory cells MC. Rows of the plurality of nonvolatile memory cells MC are coupled to each word line WL0 to WLm, and columns of the plurality of nonvolatile memory cells MC are local bit lines BL0 to BL3. ) Is coupled.

Here, the nonvolatile memory cell MC has a variable resistance element RC including phase change materials having different resistance values according to a crystalline state or an amorphous state, and an access for controlling a current flowing through the variable resistance element RC. Device AC may be included. The access element AC may be a diode, a transistor, or the like coupled in series with the variable resistance element RC. 2 exemplarily illustrates a diode as an access element AC, but is not limited thereto. As described above, a phase change nonvolatile memory cell using a diode as an access element AC is called a diode controlled phase change nonvolatile memory cell. In addition, the phase change material is GaSb, InSb, InSe. Sb ₂ Te ₃ , GeTe, GeSbTe, GaSeTe, InSbTe, SnSb ₂ Te ₄ , InSbGe, 3 elements, AgInSbTe, (GeSn) SbTe, GeSb (SeTe), Te81Ge15Sb2S2 Can be used. Of these, GeSbTe made of germanium (Ge), antimony (Sb), and tellurium (Te) can be mainly used.

Each word line WL0 to WLm is coupled to a row of the plurality of nonvolatile memory cells MC and disposed in one memory bank 110_1 to 110_8 of the plurality of memory banks 110_1 to 110_8. Although not shown in the drawing, such a word line may be implemented in a hierarchical word line structure using a main word line and a sub word line as a nonvolatile memory device has a large capacity and high integration.

The voltage levels of the word lines WL0 to WLm are adjusted by the row decoder 120 to select at least one word line WL0 to WLm among the word lines WL0 to WLm. In detail, the row decoder 120 enables the word lines WL0 to WLm by adjusting the word lines WL0 to WLm to a voltage level such as, for example, the ground voltage level in response to the row address, For example, the word line may be disabled by adjusting WL0 to WLm to the same level as the boosted power supply (VPP_X) level.

Meanwhile, as the nonvolatile memory device has a larger capacity and higher integration, the bit line may be implemented in a hierarchical bit line structure using global bit lines and local bit lines BL0 to BL3. In this case, each global bit line is selectively coupled with a plurality of local bit lines BL0 to BL3 through a local bit line select circuit 150, and each local bit line BL0 to BL3 is a plurality of nonvolatile memories. Coupling with the cell MC.

In particular, each global bit line of the nonvolatile memory device according to example embodiments of the inventive concept may include a write global bit line WGBL0 to WGBLn and a read global bit line RGBL0 to RGBLn as shown in FIG. 1. have. The write global bit lines WGBL0 to WGBLn are disposed to be shared in the plurality of memory banks 110_1 to 110_8, and are used when writing data in the plurality of memory banks 110_1 to 110_8. On the other hand, the read global bit lines RGBL0 to RGBLn are arranged to be shared in the plurality of memory banks 110_1 to 110_8, and are used when reading data from the plurality of memory banks 110_1 to 110_8. As such, when the nonvolatile memory device includes the write global bit lines WGBL0 to WGBLn and the read global bit lines RGBL0 to RGBLn arranged to be shared by the plurality of memory banks 110_1 to 110_8, an area of the core structure is provided. This can be reduced.

When each global bit line includes the write global bit lines WGBL0 to WGBLn and the read global bit lines RGBL0 to RGBLn, the local bit line select circuit 150 may include the write local bit line select circuit 151 and the read local. The bit line selection circuit 153 may be included. The write local bit line select circuit 151 uses the write local bit line select signals WLY00 to WLY73 to write data to the memory banks 110_1 to 110_8 to write the local bit lines BL0 to BL3 and the write global bits. Selectively couple the lines WGBL0 to WGBLn. On the other hand, when the read local bit line select circuit 153 reads data from the memory banks 110_1 to 110_8, the read local bit line select circuit 153 uses the read local bit line select signals RLY00 to RLY73 to read the local bit lines BL0 to BL3. Selectively couple the global bit lines RGBL0 to RGBLn.

In the drawing, although the write local bit line selection circuit 151 and the read local bit line selection circuit 153 are disposed under the memory banks 110_1 to 110_8, the present invention is not limited thereto. For example, in another embodiment of the present invention, the write local bit line selection circuit 151 and the read local bit line selection circuit 153 may be disposed above the memory banks 110_1 to 110_8.

Also, in the nonvolatile memory device according to another embodiment of the present invention, the write local bit line selection circuit 151 and the read local bit line selection circuit 153 may be arranged as shown in FIG. 6. Specifically, in the nonvolatile memory device according to another exemplary embodiment of the present invention, the read local bit line selection circuit 153 is disposed corresponding to each of the memory banks 110_1 to 110_8, while the write local bit line selection circuit 151 is disposed. ) May correspond to at least two memory banks 110_1 to 110_8. This will be described later in detail with reference to FIG. 6.

The input / output circuit 140 is coupled to the write global bit lines WGBL0 to WGBLn to input data into the memory banks 110_1 to 110_8, or is coupled to the read global bit lines RGBL0 to RGBLn to connect the memory banks 110_1 to 110_8) to output data, and includes a write circuit and a read circuit.

The write circuit is coupled to the write global bit lines WGBL0 to WGBLn to write data in the memory banks 110_0 to 110_8, and includes a data input buffer and a write driver. The data input buffer receives and buffers external data to provide write data to the write driver, and the write driver writes the received write data to the selected nonvolatile memory cell MC among the memory banks 110_1 to 110_8.

The read circuit is coupled to the read global bit lines RGBL0 to RGBLn to read data from the memory banks 110_1 to 110_8, and includes a sense amplifier and a data output buffer. The sense amplifier reads read data from the nonvolatile memory cells MC selected from the memory banks 110_1 to 110_8, and the data output buffer outputs read data.

3 is a diagram illustrating a write operation and / or a read operation of a nonvolatile memory device according to example embodiments. In FIG. 3, the global bit line selection circuit is omitted for convenience of description. FIG. 4 is a view illustrating a condition for phase change of a phase change material included in a nonvolatile memory cell during a write operation. 5 is a timing diagram illustrating an operation of a nonvolatile memory device according to example embodiments. FIG. 5 illustrates a case in which a reset pulse having a relatively high peak level and a relatively narrow pulse width is provided as an example, but is not limited thereto. In addition, in FIG. 5, for convenience of description, a light pulse having a high level peak level will be described as an example, but is not limited thereto.

3 to 5, a nonvolatile memory device according to example embodiments performs a write operation and / or a read operation in each memory bank 110_1 ˜ 110_8. The write operation and the read operation may not be simultaneously performed in the same memory banks 110_1 to 110_8, but may be independently performed in different memory banks 110_1 to 110_8. For example, the nonvolatile memory device may read data from the second memory bank (eg, 110_8) while writing data in the first memory bank (eg, 110_1).

In such a write operation and / or a read operation, first, a word line (eg, WLm) is selected by the row decoder 120, and the write local bit line selection circuit 151 and the global bit line selection circuit (130 in FIG. 1) are selected. The local bit line (eg, BL0) and the write global bit line (eg, WGBL0) are selected by the non-volatile memory cell MC to be written. Similarly, a word line (e.g., WLm) is selected by row decoder 120, and a local bit line (e.g., 130) in read local bit line select circuit 153 and global bit line select circuit (see 130 in Figure 1). , BL0) and a read global bit line (eg, RGBL0) are selected to select the nonvolatile memory cell MC to be read. In particular, when the nonvolatile memory cell MC is a diode control phase change memory cell, the diode may be turned on by adjusting the selected word line (eg, WLm) to a voltage level such as, for example, a ground level.

Meanwhile, in FIG. 3, one write local bit line selection circuit 151 in which each write global bit line WGBL0 to WGBLn and a plurality of local bit lines BL0 to BL3 correspond to each memory bank 110_1 to 110_8 is disposed. It is selectively coupled to each other, so that one current path is formed from each write global bit line WGBL0 to WGBLn to the nonvolatile memory cell MC, but is not limited thereto. For example, the nonvolatile memory device according to another embodiment of the present invention may operate as shown in FIG. 6.

6 is a diagram illustrating an operation of a nonvolatile memory device according to another exemplary embodiment of the present invention.

Referring to FIG. 6, when data is written to a nonvolatile memory cell MC in a nonvolatile memory device according to another embodiment of the present invention, each write global bit line WGBL0 to WGBLn may correspond to each memory bank 110_1 ˜. The plurality of local bit lines BL0 to BL3 may be selectively coupled by at least two write local bit line selection circuits 151a and 151b disposed corresponding to 110_8. That is, at least two current paths may be formed from each write global bit line WGBL0 to WGBLn to the nonvolatile memory cell MC. Accordingly, the nonvolatile memory device according to another embodiment of the present invention provides a sufficient amount of current flowing through the nonvolatile memory cell MC during the write operation, so that the write operation can be stably performed.

The reading of data from the second memory bank (eg, 110_8) may provide a read current to the nonvolatile memory cell MC and thus use a level change of the read global bit lines RGBL0 to RGBLn. In detail, the read circuit 145 provides a read current to the nonvolatile memory cell MC, and senses the level change of the read global bit lines RGBL0 to RGBLn by the sense amplifier of the read circuit 145. Data stored in the volatile memory cell MC may be read.

On the other hand, writing data in the first memory bank (eg, 110_1) may be performed by using the write pulse Wpulse provided to the write global bit lines WGBL0 to WGBLn in the write driver 141. Joule heat generated by the light current (Icell) flowing through the can be used.

Specifically, as shown in FIG. 4, a reset pulse is provided to the write global bit lines WGBL0 to WGBLn so that the first logic level, for example, reset data, is written to the nonvolatile memory cell MC so that the nonvolatile memory cell ( The phase change material included in MC) may be heated to a melting point (Tm) or higher and rapidly cooled to an amorphous state. Similarly, a phase change included in the nonvolatile memory cell MC is provided by providing a set pulse to the write global bit lines WGBL0 to WGBLn so that a second logic level, for example, set data, is written to the nonvolatile memory cell MC. The material may be heated to a temperature above the crystallization temperature (Tx) or below the melting point (Tm), and then maintained at that temperature for a predetermined time before cooling to a crystalline state.

The peak level of this set pulse is typically lower than the peak level of the reset pulse, and the width of the set pulse may be wider than the width of the reset pulse. Here, the peak refers to the maximum current level of each write pulse. The set pulse may be a current pulse that maintains a peak period for a predetermined period and then decreases along a predetermined slope, or may be a current pulse that includes a plurality of stages that sequentially decrease.

In particular, the nonvolatile memory device according to the embodiments of the present invention may include nonvolatile memory cells of the first memory banks 110_1 to 110_8 of the plurality of memory banks 110_1 to 110_8 through the write global bit lines WGBL0 to WGBLn. While writing data to the MC, data is read from the nonvolatile memory cells MC of the second memory banks 110_1 to 110_8 of the plurality of memory banks 110_1 to 110_8 through the read global bit lines RGBL0 to RGBLn. When reading, the levels of the write pulse Wpulse, the write global bit lines WGBL0 to WGBLn, the write current Icell and the read global bit lines RGBL0 to RGBLn may be changed as shown in FIG. 5. . Here, as shown in FIG. 5, a detailed method for implementing the levels of the write pulse Wpulse, the write global bit lines WGBL0 to WGBLn, the write current Icell, and the read global bit lines RGBL0 to RGBLn will be described with reference to FIGS. It will be described later in detail with reference to FIG.

Referring to FIG. 5, in the nonvolatile memory device according to example embodiments, the level change form of the write current used for the write operation is the form of the write pulse Wpulse provided to the write global bit lines WGBL0 to WGBLn. And substantially similarly. On the other hand, the write global bit is charged to the predetermined voltage level by the charging unit 141_a of the write driver 141 and discharged again at the predetermined voltage level by the discharge unit 141_b of the write driver 141. The level change form of the lines WGBL0 to WGBLn is adjusted substantially differently from the form of the write pulse Wpulse.

Specifically, the rate at which the write global bit lines WGBL0 to WGBLn are occupied in the nonvolatile memory device according to embodiments of the present invention varies depending on the rate at which the write pulse Wpulse changes from a low level to a high level, for example. However, the rate at which the write global bit lines WGBL0 to WGBLn are discharged may vary regardless of the rate at which the write pulse changes from high level to low level, for example. Also, the rate at which the level of the write current Icell flowing through the nonvolatile memory cell MC increases in response to the write pulse Wpulse varies depending on the rate at which the write global bit lines WGBL0 to WGBLn are occupied. However, the rate at which the level of the write current Icell decreases may change regardless of the rate at which the write global bit lines WGBL0 to WGBLn are discharged. That is, the occupancy of the write global bit lines WGBL0 to WGBLn affects the rate at which the level of the write current Icell is increased due to the change of the write pulse Wpulse from the low level to the high level. The discharge of the global bit lines WGBL0 to WGBLn is not affected by the change of the write pulse Wpulse from the high level to the low level and does not affect the rate at which the level of the write current Icell decreases.

In addition, in the memory device according to example embodiments, the discharge time td of the write global bit lines WGBL0 to WGBLn may include a charge time of the write global bit lines WGBL0 to WGBLn. longer than tc). Here, the charge time tc of the write global bit lines WGBL0 to WGBLn is a time for which the write global bit lines WGBL0 to WGBLn are charged to a predetermined voltage level by the charge unit 141_a, and the write global bit lines WGBL0. The discharge time td of ˜WGBLn may be a time when the write global bit lines WGBL0 to WGBLn are discharged again at the predetermined voltage level by the discharge unit 141_b. Specifically, a relatively high peak level as well as a case where a set pulse including a current pulse that includes a plurality of stages or a current pulse that decreases along a predetermined slope while maintaining a peak period for a predetermined period is provided. Even when a reset pulse having a relatively narrow pulse width is provided, the time for which the write global bit lines WGBL0 to WGBLn are discharged again at a predetermined voltage level is relatively longer than the time for which the predetermined voltage level is charged. Can be.

That is, the discharge time td of the write global bit line of the nonvolatile memory device according to the embodiments of the present invention passes through the nonvolatile memory cell MC of the first memory banks 110_1 to 110_8. Longer than the quenching time tq of Icell). The discharge time td is, for example, at least twice as long as the quench time tq, so that the write global bit line is relatively fast compared to the current Icell flowing through the nonvolatile memory cell MC. (WGBL0 to WGBLn) can be discharged slowly enough. Here, the quenching time tq may refer to the time when the level of the current Icell flowing through the nonvolatile memory cell MC decreases from a predetermined level.

Specifically, when the write global bit lines WGBL0 to WGBLn are discharged again after being received with the write pulse Wpulse at a predetermined voltage level, the write global bit lines WGBL0 to WGBLn are rapidly lowered. It will be slowly lowered for a predetermined time without losing. On the other hand, unlike the write global bit lines WGBL0 to WGBLn, the level of the write current Icell is adjusted depending on the set pulse or the reset pulse, and may be sharply reduced within a short time when the reset pulse is provided.

Accordingly, the nonvolatile memory device in accordance with embodiments of the present invention can stably write not only set data but also reset data requiring very short quenching time in the nonvolatile memory cell MC. In addition, the second memory is read through the read global bit lines RGBL0 to RGBLn while data is written to the nonvolatile memory cells MC of the first memory banks 110_1 to 110_8 through the write global bit lines WGBL0 to WGBLn. When data is read from the nonvolatile memory cells of the banks 110_1 to 110_8, errors in the read operation can be reduced. This will be described in detail with reference to FIGS. 3 and 7A to 7B.

7A to 7B illustrate errors in a read operation of a read global bit line by a write global bit line in a conventional nonvolatile memory device.

Referring to FIGS. 3 and 7A to 7B, in the conventional nonvolatile memory device, the levels of the write global bit lines WGBL0 to WGBLn are adjusted in response to the write pulses Wpulse. Specifically, as the write pulse Wpulse changes from the low level to the high level, the level of the write global bit lines WGBL0 to WGBLn is occupied by a predetermined voltage level at the ground voltage level. In addition, as the write pulse Wpulse changes from the high level to the low level, the level of the write global bit lines WGBL0 to WGBLn is discharged from the predetermined voltage level to the ground voltage level.

As a result, the amount of the write current Icell passing through the nonvolatile memory cell MC coupled to the write global bit lines WGBL0 to WGBLn may be adjusted. Specifically, as the write pulse Wpulse changes from the low level to the high level, the write global bit lines WGBL0 to WGBLn are occupied to increase the amount of the write current Icell, and the write pulse Wpulse at the high level. As the low level changes, the write global bit lines WGBL0 to WGBLn are discharged to reduce the amount of the write current Icell. In other words, the level change form of the write global bit lines WGBL0 to WGBLn and the level change form of the write current Icell are substantially similar to the form of the write pulse Wpulse provided to the write global bit lines WGBL0 to WGBLn. Can be adjusted.

However, in the nonvolatile memory device operating as described above, an error may occur in a read operation for reading data due to a change in the level of the write global bit lines WGBL0 to WGBLn. Specifically, between the write global bit lines WGBL0 to WGBLn and the selected local bit lines BL0 to BL3 in the memory banks 110_1 to 110_8 where the read operation is performed, and the read global bit lines WGBL0 to WGBLn adjacent to the write global bit lines WGBL0 to WGBLn. Parasitic capacitors Cp1 and Cp2 exist between the bit lines RGBL0 to RGBLn, so that the level change of the write global bit lines WGBL0 to WGBLn is changed to the local bit lines BL0 to BL3 and / or the read global bit lines May affect the levels of RGBL0 to RGBLn).

For example, when the write global bit lines WGBL0 to WGBLn are discharged as the write pulse Wpulse changes from the high level to the low level, the level of the write global bit lines WGBL0 to WGBLn is rapidly lowered so that the local The levels of the bit lines BL0 to BL3 and / or the read global bit lines RGBL0 to RGBLn may be lowered by the parasitic capacitors Cp1 and Cp2 as shown in FIG. 7A. As a result, when the level of the local bit lines BL0 to BL3 or the read global bit lines RGBL0 to RGBLn is lowered as shown in FIG. 7B, the read circuit 145 of the nonvolatile memory device is configured to perform nonvolatile memory cells. The resistance leads to a lower level than the resistance of the cell stored in the MC. That is, due to the level change of the write global bit lines WGBL0 to WGBLn, an error that leads to a resistance different from that of the cell stored in the nonvolatile memory cell MC may occur.

This read error is especially true for write global bit lines WGBL0 to WGBLn over time when a reset pulse having a relatively high peak level and relatively narrow pulse width is provided to the write global bit lines WGBL0 to WGBLn. More level variations can occur since they can be relatively larger than when set pulses are provided. Also, when a reset pulse is provided, the write pulse is typically written as the reset pulse is changed from the high level to the low level, rather than the time taken by the write global bit lines WGBL0 to WGBLn as the reset pulse is changed from the low level to the high level. Since the time for which the global bit lines WGBL0 to WGBLn are discharged is shorter, more read errors may occur when the reset pulse changes from a high level to a low level.

However, in the nonvolatile memory device according to example embodiments of the inventive concept, even when the write global bit lines WGBL0 to WGBLn are changed from the high level to the low level, the write global bit lines WGBL0 to WGBLn are not. Since it is discharged within a short time and its level is not drastically lowered, it is possible to reduce an error in the read operation as described above. In addition, unlike the write global bit lines WGBL0 to WGBLn, the amount of the write current Icell is adjusted depending on the set pulse or the reset pulse, and in particular, when the reset pulse is provided, the amount decreases rapidly in a short time. Data corresponding to a predetermined resistance level can be stably written to the volatile memory cell MC.

Hereinafter, a nonvolatile memory device according to some embodiments of the present invention will be described in detail with reference to FIGS. 8 and 9.

8 is a timing diagram illustrating an operation of a nonvolatile memory device in accordance with some embodiments of the inventive concept.

Referring to FIG. 8, when a nonvolatile memory device writes data corresponding to a predetermined resistance level to a nonvolatile memory cell using a write pulse, a write global bit line may be used. (WGBL0 to WGBLn) is discharged again after receiving the write pulse (Wpulse) and occupies a predetermined level, but the period (td) and the word line (WL0 to WLm) where the write global bit lines (WGBL0 to WGBLn) are discharged. At least a portion of the disable period tdis may overlap. In addition, a period where the local bit lines BL0 to BL3 coupled to the write global bit lines WGBL0 to WGBLn are discharged may also partially overlap the disable period tdis of the word lines WL0 to WLm. .

Here, in the disable period tdis of the word lines WL0 to WLm, the word lines WL0 to WLm are again enabled after the word lines WL0 to WLm are adjusted to a voltage level equal to, for example, the ground voltage level. ) May be, for example, a period after being adjusted to a voltage level equal to the boosted voltage VPP and disabled. In addition, the nonvolatile memory device may write data to nonvolatile memory cells MC of the memory banks 110_1 to 110_8 through the write global bit lines WGBL0 to WGBLn as described above. The data may be read from the nonvolatile memory cells MC of the second memory banks 110_1 to 110_8 of the plurality of memory banks 110_1 to 110_8 through the read global bit lines RGBL0 to RGBLn.

Specifically, during the write operation, the word lines WL0 to WLm are first adjusted to a voltage level such as, for example, the ground voltage level using the row decoder 120 to enable the word lines. Further, the local bit line (e.g., BL0) and the write global bit line (e.g., WGBL0) are selected and written by the write local bit line selection circuit 151 and the global bit line selection circuit (see 130 in FIG. 1). Volatile memory cell MC is selected. Here, the word lines WL0 to WLm may be selected before the write global bit lines WGBL0 to WGBLn and the local bit lines BL0 to BL3, and in some cases, the write global bit lines WGBL0 to WGBLn and the local bits. It may be selected later than the lines BL0 to BL3 or simultaneously selected.

As the write pulse Wpulse provided to the write global bit lines WGBL0 to WGBLn is changed from the low level to the high level, the write global bit lines WGBL0 to WGBLn are charged at a predetermined voltage level. As the write global bit lines WGBL0 to WGBLn occupy a predetermined voltage level, the write current Icell is coupled to the write global bit lines WGBL0 to WGBLn via the local bit lines BL0 to BL3. It flows through the nonvolatile memory cell MC to the word lines WL0 to WLm.

The level of the light current Icell increases as the light pulse Wpulse changes from the low level to the high level. As the light pulse Wpulse maintains the peak level, the light current Icell also maintains the peak level. have.

Meanwhile, in the nonvolatile memory device according to some embodiments of the present invention, before the level of the write pulse Wpulse is changed to the low level, the word lines WL0 to WLm are at the same voltage level as, for example, the boost power supply VPP. The word line is adjusted to disable it. Specifically, while the level of the write pulse Wpulse is maintained at the high level, or while the level of the write pulse Wpulse is changed from the high level to the low level, the word lines WL0 to WLm are adjusted to the boost voltage VPP at the ground level, for example, so that the word line is adjusted. (WL0 to WLm) may be disabled. That is, before the write pulse Wpulse becomes low, the selection of the nonvolatile memory cell MC to be written may be released. An exemplary circuit for implementing such an operation will be described in detail with reference to FIG. 9.

As a result, the word lines WL0 to WLm are disabled, so that the write current Icell can not penetrate the nonvolatile memory cell MC to the word lines WL0 to WLm. That is, since the word lines WL0 to WLm are disabled, the level of the write current Icell may drop rapidly as shown in FIG. 8 regardless of the level change of the write global bit lines WGBL0 to WGBLn. will be. On the other hand, the write global bit lines WGBL0 to WGBLn may use the quenching time tq of the write current Icell using the discharge unit 141_b of the write driver, for example, regardless of the level change of the write current Icell. It can be discharged to a predetermined voltage slowly for a relatively long time. In other words, the discharge time td of the write global bit lines WGBL0 to WGBLn and / or the discharge time of the local bit lines BL0 to BL3 coupled with the write global bit lines WGBL0 to WGBLn are non-disabled. It may be longer than the quenching time tq of the write current Icell flowing through the volatile memory cell MC.

Therefore, in the nonvolatile memory device according to some embodiments of the present invention, the level of the write current Icell flowing through the nonvolatile memory cell MC is rapidly lowered for a short time, while the local bit lines BL0 to BL3 are used. And / or the level of the write global bit lines WGBL0 to WGBLn may be slowly lowered for a predetermined time without being drastically lowered for a short time. As a result, while stably writing data corresponding to a predetermined resistance level in the nonvolatile memory cell MC, an error during read operation due to a sudden level change of the write global bit lines WGBL0 to WGBLn can be reduced.

9 is an exemplary circuit diagram illustrating a nonvolatile memory device in accordance with some embodiments of the present invention. FIG. 9 is an exemplary circuit diagram for implementing the method of driving the nonvolatile memory device of FIG. 8, and may be variously modified by those skilled in the art.

Referring to FIG. 9, the write driver 141 provides the write pulse Wpulse to the write global bit lines WGBL0 to WGBLn in response to the write signal P_Wpulse, and the charge unit 141_a and the discharge unit ( 141_b). The write signal P_Wpulse may include a reset write signal providing a reset pulse and a set write signal providing a set pulse.

The charge unit 141_a occupies the write global bit lines WGBL0 to WGBLn in response to the write signal P_Wpulse, and is charged between the boost power supply VPP and the write global bit lines WGBL0 to WGBLn. MP1). On the other hand, unlike the charge unit 141_a, the discharge unit 141_b discharges the write global bit lines WGBL0 to WGBLn in response to the write signal P_Wpulse, and the ground voltage and the write global bit lines WGBL0 to WGBLn. It may include a discharge transistor (MP2) coupled between. The charge unit 141_a and the discharge unit 141_b, for example, occupy the write global bit lines WGBL0 to WGBLn in response to the high level write signal P_Wpulse, and respond to the low level write signal P_Wpulse. As a result, the write global bit lines WGBL0 to WGBLn may be discharged to complementarily operate in response to the write signal P_Wpulse.

In particular, in the nonvolatile memory device in accordance with some embodiments of the present invention, the discharge unit 141_b of the write driver 141 discharges the write global bit lines WGBL0 to WGBLn from the write driver 141. The charge portion 141_a may be slower than a speed of occupying the write global bit lines WGBL0 to WGBLn. That is, the discharge time td of the write global bit lines WGBL0 to WGBLn using the discharge unit 141_b of the write driver 141 is the write global bit line using the charge unit 141_a of the write drive 141. It may be longer than the charge time tc of (WGBL0 to WGBLn). As a result, the level of the write global bit lines WGBL0 to WGBLn is rapidly increased while the level is occupied while the write global bit lines WGBL0 to WGBLn are rapidly lowered while the level is being discharged. Can be lowered slowly for a predetermined time without being lost.

Here, the discharge time td of the write global bit lines WGBL0 to WGBLn () using the discharge unit 141_b is longer than the charge time tc of the write global bit lines WGBL0 to WGBLn using the charge unit 141_a. There are many ways to do this. For example, the level of the signal applied to the gate of the discharge transistor MP2 may be lower than that of the charge transistor MP1, or the resistance of the discharge transistor MP2 may be greater than that of the charge transistor MP1. Here, the larger resistance of the discharge transistor MP2 than the charge transistor MP1 is, for example, by making the doping concentration of the channel region of the discharge transistor MP2 higher than the doping concentration of the channel region of the charge transistor MP1. By increasing the threshold voltage Vth, reducing the length of the channel region, or making the channel region larger, the ratio of the width Wd and the length L of the channel region, that is, the W / L, is increased. The size of the charge transistor MP1 may be larger than that of the transistor MP2.

Meanwhile, the write local bit line select circuit 151 selectively couples the write global bit lines WGBL0 to WGBLn and the local bit lines BL0 to BL3 using the write local bit line select signal (eg, WLY00). .

In addition, the row decoder 120 adjusts the voltage level of the word lines WL0 to WLm using the word line selection signals LX0 to LXm and the write signal P_Wpulse to adjust at least one of the word lines WL0 to WLm. Selects the word lines WL0 to WLm, and includes a pull-up element 121 and a pull-down element 123.

The pull-up element 121 adjusts the word lines WL0 to WLm to the same voltage level as, for example, the boost power supply VPP_X, using the word line selection signals LX0 to LXm and the write signal P_Wpulse. You can disable it. The pull-up element 121 may include, for example, a PMOS transistor coupled between the word lines WL0 to WLm and the boosted power supply VPP_X.

On the other hand, the pull-down element 123 adjusts the word lines WL0 to WLm to a voltage level such as, for example, the ground voltage level in response to the word line selection signals LX0 to LXm and the write signal P_Wpulse, thereby adjusting the word lines. It can be enabled. For example, the pull-down device 123 may be coupled between the word lines WL0 to WLm and the ground voltage and include an NMOS transistor.

Here, the gates of the PMOS transistors of the pull-up element 121 and the gates of the NMOS transistors of the pull-down element 123 are the signals obtained by AND calculating the word line selection signals LX0 to LXm and the write signal P_Wpulse as shown in the figure. Can be applied. Table 1 shows the signals LX ′ provided to the pull-up element 121 and the pull-down element 123 according to the word line selection signals LX0 to LXm and the write signal P_Wpulse.

LX L L H H P_Wpulse L H H L LX ' L L H L

Referring to Table 1, the signal LX 'provided to the pull-up element 121 and the pull-down element 123 only when the levels of the write signal P_Wpulse and the word line selection signals LX0 to LXm are high. Becomes the high level. Accordingly, the pull-up element 121 is disabled and the pull-down element 123 is enabled so that the word lines WL0 to WLm may be adjusted and enabled, for example, at a voltage level such as the ground voltage level.

On the other hand, as the write signal P_Wpulse changes from the high level to the low level, the signal LX provided to the pull-up element 121 and the pull-down element 123 regardless of the level of the word line selection signals LX0 to LXm. ') Goes low. Accordingly, the pull-down element 123 may be disabled and the pull-up element 121 may be enabled, such that the word lines WL0 to WLm may be adjusted to be disabled at the same voltage level as, for example, the boost power supply VPP_X.

As a result, the level of the write current Icell may drop rapidly regardless of the level change of the write global bit lines WGBL0 to WGBLn as shown in FIG. 8. In addition, the discharge unit 141_b of the write driver 141 discharges the write global bit lines WGBL0 to WGBLn relatively slowly in response to the low level write signal P_Wpulse, and thus the write global bit lines WGBL0 to The level of WGBLn) can be lowered slowly for a predetermined time without being drastically lowered for a short time.

Hereinafter, a nonvolatile memory device according to some other embodiments of the present invention will be described in detail with reference to FIGS. 10 and 11.

10 is a timing diagram illustrating an operation of a nonvolatile memory device in accordance with some other embodiments of the present invention.

Unlike the nonvolatile memory device of FIG. 8, the nonvolatile memory device according to the embodiment of FIG. 10 uses decoupling of the local bit lines BL0 to BL3 and the write global bit lines WGBL0 to WGBLn. 5, the levels of the write global bit lines WGBL0 to WGBLn, the write current Icell, and the read global bit lines RGBL0 to RGBLn may be implemented. Hereinafter, for convenience of description, a detailed description of operations substantially the same as in the embodiment of FIG. 8 will be omitted.

Referring to FIG. 10, when a nonvolatile memory device writes data corresponding to a predetermined resistance level to a nonvolatile memory cell using a write pulse, a write global bit may be used. The lines WGBL0 to WBGLn receive the write pulse Wpulse and are discharged again after being charged to a predetermined level, and the interval td where the write global bit lines WGBL0 to WGBLn are discharged is local bit line BL0. At least partially overlaps the period tdc at which ~ BL3) and the write global bit lines WGBL0 to WGBLn are decoupled. Here, the section tdc decoupled between the local bit lines BL0 to BL3 and the write global bit lines WGBL0 to WGBLn may include the write global bit lines WGBL0 to WGBLn selected by the write local bit line selection circuit. After the lines BL0 to BL3 are coupled, this may be an interval after the write local bit lines BL0 to BL3 and the local bit lines BL0 to BL3 are decoupled. In addition, the nonvolatile memory device in accordance with some embodiments of the present invention transmits data to the nonvolatile memory cells MC of the memory banks 110_1 to 110_8 through the write global bit lines WGBL0 to WGBLn. While writing, data may be read from the nonvolatile memory cells MC of the second memory banks 110_1 to 110_8 of the plurality of memory banks 110_1 to 110_8 through the read global bit lines RGBL0 to RGBLn.

Specifically, in the write operation, first, the word lines WL0 to WLm are adjusted to a voltage level such as, for example, the ground voltage level using the row decoder 120 to enable the word line, and the write local bit line selection circuit ( The local bit line (eg, BL0) and the write global bit line (eg, WGBL0) are selected by the 151 and the global bit line selection circuit (see 130 of FIG. 1) to select the nonvolatile memory cell MC to be written. .

As the write pulses Wpulse provided to the write global bit lines WGBL0 to WGBLn change from a low level to a high level, the write global bit lines WGBL0 to WGBLn occupy a predetermined voltage level. As the write global bit lines WGBL0 to WGBLn occupy a predetermined voltage level, the write current Icell is coupled to the write global bit lines WGBL0 to WGBLn via the local bit lines BL0 to BL3. It flows through the volatile memory cell MC to the word lines WL0 to WLm.

Meanwhile, in the nonvolatile memory device according to some other embodiments of the present invention, before the level of the write pulse Wpulse is changed to the low level, the write global bit lines WGBL0 to WGBLn and the local bit lines BL0 to BL3 are connected. Decoupled. In detail, the write global bit lines WGBL0 to WGBLn and the local bit lines BL0 to BL3 are written to the write local bit line while the level of the write pulse Wpulse is maintained at the high level or is changed from the high level to the low level. Decoupled by a selection circuit 151. That is, before the write pulse Wpulse becomes the low level, selection of the nonvolatile memory cell MC to be written is released. An exemplary circuit for implementing such an operation will be described in detail with reference to FIG. 11.

As a result, the write global bit lines WGBL0 to WGBLn and the nonvolatile memory cell MC are decoupled so that the write current Icell passes through the nonvolatile memory cell MC and flows through the word lines WL0 to WLm. The level of the current Icell is lowered. That is, since the write global bit lines WGBL0 to WGBLn and the local bit lines BL0 to BL3 or the write global bit lines WGBL0 to WGBLn and the nonvolatile memory cells MC are decoupled from each other, the write global bit lines WGBL0 are decoupled. Regardless of the level change of ˜WGBLn, the level of the write current Icell may drop rapidly as shown in FIG. 8. On the other hand, the write global bit lines WGBL0 to WGBLn may use the quenching time tq of the write current Icell using the discharge unit 141_b of the write driver, for example, regardless of the level change of the write current Icell. In comparison, the voltage can be discharged slowly over a relatively long time. In other words, the discharge time td of the write global bit lines WGBL0 to WGBLn is the quenching time tq of the write current Icell flowing through the nonvolatile memory cell MC or the local bit lines BL0 to BL3. May be longer than the discharge time.

Accordingly, in the nonvolatile memory device according to some embodiments of the present invention, the level of the write current Icell and / or the level of the local bit lines BL0 to BL3 flowing through the nonvolatile memory cell MC may be reduced for a short time. While sharply lowered, the level of the write global bit lines WGBL0 to WGBLn may be lowered slowly for a predetermined time without being abruptly lowered for a short time. As a result, while stably writing data corresponding to a predetermined resistance level in the nonvolatile memory cell MC, an error during read operation due to a sudden level change of the write global bit lines WGBL0 to WGBLn can be reduced.

11 is an exemplary circuit diagram illustrating a nonvolatile memory device in accordance with some embodiments of the present invention. FIG. 11 is an exemplary circuit diagram for implementing the method of driving the nonvolatile memory device of FIG. 10, and may be variously modified by those skilled in the art.

Referring to FIG. 11, although the example circuit according to the embodiment of FIG. 11 is substantially similar to the example circuit according to the embodiment of FIG. 9, the write local bit line select circuit 151 may use the write local bit line select signal ( For example, there may be a difference in coupling the write global bit lines WGBL0 to WGBLn and the local bit lines BL0 to BL3 using the WLY00 and the write signal P_Wpulse. In addition, unlike the embodiment of FIG. 9, in the embodiment of FIG. 11, the row decoder 120 may adjust the voltage levels of the word lines WL0 to WLm using only the word line selection signal (eg, LXm). Hereinafter, for convenience of description, detailed description of the substantially the same components as in the embodiment of Figure 9 will be omitted.

Specifically, the write local bit line selection circuit 151 uses the write signal P_Wpulse and the write local selection signals WLY00 to WLY73 to write the write global bit lines WGBL0 to WGBLn and the local bit lines BL0 to BL3. Is optionally coupled. The write local bit line selection circuit 151 includes, for example, a plurality of selection elements (eg, NMOS transistors) interposed between each write global bit line WGBL0 to WGBLn and the plurality of local bit lines BL0 to BL3. can do.

Here, the gates of the selection elements of the write local bit line selection circuit 151 are the signals WLY'00 to WLY that AND-operates the write local bit line selection signals WLY00 to WLY73 and the write signal P_Wpulse as shown in the drawing. '73 may be applied. Table 2 shows the signals WLY'00 to WLY'73 provided to the selection device according to the write local bit line selection signals WLY00 to WLY73 and the write signal P_Wpulse.

WLY L L H H P_Wpulse L H H L WLY ' L L H L

Referring to Table 2, when the level of the write signal P_Wpulse and the write local bit line selection signals WLY00 to WLY73 are both at the high level, the signal provided to the selection element of the write local bit line selection circuit 151 ( WLY'00 to WLY'73) become the high level. Accordingly, the select device is enabled, so that the write global bit lines WGBL0 to WGBLn and the local bit lines BL0 to BL3 and / or the nonvolatile memory cell MC may be coupled.

On the other hand, as the write signal P_Wpulse changes from the high level to the low level, the signal WLY'00 to WLY'73 provided to the selection device regardless of the level of the write local bit line selection signals WLY00 to WLY73. Goes to the low level. As a result, the selection device may be disabled to decouple the write global bit lines WGBL0 to WGBLn, the local bit lines BL0 to BL3, and / or the nonvolatile memory cell MC.

As a result, the level of the write current Icell drops rapidly regardless of the level change of the word write global bit lines WGBL0 to WGBLn as shown in FIG. 10. In addition, the discharge unit 141_b of the write driver 141 discharges the write global bit lines WGBL0 to WGBLn relatively slowly in response to the low level write signal P_Wpulse, and thus the write global bit lines WGBL0 to The level of WGBLn) can be lowered slowly for a predetermined time without being drastically lowered for a short time.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

1 and 2 are block diagrams and circuit diagrams for describing a nonvolatile memory device according to example embodiments.

3 is a diagram illustrating a write operation and / or a read operation of a nonvolatile memory device according to example embodiments.

FIG. 4 is a view illustrating a condition for phase change of a phase change material included in a nonvolatile memory cell during a write operation.

5 is a timing diagram illustrating an operation of a nonvolatile memory device according to example embodiments.

6 is a diagram illustrating a write operation and / or a read operation of a nonvolatile memory device according to another exemplary embodiment of the present invention.

9 is an exemplary circuit diagram illustrating a nonvolatile memory device in accordance with some embodiments of the present invention.

11 is an exemplary circuit diagram illustrating a nonvolatile memory device in accordance with some other embodiments of the present invention.

(Explanation of symbols for the main parts of the drawing)

110_1 to 110_8: Memory bank 120: Low driver

130: global bit line selection circuit 140: input / output circuit

141: light driver 141_a: charge portion

141_b: discharge unit 143: lead circuit

150: local bit line selection circuit

151: write local bit line selection circuit

153: Lead Local Bit Line Selection Circuit

Claims

A plurality of memory banks, each memory bank comprising: a plurality of memory banks comprising a matrix of a plurality of nonvolatile memory cells having different resistance levels in accordance with data stored therein;

A plurality of write global bit lines, each write global bit line arranged to be shared in the plurality of memory banks, the plurality of write global bit lines used when writing data in the plurality of memory banks; And

A plurality of word lines, each word line including a plurality of word lines coupled with rows of a plurality of nonvolatile memory cells in the memory bank,

When data is written to the nonvolatile memory cell using a write pulse, the write global bit line is discharged after receiving the write pulse and being charged to a predetermined level.

And a period in which the write global bit line is discharged and the disable period of the word line at least partially overlap.

The method of claim 1,

A plurality of read global bit lines, wherein each read global bit line is arranged to be shared in the plurality of memory banks, further comprising a read global bit line used when reading data in the plurality of memory banks,

Non-volatile memory cells of a second memory bank of the plurality of memory banks through the read global bit line, while writing data to the non-volatile memory cells of the first memory bank of the plurality of memory banks through the write global bit line A nonvolatile memory device that reads data from.

The method of claim 1,

And a write driver providing the write pulse to the write global bit line in response to a write signal.

The method of claim 3,

The write driver may include a charge unit occupying the write global bit line and a discharge unit discharging the write global bit line.

The discharge time of the write global bit line using the discharge unit is longer than the charge time of the write global bit line using the charge unit.

The method of claim 4, wherein

The charge unit may include a charge transistor and the discharge unit may include a discharge transistor.

The resistance of the charge transistor is less than the resistance of the discharge transistor.

The method of claim 3,

And a row decoder to disable the word line using a word line select signal and the write signal.

The method of claim 1,

The discharge time of the write global bit line is longer than the charge time of the write global bit line.

The method of claim 1,

A plurality of local bit lines selectively coupled with each write global bit line, each local bit line further comprising a plurality of local bit lines coupled with a column of a plurality of nonvolatile memory cells in the memory bank,

The local bit line is discharged after receiving the write pulse through the write global bit line and occupied at a predetermined level. The local bit line overlaps the interval where the local bit line is discharged and the disable period of the word line. Nonvolatile Memory Device.

The method of claim 8,

A plurality of write bit line selection circuits, each write bit line selection circuit further comprising a plurality of write bit line selection circuits for selectively coupling each of the write global bit lines and the plurality of local bit lines;

And when writing data to the nonvolatile memory cell, each write global bit line is coupled with the nonvolatile memory cell through at least two write local bit line selection circuits.

The method of claim 1,

And the nonvolatile memory cell is a phase change memory cell.

A plurality of write global bit lines, each write global bit line arranged to be shared in the plurality of memory banks, the plurality of write global bit lines used when writing data in the plurality of memory banks;

A plurality of word lines, each word line comprising: a plurality of word lines coupled with rows of a plurality of nonvolatile memory cells in the memory bank;

A write driver providing a write pulse to the write global bit line in response to a write signal when writing data to the nonvolatile memory cell; And

And a row decoder configured to determine a level of the word line in response to a word line selection signal and the write signal.

The method of claim 11,

The write driver may include a charge unit occupying the write global bit line and a discharge unit discharging the global bit line.

The method of claim 11,

And. The data written to the nonvolatile memory cell is reset data.

The method of claim 11,

A plurality of local bit lines selectively coupled with each write global bit line, each local bit line having a plurality of local bit lines coupled with a column of a plurality of nonvolatile memory cells in the memory bank;

A plurality of local bit line selection circuits, each write bit line selection circuit further comprising a plurality of write bit line selection circuits for selectively coupling each of the write global bit lines and the plurality of local bit lines;

The method of claim 11,

And the nonvolatile memory cell is a phase change memory cell.