KR20100020149A - Circuit for generating column selection pulse of semiconductor memory apparatus - Google Patents

Abstract

PURPOSE: A circuit for generating a column selection pulse of a semiconductor memory apparatus is provided to enhance the data input/output stability of a semiconductor memory device by controlling the length of an enable section of a column selection pulse according to a frequency change of a clock. CONSTITUTION: A column selection pulse generating part(10) enables a column selection pulse in response to a read pulse or a write pulse. The column selection pulse generating part disables the column selection pulse in response to the control signal. A controller(100) outputs the control signal when a column burst count signal is enabled. The column burst count signal is enabled from a point of time when either of the read pulse or the write pulse is enabled. The length of the enable section of the column burst count signal is determined according to the burst length value selected in the semiconductor memory device.

Description

Circuit for Generating Column Selection Pulse of Semiconductor Memory Apparatus

TECHNICAL FIELD The present invention relates to semiconductor memory devices, and more particularly, to a column select pulse generation circuit.

As shown in FIG. 1, a column select pulse generation circuit of a general semiconductor memory device includes a column select pulse generator 10 and a delay unit 20.

The column select pulse generator 10 enables the column select pulse YS at the enable timing of the read or write pulses IRDP and IWTP, and when the delay column select pulse YS_d is enabled, the column select pulse. Disable (YS). In this case, when a read or write command is input to the semiconductor memory device, the read or write pulses IRDP and IWTP are generated at the rising timing of the clock in the semiconductor memory device.

The delay unit 20 delays the column select pulse YS to generate the delay column select pulse YS_d and outputs the delay column select pulse YS_d to the column select pulse generator 10. The delay unit 20 is composed of a commonly used RC delay.

Accordingly, the column select pulse generation circuit of the general semiconductor memory device determines the enable timing of the column select pulse YS in response to the read or write pulses IRDP and IWTP, and the delay time of the delay unit 20 is determined. The enable time of the column select pulse YS is determined. As a result, the column selection pulse YS has an enable period having the same time as the delay time of the delay unit 20.

The column select pulse YS is used as a column select signal in combination with a column address. The column select signal connects the bit line and the local data line during its enable period. In this case, the enable period of the column select pulse YS and the enable period of the column select signal are the same. Therefore, the bit line and the local data line are connected during the enable period of the column select pulse YS.

In designing a semiconductor memory device, the length of the enable period of the column selection pulse YS is determined according to the highest operating speed at which the semiconductor memory device can operate. As a result, the length of the enable period of the column select pulse YS is determined to be the minimum length that can connect the bit line and the local data line to transfer data.

The semiconductor memory device generates and operates the column selection pulse YS having an enable period of minimum length even when operating in synchronization with a low frequency. Therefore, the semiconductor memory device has a tight data transfer margin even when operating in synchronization with a low frequency, although the data transfer margin between the bit line and the local data line can be sufficiently obtained.

Disclosure of Invention The present invention has been made to solve the above-described problem, and an object thereof is to provide a column selection pulse generation circuit of a semiconductor memory device capable of controlling the length of an enable period of a column selection pulse according to a change in a frequency of a clock. .

A column select pulse generation circuit of a semiconductor memory device according to an embodiment of the present invention enables column select pulse generation in response to a read pulse or a write pulse, and generates a column select pulse for disabling the column select pulse in response to a control signal. And a controller for dividing a clock and outputting the clock as the control signal when the column burst count signal is enabled.

The column select pulse generation circuit of the semiconductor memory device according to another embodiment of the present invention determines an enable timing of a control signal in response to a read or write command, and determines an enable interval length of the control signal according to a clock frequency. And a column select pulse generator configured to enable a column select pulse in response to the read or write command and to disable the column select pulse in response to the control signal.

According to another embodiment of the present invention, a column select pulse generation circuit of a semiconductor memory device may include a controller configured to enable a control signal at a rising timing of a clock after the column select pulse is enabled, and one of the read pulse and the write pulse may be enabled. And a column select pulse generator for enabling the column select pulse and disabling the column select pulse when the control signal is enabled.

The column select pulse generation circuit of the semiconductor memory device according to another embodiment of the present invention enables the column select pulse when one of the read pulse and the write pulse is enabled, and the input of the column select pulse for a predetermined period of the clock. It is characterized by maintaining the enabled state.

The column selection pulse generation circuit of the semiconductor memory device according to the present invention can control the length of the enable period of the column selection pulse according to the frequency change of the clock, thereby increasing the data input / output stability of the semiconductor memory device.

As shown in FIG. 2, the column select pulse generation circuit of the semiconductor memory device according to the embodiment of the present invention includes a column select pulse generator 10 and a controller 100.

The column select pulse generator 10 enables the column select pulse YS when one of the read pulse IRDP or the write pulse IWTP is enabled, and selects the column when the control signal ctrl is enabled. Disable pulse YS. At this time, the read pulse IRDP is a signal generated in the semiconductor memory device in synchronization with the clock CLK when a read command is input to the semiconductor memory device. The write pulse IWTP is a signal generated in the semiconductor memory device in synchronization with the clock CLK when a write command is input to the semiconductor memory device.

When the column burst count signal CBSTC is enabled, the controller 100 divides the clock CLK into two and outputs the control signal ctrl. In addition, the controller 100 is initialized when the column burst count signal CBSTC is disabled. In this case, the column burst count signal CBSTC is enabled from a time point when one of the read pulse IRDP or the write pulse IWTP is enabled, and the burst burst value is set to a burst length value preset in the semiconductor memory device. Accordingly, the length of the enable period is determined. For example, the length of the enable period of the column burst count signal CBSTC is equal to the length of two cycles of the clock CLK when the burst length is set to 4 in the semiconductor memory device.

As illustrated in FIG. 3, the controller 100 includes a flip flop FF11 and an inverter IV11.

The flip-flop FF11 receives the clock CLK at a clock input terminal and receives the column burst count signal CBSTC at a reset terminal RST. The inverter IV11 is connected to an output terminal Q of the flip flop FF11 to an input terminal and an input terminal D of the flip flop FF11 to an output terminal. In this case, the control signal ctrl is output at the output terminal of the flip flop FF11.

The flip-flop FF11 transitions the level of the control signal ctrl whenever the clock CLK transitions to a high level when the column burst count signal CBSTC is enabled. In addition, the flip-flop FF11 fixes the control signal ctrl to a low level regardless of the clock CLK when the column burst count signal CBSTC is disabled. That is, the flip flop FF11 is initialized when the column burst count signal CBSTC is disabled.

An operation of the column select pulse generation circuit of the semiconductor memory device according to the embodiment of the present invention configured as described above will be described with reference to FIG. 4.

When a read or write command is input to the semiconductor memory device, a read pulse IRDP or a write pulse IWTP is generated inside the semiconductor memory device. In addition, when the read pulse IRDP or the write pulse IWTP is enabled, the column burst count signal CBSTC is enabled. In this case, the semiconductor memory device assumes that the burst length is 4, and the length of the enable period of the column burst count signal CBSTC is equal to two periods of the clock CLK.

The column select pulse generator 10 enables the column select pulse YS when the read pulse IRDP or the write pulse IWTP is enabled.

The controller 100 generates a control signal ctrl that transitions to a high level when the clock CLK transitions to a high level after the column burst count signal CBSTC is enabled.

When the control signal ctrl is enabled, the column select pulse generator 10 disables the column select pulse YS.

The controller 100 initializes the control signal ctrl to a low level when the column burst count signal CBSTC is disabled.

As a result, the column select pulse generation circuit of the semiconductor memory device according to the present invention generates a column select pulse YS that is enabled for one period of the clock CLK after the read or write pulses IRDP and IWTP are enabled. do.

Therefore, when the semiconductor memory device operates in synchronization with a clock having a high frequency, the enable period is shorter than that when the semiconductor selection device YS operates in synchronization with a clock of a low frequency. On the other hand, when the semiconductor memory device operates in synchronization with a clock having a low frequency, the enable period of the column select pulse YS is generated longer than when the semiconductor memory device operates in a clock having a high frequency.

The semiconductor memory device to which the column select pulse generation circuit according to the present invention is applied can control the length of the enable section of the column select pulse according to the clock frequency, that is, the operating speed of the semiconductor memory device. There is an effect to increase.

As shown in FIG. 5, a column select pulse generation circuit of a semiconductor memory device according to another embodiment of the present invention includes a column select pulse generator 10 and a controller 100-1.

The column select pulse generator 10 enables the column select pulse YS when one of the read pulse IRDP or the write pulse IWTP is enabled, and selects the column when the control signal ctrl is enabled. Disable pulse YS.

The controller 100-1 enables the control signal ctrl at the rising timing of the clock CLK after the column selection pulse YS is enabled. In addition, the control unit 100-1 disables the control signal ctrl after a predetermined time after the column select pulse YS is disabled.

As illustrated in FIG. 6, the controller 100-1 includes a pulse generator 110 and a clock divider 120.

The pulse generator 110 generates a reset pulse RST_P having the same enable timing as the column select pulse YS and a later disable timing than the column select pulse YS.

The pulse generator 110 may include a delay element, a NOR gate NOR21, and a first inverter IV21. The delay element receives the column select pulse YS. The NOR gate NOR21 receives an output signal of the delay element and the column select pulse YS. The first inverter IV21 receives the output signal of the NOR gate NOR21 and outputs the reset pulse RST_P.

When the reset pulse RST_P is enabled, the clock divider 120 divides the clock CLK into two and outputs the control signal ctrl. The clock divider 120 is initialized when the reset pulse RST_P is disabled. When the clock divider 120 is initialized, the clock divider 120 fixes the control signal ctrl to a specific level (for example, a low level) regardless of the clock CLK.

The clock divider 120 includes a flip flop FF21 and a second inverter IV22. The flip flop FF21 receives the clock CLK at a clock input terminal and receives the reset pulse RST_P at a reset terminal. In the second inverter IV22, an output terminal of the flip flop FF21 is connected to an input terminal and an input terminal of the flip flop FF21 is connected to an output terminal. In this case, the output signal of the flip flop FF21 is the control signal ctrl.

An operation of the column select pulse generation circuit of the semiconductor memory device according to another exemplary embodiment of the present invention configured as described above will be described with reference to FIG. 7.

When a read or write command is input to the semiconductor memory device, a read pulse IRDP or a write pulse IWTP synchronized with the clock CLK is generated in the semiconductor memory device.

The column select pulse generator 10 enables the column select pulse YS when one of the read pulse IRDP or the write pulse IWTP is enabled.

The controller 100-1 generates a reset pulse RST_P having the same enable timing as the enable timing of the column select pulse YS.

After the reset pulse RST_P is enabled, the controller 100-1 divides the clock CLK into two and outputs it as a control signal ctrl. That is, after the reset pulse RST_P is enabled, the control signal ctrl transitions to a high level at the rising timing of the clock CLK.

When the control signal ctrl is enabled at the high level, the column select pulse generator 10 disables the column select pulse YS.

The column selection pulse YS is disabled and the reset pulse RST_P is disabled after a predetermined time (after the delay time of the delay element shown in FIG. 6).

When the reset pulse RST_P is disabled, the controller 100-1 is initialized and the control signal ctrl is initialized to a low level regardless of the clock CLK.

As a result, since the column select pulse YS is enabled and disabled at the rising timing of the clock CLK, the length of the enable period of the column select pulse YS is one cycle length of the clock CLK. Becomes the same as

The column select pulse generation circuit according to the present invention controls the length of the enable period of the column select pulse YS to the same length as one period of the clock. Therefore, when the semiconductor memory device operates in synchronization with a low frequency clock, the semiconductor memory device generates a column selection pulse YS having a longer enable period than when operating in synchronization with a high frequency clock.

The semiconductor memory device to which the column select pulse generation circuit according to the present invention is applied can control the length of the enable section of the column select pulse according to the clock frequency, that is, the operating speed of the semiconductor memory device. There is an effect to increase.

As shown in FIG. 5, a column select pulse generation circuit of a semiconductor memory device according to another embodiment of the present invention includes a column select pulse generator 10 and a controller 100-1. However, the controller 100-1 is configured of the controller 100-2 shown in FIG. 8.

The column selection pulse generation circuit of the semiconductor memory device enables the column selection pulse YS when one of the read pulse IRDP and the write pulse IWTP is enabled, and the column selection pulse generation circuit enables the column selection pulse YS to be operated during a predetermined period of the clock CLK. The enable state of the column select pulse YS is maintained.

The column select pulse generator 10 enables the column select pulse YS when one of the read pulse IRDP or the write pulse IWTP is enabled, and when the control signal ctrl is enabled. The column selection pulse YS is disabled.

The controller 100-2 counts the period of the clock CLK in response to the column selection pulse YS. For example, the controller 100-2 counts the period of the clock CLK when the column select pulse YS is enabled. The controller 100-2 generates a count code CNT <1: 2 by counting a period of the clock CLK, and when the count code CNT <1: 2> is equal to a preset code, Enable the control signal ctrl. In addition, the controller 100-2 is disabled after the column selection pulse YS is initialized after a predetermined time. In this case, the initialized control unit 100-2 disables the control signal ctrl.

As illustrated in FIG. 8, the controller 100-2 includes a pulse generator 130, a count signal generator 140, and a control signal generator 150.

The pulse generator 130 has an enable timing that is the same as an enable timing of the column select pulse YS, and a reset pulse RST_P having a disable timing later than the disable timing of the column select pulse YS. Create

The pulse generator 130 may include a delay element, a first NOR gate NOR31, and a first inverter IV31. The delay element receives the column select pulse YS. The first NOR gate NOR31 receives an output signal of the column select pulse YS and the delay element. The first inverter IV31 receives the output signal of the first NOR gate NOR31 and outputs the reset pulse RST_P.

When the reset pulse RST_P is enabled, the count signal generator 140 divides the clock CLK into two to generate a first count signal CNT <1>, and divides the clock CLK into four divisions. A second count signal CNT <2> is generated and initialized when the reset pulse RST_P is disabled. In this case, the count code CNT <1: 2> includes the first and second count signals CNT <1> and CNT <2>. In addition, the initialized count signal generation unit 140 initializes both the first and second count signals CNT <1> and CNT <2> to a low level.

The count signal generator 140 includes a first clock divider 141 and a second clock divider 142.

When the reset pulse RST_P is enabled, the first clock divider 141 divides the clock CLK into two to generate a divided clock CLK_2, and generates the divided clock CLK_2 by the first clock divider CLK_2. It outputs as a count signal CNT <1>. In addition, the first clock divider 141 is initialized when the reset pulse RST_P is disabled. The initialized first clock divider 141 initializes the first count signal CNT <1> to a low level regardless of the clock CLK.

The first clock divider 141 includes a first flip flop FF31 and a second inverter IV32. The first flip flop FF31 receives the clock CLK at a clock input terminal and the reset pulse RST_P at a reset terminal. An output terminal Q of the first flip flop FF31 is connected to an input terminal of the second inverter IV32, and an input terminal of the first flip flop FF31 is connected to an output terminal of the second inverter IV32. In this case, the two-division clock CLK_2 is output from the output terminal of the first flip flop FF31.

When the reset pulse RST_P is enabled, the second clock divider 142 divides the two divided clock CLK_2 by two to generate a four divided clock CLK_4, and generates the four divided clock CLK_4. It outputs as the 2nd count signal CNT <2>. In addition, the second clock divider 142 is initialized when the reset pulse RST_P is disabled. The initialized second clock divider 142 initializes the second count signal CNT <2> to a low level irrespective of the divided clock CLK_2.

The second clock divider 142 includes a second flip flop FF32 and a third inverter IV33. The second flip-flop FF32 receives the divided clock CLK_2 at a clock input terminal and the reset pulse RST_P at a reset terminal. An output terminal Q of the second flip flop FF32 is connected to an input terminal of the third inverter IV33, and an input terminal of the second flip flop FF32 is connected to an output terminal of the third inverter IV33. In this case, the quarter clocked clock CLK_4 is output from the output terminal of the second flip flop FF32.

The control signal generator 150 controls the count codes CNT <1: 2> when the first and second count signals CNT <1> and CNT <2> are at predetermined levels. Enable the signal (ctrl). In this case, it is assumed that the predetermined level of the first count signal CNT <1> is a low level and the predetermined level of the second count signal CNT <2> is a high level.

The control signal generator 150 includes a second NOR gate NOR32 and a fourth inverter IV34. The fourth inverter IV34 receives the second count signal CNT <2>. The second NOR gate NOR32 receives the first count signal CNT <1> and the output signal of the fourth inverter IV34 and outputs the control signal ctrl.

An operation of the column select pulse generation circuit of the semiconductor memory device according to another exemplary embodiment of the present invention configured as described above will be described with reference to FIG. 9.

When the read pulse IRDP or the write pulse IWTP is enabled, the column select pulse YS is enabled.

When the column select pulse YS is enabled, a reset pulse RST_P is enabled, and after the reset pulse RST_P is enabled, the clock CLK is divided into two and four divisions so that the first and second count signals are divided. (CNT <1>, CNT <2>) are generated.

When the first count signal CNT <1> transitions to a low level and the second count signal CNT <2> is a high level, a control signal ctrl is enabled to a high level.

When the control signal ctrl is enabled at the high level, the column select pulse YS is disabled.

The column selection pulse YS is disabled and the reset pulse RST_P is disabled after a predetermined time (after the delay time of the delay element delay shown in FIG. 8).

When the reset pulse RST_P is disabled, the first and second count signals CNT <1> and CNT <2> are all initialized to a low level. In addition, when the reset pulse RST_P is disabled, the control signal ctrl is disabled.

The present invention generates the first and second count signals CNT <1> and CNT <2> by dividing the clock CLK by two and four divisions after the column selection pulse YS is enabled. Therefore, when the levels of the first and second count signals CNT <1> and CNT <2> both transition to a high level, 1 of the clock CLK after the column select pulse YS is enabled. When the period has passed and the first count signal CNT <1> transitions to a low level and the second count signal CNT <2> is a high level, the column select pulse YS is enabled. Thereafter, two cycles of the clock CLK have passed.

The column select pulse generation circuit of the semiconductor memory device according to another embodiment of the present invention sets the length of the enable period of the column select pulse to be equal to two periods of the clock. However, by adding or removing an inverter to the control signal generator 150 of FIG. 8, the length of the enable period of the column select pulse may be set to be equal to one period of the clock or may be set to be equal to three periods. In addition, the clock divider may be additionally configured to count up to eight cycles of the clock when the eight-division clock is used as the third count signal. Thus, the length of the enable period of the column selection pulse may be set to eight cycles of the clock.

The column select pulse generation circuit according to the present invention controls the length of the enable period of the column select pulse YS to the same length as a preset period of the clock. In addition, when the semiconductor memory device operates in synchronization with a low frequency clock, the semiconductor memory device generates a column selection pulse YS having a longer enable period than when operating in synchronization with a high frequency clock.

The semiconductor memory device to which the column select pulse generation circuit according to the present invention is applied can control the length of the enable section of the column select pulse according to the clock frequency, that is, the operating speed of the semiconductor memory device. There is an effect to increase.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a configuration diagram of a column select pulse generation circuit of a general semiconductor memory device;

2 is a block diagram of a column select pulse generation circuit of a semiconductor memory device according to an embodiment of the present invention;

3 is a detailed configuration diagram of the controller illustrated in FIG. 2;

4 is a timing diagram of a column select pulse generation circuit of the semiconductor memory device according to the embodiment of the present invention shown in FIG.

5 is a configuration diagram of a column select pulse generation circuit of a semiconductor memory device according to another embodiment of the present invention;

6 is a detailed configuration diagram according to an embodiment of the control unit shown in FIG. 5;

7 is a timing diagram of a column select pulse generation circuit when the control unit shown in FIG. 6 is applied to FIG. 5;

8 is a detailed configuration diagram according to another embodiment of the control unit shown in FIG. 5;

FIG. 9 is a timing diagram of a column select pulse generation circuit when the control unit shown in FIG. 8 is applied to FIG. 5.

<Description of the symbols for the main parts of the drawings>

10: column selection pulse generator 100, 100-1, 100-2: control unit

Claims (20)

A column select pulse generator configured to enable a column select pulse in response to a read pulse or a write pulse, and to disable the column select pulse in response to a control signal; And And a controller for dividing a clock when the column burst count signal is enabled and outputting the clock signal as the control signal. The method of claim 1, The column burst count signal is a signal which is enabled from a time point at which either the read pulse or the write pulse is enabled, and the length of the enable period is determined according to the burst length value set in the semiconductor memory device. Column selection pulse generation circuit of the memory device. The method of claim 2, The control unit And dividing the clock when the column burst count signal is enabled, and initializing when the column burst count signal is disabled. The method of claim 3, wherein The control unit And dividing the clock by two when the column burst count signal is enabled. The method of claim 1, The lead pulse And a write pulse is generated in synchronization with the clock when a read command is input to the semiconductor memory device. The write pulse is generated in synchronization with the clock when a write command is input. The method of claim 5, The column select pulse generator is The column select pulse generation circuit is enabled when one of the read pulse and the write pulse is enabled, and the column select pulse is disabled when the control signal is enabled. . A controller configured to determine an enable timing of a control signal in response to a read or write command, and determine an enable interval length of the control signal according to a frequency of a clock; And And a column select pulse generator configured to enable a column select pulse in response to the read or write command and to disable the column select pulse in response to the control signal. Circuit. The method of claim 7, wherein The control unit And dividing the clock when one of the read or write pulses is enabled. The method of claim 8, The control unit The clock is enabled during the enable period of the column burst count signal which is enabled from the time point at which either the read pulse or the write pulse is enabled, and the length of the enable period is determined according to the burst length value set in the semiconductor memory device. A column select pulse generation circuit of a semiconductor memory device, characterized in that it is divided and output as the control signal. The method of claim 9, The control unit And dividing the clock when the column burst count signal is enabled, and initializing when the column burst count signal is disabled. The method of claim 10, The control unit And dividing the clock by two when the column burst count signal is enabled. The method of claim 7, wherein The column select pulse generator is And enabling the column select pulse when one of the read pulse and the write pulse is enabled, and disabling the column select pulse when the control signal is enabled. A controller that enables the control signal at the rising timing of the clock after the column select pulse is enabled; And And a column select pulse generator configured to enable the column select pulse when one of the read pulse and the write pulse is enabled, and to disable the column select pulse when the control signal is enabled. Column select pulse generation circuit. The method of claim 13, The control unit And disabling the control signal after a predetermined time after the column select pulse is disabled. The method of claim 14, The control unit A pulse generator for generating a reset pulse having the same enable timing as the column select pulse and having a disable timing later than the column select pulse, and And a clock divider which divides the clock when the reset pulse is enabled and outputs the clock signal as the control signal, and initializes when the reset pulse is disabled. The method of claim 15, The clock division unit A flip-flop receiving the clock at a clock input terminal and receiving the reset pulse at a reset terminal; An inverter connected to an output terminal of the flip flop and an input terminal of the flip flop to an output terminal; And a signal output from an output terminal of the flip flop is output as the control signal. The column select pulse generation circuit of the semiconductor memory device, wherein the column select pulse is enabled when one of the read pulse and the write pulse is enabled, and the enable state of the column select pulse is maintained for a predetermined period of the clock. . The method of claim 17, The column select pulse generation circuit A column select pulse generator for enabling the column select pulse when one of the read pulse or the write pulse is enabled, and disabling the column select pulse when a control signal is enabled; And a control unit for counting the period of the clock in response to the column select pulse and enabling the control signal when a count code equals a predetermined code. The method of claim 18, The control unit And dividing the clock to generate the count code when the column select pulse is enabled, and wherein the column select pulse is disabled and initialized after a predetermined time. The method of claim 19, The count code includes a first count signal and a second count signal, The control unit A pulse generator configured to generate a reset pulse having an enable timing equal to the column select pulse and later than a disable timing of the column select pulse; When the reset pulse is enabled, the clock is divided into two to generate the first count signal, and the clock is divided into four to generate the second count signal. The count signal generator is initialized when the reset pulse is disabled. , And And a control signal generator for enabling the control signal when both the first count signal and the second count signal are at a predetermined level.

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