KR20100019602A - Frequency offset based lock detector and pll circuit including the same - Google Patents

Abstract

PURPOSE: A frequency offset based lock detector and a PLL(Phase Locked Loop) circuit thereof are provided to decrease a malfunction rate due to a process variation by simply forming the circuit with a simple algorithm. CONSTITUTION: A frequency estimator(200) supplies a first detection signal activated according to the frequency difference of a feedback signal and a reference signal. A phase detector(300) is operated in the active state of the first detection signal based on the reference signal, the feedback signal and the first detection signal. The phase detector supplies the second detection signal activated according to the phase difference of the feedback signal and the reference signal. A output unit(110) supplies a lock signal activated in the simultaneous active state of the second detection signal and the first detection signal.

Description

Frequency offset detection-based fixed state detector and a phase locked loop circuit including the same {Frequency offset based lock detector and PLL circuit including the same}

The present invention relates to a frequency synthesizer for generating a clock signal, and more particularly, to a fixed state detector and a phase locked loop circuit including the same.

In general, a fixed state detector is a circuit that determines whether a desired frequency is synthesized in a phase locked loop (PLL) or whether a clock is restored by a clock recovery circuit of a data processing circuit.

The fixed state detector is a circuit that detects whether or not the reference frequency and the voltage controlled oscillator frequency are locked. The detected lock signal is transmitted to a user or another system to control internal circuits or provide convenience for application circuits and system configuration.

In general, the structure of the fixed state detector is used to indicate the fixed state as a digital signal when the PLL synthesizes a desired frequency. The commonly used structure is a digital structure using a delay cell or an analog method of outputting a fixed state by monitoring a capacitor charge amount. In the digital structure using delay cells, it is very difficult to find the optimized delay value because the delay difference between the comparison frequencies for detecting the fixed state is affected by the loop characteristics of the PLL itself or the process change. In general analog methods, it is difficult to find optimized values of capacitor and current values.

Accordingly, an object of the present invention is to provide a frequency difference-based fixed state detector having a simple configuration and strong against the influence of process change.

An object of the present invention is to provide a phase locked loop circuit including the frequency difference based fixed state detector.

An object of the present invention is to provide a frequency fixing method that is easy to implement.

One object of the present invention is to provide a phase locking method that is easy to implement.

In order to achieve the above object of the present invention, the frequency difference detection-based fixed state detector according to an embodiment of the present invention is activated according to the frequency difference between the reference signal and the feedback signal based on the reference signal and the feedback signal. A frequency detector which provides a first detection signal, operates when the first detection signal is activated based on the reference signal, the feedback signal, and the first detection signal to activate according to a phase difference between the reference signal and the feedback signal And a phase detector for providing a second detection signal, and an output unit for providing a lock signal that is activated when the first detection signal and the second detection signal are simultaneously activated.

In example embodiments, the frequency detector receives the reference signal and the feedback signal and generates a first pulse signal having a frequency proportional to a frequency difference between the reference signal and the feedback signal, the frequency difference detector. A first logic unit configured to provide a logic signal activated when the first pulse signal is received by the first logic unit, and a frequency provided to the second pulse signal by lowering the frequency of the reference signal based on a division control signal; A first counter that is reset when a period and the logic signal are activated and provides the first detection signal that is activated when the second pulse signal is counted up to a first set value by a first count control signal. Can be.

The phase detector may include: a phase / frequency detector configured to output an up pulse signal and a down pulse signal according to a frequency and a phase difference between the reference signal, the feedback signal, and a rising edge of the up pulse signal; A narrow pulse generator (NPG) for generating a fourth pulse signal corresponding to a rising edge of the pulse signal and the down pulse signal, and performing a logical sum of the third pulse signal and the fourth pulse signal to generate a fifth pulse signal; A second logic unit providing a signal;

A second counter providing a counting completion signal that is activated when the fifth pulse signal is counted to a second set value by a second count control signal when the first sensing signal is activated, and the counting completion signal is activated. In this case, it may include a third counter that is reset and provides the second detection signal that is activated when the reference signal is counted to a third set value by a third count control signal.

In example embodiments, the third set value may be smaller than the second set value.

In example embodiments, the first counter may monitor a frequency difference between the reference signal and the feedback signal until the first set value by the first count control signal.

The frequency of the fifth pulse signal is the same as the frequency of the reference signal when the phases of the reference signal and the feedback signal coincide, and the phases of the reference signal and the feedback signal are inconsistent. The frequency of the fifth pulse signal may be higher than the frequency of the reference signal.

The counting operation of the third counter is completed before the counting operation of the second counter when the phases of the reference signal and the feedback signal coincide with each other, and the phases of the reference signal and the feedback signal do not coincide with each other. If not, the counting operation of the third counter may be completed later than the counting operation of the second counter.

In order to achieve the above object of the present invention, the frequency fixing method according to an embodiment of the present invention provides a first pulse signal proportional to the frequency difference between the reference signal and the feedback signal, the first pulse signal Providing a logic signal that is activated based on whether the signal is received, lowering the frequency of the reference signal as a second pulse signal based on the divided control signal based on the reference signal, and based on whether the logic signal is activated And providing a frequency fixed signal that is activated when counting the second pulse signal up to a set value.

In order to achieve the above object of the present invention, the phase lock method according to an embodiment of the present invention determines whether the frequency of the input signal and the feedback signal is identical, if the frequency is the reference signal Generating an up pulse signal and a down pulse signal according to a phase difference between the feedback signal, a first pulse signal corresponding to a rising edge of the up pulse signal, and a second pulse corresponding to a rising edge of the down pulse signal; Generating a signal, performing an OR operation on the first pulse signal and the second pulse signal to provide a third pulse signal, and counting a completion signal that is activated when counting the third pulse signal up to a first set value. Providing; And providing a phase lock signal that is activated when the counting completion signal is counted and the reference signal is counted to a second set value when the counting completion signal is in an inactive state.

According to an embodiment of the present invention, a phase locked loop circuit generates a first up pulse signal and a first down pulse signal based on a phase difference and a frequency difference between a reference signal and a feedback signal. A first phase / frequency detector, a charge pump for generating a varying voltage signal in response to the first up pulse signal and the first down pulse signal, a loop filter for filtering the voltage signal and generating an oscillation control signal, the oscillation A voltage controlled oscillator for generating an output signal of varying frequency based on a control signal, a divider for dividing the output signal as the feedback signal, and sequentially detecting a frequency difference and a phase difference between the reference signal and the feedback signal And a lock signal that is activated when both the phase and frequency of the reference signal and the feedback signal match. It includes a frequency difference detection based fixed state detector to provide.

Hereinafter, a method of manufacturing a semiconductor device in accordance with embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments, and has ordinary skill in the art. It will be apparent to those skilled in the art that the present invention may be embodied in various other forms without departing from the spirit of the invention.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof. Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

On the other hand, when an embodiment is otherwise implemented, a function or operation specified in a specific block may occur out of the order specified in the flowchart. For example, two consecutive blocks may actually be performed substantially simultaneously, and the blocks may be performed upside down depending on the function or operation involved. Like reference numerals in the drawings denote like elements.

1 is a block diagram illustrating a structure of a frequency detection based fixed state detector (hereinafter, a “fixed state detector”) according to an embodiment of the present invention.

Referring to FIG. 1, the fixed state detector 100 according to an embodiment of the present invention includes a frequency detector 200, a phase detector 300, and an output unit 110.

The frequency detector 200 receives the reference signal FREF and the feedback signal FVCO and provides a first detection signal FDO activated according to a frequency difference between the reference signal FREF and the feedback signal FVCO. The phase detector 300 operates when the first detection signal FDO is activated by receiving the reference signal FREF, the feedback signal FVCO, and the first detection signal FDO, and the reference signal FREF The phase difference of the feedback signal FVCO is detected to provide a second detection signal PDO that is activated according to the detected phase difference. The output unit 110 provides a lock signal that is activated when the first detection signal FDO and the second detection signal PDO are simultaneously activated. The output unit 110 may be configured as an AND gate.

2 is a block diagram illustrating a configuration of the frequency detector 200 of FIG. 1.

Referring to FIG. 2, the frequency detector 200 includes a wide digital logic quadricorrelator (WLDQ), a divider 220, a first logic unit 230, and a first counter 240.

The frequency difference detector 210 receives the reference signal FREF and the feedback signal FVCO, and receives the first pulse signal PS1 having a frequency proportional to the frequency difference between the reference signal FREF and the feedback signal FVCO. Create An up pulse signal is output from the first output terminal 211 of the frequency difference detector 210 and a down pulse signal is output from the second output terminal 212.

The first logic unit 230 provides a logic signal LG that is activated when an up pulse or a down signal output from the frequency difference detector 210 is received. The first logic unit 230 may be configured as an OR gate.

The divider 230 receives the reference signal FREF through the clock terminal 221 and lowers the frequency of the reference signal FREF based on the division control signal DCTL input to the control terminal 223 to output the terminal 225. ) As a second pulse signal PS2. When the division control signal DCTL is 1, the frequency of the second pulse signal is the same as the frequency of the reference signal FREF.

The first counter 240 receives a logic signal output from the first logic unit 230 through the reset terminal 241 and is reset when the logic signal is activated. Otherwise, the first counter 240 is input to the control terminal 245. The first detection signal FDO is activated when the second pulse signal PS2 is counted up to the first set value by the first count control signal CCTL1.

If there is no difference between the frequency of the reference signal FREF and the feedback signal FVCO, the first pulse signal PS1 is not output, and thus the logic signal LG output from the first logic unit 230 is inactivated and thus the first counter. Since 240 is not reset, the first detection signal FDO is activated.

3 is a block diagram illustrating a specific configuration of the phase detector 300 of FIG. 1.

Referring to FIG. 3, the phase detector 300 includes a phase / frequency detector 310, a narrow pulse generator 320, a second logic unit 330, a second counter 340, and a third A counter 350.

The phase frequency detector 310 has an up pulse signal UP and a frequency difference between the reference signal FREF and the feedback signal FVCO and the phase difference at the first output terminal 311 and the second output terminal 313, respectively. The down pulse signal DN is output.

The narrow pulse generator 320 has a third pulse signal PS3 and a down pulse signal DN corresponding to the rising edges of the up pulse signal UP at the first output terminal 321 and the second output terminal 323, respectively. Each of the fourth pulse signals PS4 corresponding to the rising edge of is generated and output.

The second logic unit 330 performs an OR operation on the third pulse signal PS3 and the fourth pulse signal PS4 to provide the fifth pulse signal PS5. When the frequency of the fifth pulse signal PS5 output from the second logic unit 330 is the same as that of the reference signal FREF and the feedback signal FVCO due to the operation of the narrow pulse generator 320 for a predetermined time period, When the frequency is the same as that of the reference signal REF and the phases are different from each other, the frequency is higher than the frequency of the reference signal FREF for a predetermined time.

The second counter 340 is reset when the first detection signal FDO is received by the reset terminal 341 and the first detection signal FDO is deactivated, and when the first detection signal FDO is activated. Activation when the fifth pulse signal PS5 is received by the clock terminal 343 and the fifth pulse signal PS5 is counted up to a second set value by the second counting control signal input to the control terminal 345. The counting completion signal CO is provided at the output terminal 347.

The third counter 350 is reset when the counting completion signal 351 is activated by receiving the reference signal FREF through the clock terminal 353 and the counting completion signal 351 through the reset terminal 351. The second sensing signal PDO output from the terminal 357 is inactivated. When the counting completion signal 351 is not activated, the third counter 350 operates to supply the reference signal FREF to the third set value by the third count control signal CCTL3 input to the control terminal 355. When counting and counting is completed, the output terminal 357 outputs the second detection signal PDO in an activated state. The third set value may be smaller than the second set value. If the second counter 340 is an N counter that counts to N, the third counter 350 may be an N-1 counter that counts to N-1.

5A to 5C illustrate the up signal UP and the down signal according to the phase and frequency difference between the reference signal FREF and the feedback signal FVCO in FIG. 3.

1, 2, 3 and 5a to 5c will be described in detail the operation of the fixed state detector according to an embodiment of the present invention.

First, the division control value DCTL of the divider 220 is set to 1, so that the second pulse signal PS2 is equal to the reference signal FREF.

The first counter 240 may count up to 200 by the first count control signal CCTL1.

The second counter 340 is set to count 100 according to the second count control signal CCTL2, and the third counter 350 is set to count 99 according to the third count control signal CCTL3.

First, as shown in FIGS. 5A and 5C, the case where the frequency and phase of the reference signal FREF and the feedback signal FREF do not coincide with each other will be described first.

When the frequency or phase of the reference signal FREF and the feedback signal FREF do not coincide with each other, the frequency detector 210 may use the first pulse signal PS1 corresponding to the frequency difference between the reference signal FREF and the feedback signal FREF. ) Is generated periodically. When the frequency of the reference signal FREF is lower than the frequency of the feedback signal FVCO as shown in FIG. 5A, the first pulse signal PS1 is periodically generated at the first output terminal 211, and as shown in FIG. 5C. If the frequency of the FREF is higher than the frequency of the feedback signal FVCO, the first pulse signal PS1 is periodically generated at the second output terminal 213. The generated first pulse signal PS1 is input to the reset terminal 241 of the first counter 240 through the first logic unit 230 to reset the first counter 240. Therefore, the first detection signal FDO in an inactive state is output from the first counter 240. Therefore, the lock signal LOCK output from the output unit 110 is deactivated.

At the same time, when the first detection signal FDO is provided to the phase detection unit 300, the phase detection unit 300 starts operation. Since the first detection signal FDO is in an inactive state, the second counter 340 is reset. The counting completion signal CO is deactivated and the deactivated counting completion signal CO is also resetting the third counter 350 to deactivate the second detection signal PDO output from the third counter 357.

When the phase and frequency of the reference signal FREF and the feedback signal FVCO coincide with each other as shown in FIG. 5B, no signal is output from the frequency detector 210. Since there is no signal output from the frequency detector 210, the first counter 240 is not reset, but counts the reference signal FREF up to 200 and provides the first detection signal FDO in an activated state. The activated first sensing signal FDO means that the frequency of the reference signal FREF and the feedback signal FVCO are the same.

When the first detection signal FDO is input to the phase detector 300, the phase detector 300 starts to operate, but the up signal UP and the down signal DN output from the phase / frequency detector 310 are the same. Since the frequencies of the third pulse signal PS3 and the fourth pulse signal PS4 provided by the narrow pulse generator 320 are also the same as those of the reference signal REF, the frequency of the fifth pulse signal PS5 is also the reference signal ( REF). Accordingly, the second counter 340 counts the fifth pulse signal PS5 having the same frequency as the reference signal FREF to 100 and the third counter 350 counts the reference signal FREF to 99. Therefore, the third counter 350 outputs the second detection signal PDO in an activated state before being reset by the counting completion signal CO. Accordingly, the lock signal LOCK output from the output unit 110 is also activated to indicate a fixed state.

The first counter 240 determines a time for monitoring the frequency difference between the reference signal FREF and the feedback signal FVCO.

4 is a block diagram illustrating a phase locked loop circuit according to an exemplary embodiment of the present invention.

Referring to FIG. 4, a phase locked loop circuit according to an embodiment of the present invention includes a first phase frequency detector 410, a charge pump 420, a loop filter 430, a voltage controlled oscillator 440, and a divider ( 450 and a frequency difference detection based fixed state detector 460.

The first phase frequency detector 410 generates the first up pulse signal and the first down pulse signal based on the phase difference and the frequency difference between the reference signal FREF and the feedback signal. The charge pump 420 generates a voltage signal that changes in response to the first up pulse signal and the first down pulse signal. The loop filter 430 filters the voltage signal and generates an oscillation control signal. The voltage controlled oscillator 440 generates an output signal FOUT whose frequency changes based on the oscillation control signal. The divider 450 divides the output signal FOUT to provide the feedback signal FVCO. The frequency difference detection-based fixed state detector 460 sequentially detects a frequency difference and a phase difference between the reference signal FREF and the feedback signal FVCO, and the phase and frequency of both the reference signal and the feedback signal may coincide. Provides a lock signal (LOCK) that is activated when The frequency difference detection based fixed state detector 100 of FIG. 1 including the frequency detector 200 of FIG. 2 and the phase detector 300 of FIG. 3 is the frequency difference detection based fixed state detector 460 of FIG. It can be employed as. Therefore, detailed description thereof will be omitted.

The frequency difference detection-based fixed state detector according to the embodiment of the present invention can variably set the monitoring time according to the lock time of the PLL, so that the lock time can be efficiently taken in any system and the sub-fixed state can be detected in real time. It is easy to implement with simple algorithm and low malfunction rate according to process change.

As described above, the present invention has been described with reference to a preferred embodiment of the present invention, but those skilled in the art may vary the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be understood that modifications and changes can be made.

1 is a block diagram illustrating a structure of a frequency detection based fixed state detector according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of the frequency detector of FIG. 1.

3 is a block diagram illustrating a specific configuration of a phase detector of FIG. 1.

4 is a block diagram illustrating a phase locked loop circuit according to an exemplary embodiment of the present invention.

5A to 5C illustrate an up pulse signal and a down pulse signal according to phase and frequency differences of a reference signal) and a feedback signal in FIG. 3.

Claims (13)

A frequency detector configured to provide a first detection signal activated based on a frequency difference between the reference signal and the feedback signal based on a reference signal and a feedback signal; A phase detection unit operating when the first detection signal is activated based on the reference signal, the feedback signal, and the first detection signal to provide a second detection signal activated according to a phase difference between the reference signal and the feedback signal ; And And an output for providing a lock signal that is activated when the first detection signal and the second detection signal are simultaneously activated. The method of claim 1, wherein the frequency detector, A frequency difference detector receiving the reference signal and the feedback signal and generating a first pulse signal having a frequency proportional to a frequency difference between the reference signal and the feedback signal; A first logic unit providing a logic signal that is activated when the first pulse signal is received by the frequency difference detector; A divider which receives the reference signal and lowers the frequency of the reference signal as a second pulse signal based on a division control signal; And And a first counter that is reset when the logic signal is activated and provides the first detection signal that is activated when counting the second pulse signal up to a first set value by a first count control signal. Frequency difference detection based fixed state detector. The method of claim 2, wherein the phase detection unit, A phase / frequency detector configured to output an up pulse signal and a down pulse signal according to a frequency and a phase difference between the reference signal and the feedback signal; A narrow pulse generator (NPG) for generating a third pulse signal corresponding to the rising edge of the up pulse signal and a fourth pulse signal corresponding to the rising edge of the down pulse signal; A second logic unit configured to perform a logic sum on the third pulse signal and the fourth pulse signal to provide a fifth pulse signal; A second counter providing a counting completion signal that is activated when the fifth sensed signal is counted to a second set value by a second count control signal when the first sensed signal is activated; And And a third counter that is reset when the counting completion signal is activated and provides the second detection signal that is activated when the reference signal is counted to a third set value by a third count control signal. Frequency difference detection based fixed state detector. 4. The fixed state detector of claim 3, wherein the third set value is smaller than the second set value. 4. The fixed state detector of claim 3, wherein the first counter monitors a frequency difference between the reference signal and the feedback signal up to the first set value by the first count control signal. 5. . The frequency of the fifth pulse signal is the same as the frequency of the reference signal, and the phase of the reference signal and the feedback signal are inconsistent. And the frequency of the fifth pulse signal is higher than the frequency of the reference signal. The method of claim 3, wherein the counting operation of the third counter is completed before the counting operation of the second counter when the phases of the reference signal and the feedback signal coincide with each other, and the phases of the reference signal and the feedback signal coincide. Otherwise, the counting operation of the third counter is completed later than the counting operation of the second counter. Providing a first pulse signal proportional to a frequency difference between the input signal and the feedback signal; Providing a logic signal that is activated based on whether the first pulse signal is received; Receiving the reference signal and lowering a frequency of the reference signal based on a division control signal to provide a second pulse signal; And And providing a frequency fixed signal that is activated when counting the second pulse signal to a set value based on whether the logic signal is activated. Determining whether the frequencies of the input signal and the feedback signal match; Generating an up pulse signal and a down pulse signal according to a phase difference between the reference signal and the feedback signal when the frequencies coincide; Generating a first pulse signal corresponding to the rising edge of the up pulse signal and a second pulse signal corresponding to the rising edge of the down pulse signal; Performing an OR operation on the first pulse signal and the second pulse signal to provide a third pulse signal; Providing a counting completion signal that is activated when counting the third pulse signal to a first set value; And And receiving a counting completion signal to provide a phase lock signal that is activated when the reference signal is counted to a second set value when the counting completion signal is in an inactive state. A first phase / frequency detector for generating a first up pulse signal and a first down pulse signal based on a phase difference and a frequency difference between the reference signal and the feedback signal; A charge pump generating a voltage signal that changes in response to the first up pulse signal and the first down pulse signal; A loop filter for filtering the voltage signal and generating an oscillation control signal; A voltage controlled oscillator for generating an output signal of varying frequency based on the oscillation control signal; A divider for dividing the output signal to provide the feedback signal; And A frequency difference detection based fixed state detector for sequentially detecting a frequency difference and a phase difference between the reference signal and the feedback signal and providing a lock signal that is activated when both the phase and frequency of the reference signal and the feedback signal coincide. Phase-locked loop circuit. 11. The method of claim 10 wherein the frequency difference detection based fixed state detector A frequency detector configured to provide a first detection signal activated based on a frequency difference between the reference signal and the feedback signal based on the reference signal and the feedback signal; A phase which operates when the first detection signal is activated based on the reference signal, the feedback signal, and the first detection signal to provide a second detection signal activated according to a phase difference between the reference signal and the feedback signal Detection unit; And And an output unit configured to provide a lock signal that is activated when the first detection signal and the second detection signal are simultaneously activated. The method of claim 11, wherein the frequency detector, A frequency difference detector receiving the reference signal and the feedback signal and generating a first pulse signal having a frequency proportional to a frequency difference between the reference signal and the feedback signal; A first logic unit providing a logic signal that is activated when the first pulse signal is received by the frequency difference detector; A divider which receives the reference signal and lowers the frequency of the reference signal as a second pulse signal based on a division control signal; And And a first counter that is reset when the logic signal is activated and provides the first detection signal that is activated when counting the second pulse signal up to a first set value by a first count control signal. Phase locked loop circuit. The method of claim 12, wherein the phase detection unit, A second phase / frequency detector configured to output a second up pulse signal and a second down pulse signal according to a frequency and a phase difference between the reference signal and the feedback signal; A narrow pulse generator (NPG) for generating a third pulse signal corresponding to the rising edge of the second up pulse signal and a fourth pulse signal corresponding to the rising edge of the second down pulse signal; A second logic unit configured to perform a logic sum on the third pulse signal and the fourth pulse signal to provide a fifth pulse signal; A second counter providing a counting completion signal that is activated when the fifth sensed signal is counted to a second set value by a second count control signal when the first sensed signal is activated; And And a third counter that is reset when the counting completion signal is activated and provides the second detection signal that is activated when the reference signal is counted to a third set value by a third count control signal. Phase locked loop circuit.

Images