KR20100018764A - Display device having partitions between pixel - Google Patents

Abstract

PURPOSE: A display device with partitions between pixels is provided to wire multiple signal lines to the partition, thereby freely wire the signal lines to lengthwise partition and breadthwise partition. CONSTITUTION: A pixel electrode and a switching element are arranged on an array substrate. The switching element supplies a data signal to the pixel electrode. Partitions(101,103) are formed on the array substrate or an opposite substrate for division of at least one sub pixel or unit pixel. Multiple signal lines are wired on the array substrate corresponding to the partition forming areas. The signal lines permits a gate signal and a data signal to the switching element.

Description

Display device having partitions between pixel

The present invention relates to a large screen display device for long-distance use, and more particularly, implements a large screen display with a display device such as LCD, OLED, AMOLED, which is inexpensive in manufacturing cost and proven in mass production, compared to a conventional LED display board. The present invention relates to a display device having an inter-pixel partition wall having a larger size and forming a partition wall in an area between the pixels to form a partition wall in which multiple signal lines are wired.

In general, liquid crystal displays (LCDs) and plasma discharge displays (PDPs) are mainly used as flat panel display devices, and recently, AMOLED (Active Matrix Organic Light Emitting Diode) has attracted attention as a next generation flat panel display device.

Among the above display devices, although display devices such as LCD and AMOLED are different kinds of display devices, three subpixels of R (Red), G (Green), and B (Blue) are commonly used as unit pixels. Or Dot) to display an image using a switching element arranged corresponding to each pixel.

In the case of LCD, liquid crystal is enclosed between an array substrate on which TFT (Thin Film Transistor) is arranged and an opposing substrate such as a color filter substrate, and the optical characteristics of light passing through the liquid crystal are changed and colorized according to the arrangement of the liquid crystal. Outputs the video. In the case of AMOLED, an array substrate on which TFTs are arranged and an opposing substrate for encapsulating an organic material are disposed, and holes injected from an anode and electrons injected from a cathode are recombined in the emission layer to excite excitons. When formed, the excitons return to a stable state, and the emitted energy changes into light and emits light. The difference between LCD and AMOLED is that LCD does not emit its own light, so a separate BLU (Back Light Unit) is required, but AMOLED does not need a separate BLU because it emits its own light. Is suitable for display.

1 is a partial exploded view showing a general configuration commonly applied to the conventional flat panel display device as described above.

As shown, the counter substrate 30 is bonded to the upper surface of the array substrate 10. FIG. 1 illustrates a display panel of an LCD, and the counter substrate 30 is a color filter substrate, and a color film forming R, G, and B subpixels 31 is printed on the counter substrate 30. In the figure, the boxed portion indicated by the hidden line represents a unit pixel 33 in which R, G, and B subpixels 31 are combined. If AMOLED, the above color film will not be formed on the opposing substrate.

The LCD and AMOLED are commonly formed with a pixel electrode 11 corresponding to the position of the subpixel on the array substrate 10, and the pixel electrode 11 is connected to the drain terminal of the TFT 13. The gate signal lines 15 are wired in the transverse direction of the array substrate 10, and the gate signal lines 15 are connected to the gate terminals of the respective TFTs 13 to apply a gate signal to the TFTs 13. A data signal line 17 is wired in the longitudinal direction of the array substrate 10, and the data signal line 17 is connected to the source terminal of each TFT 13 to apply a data signal to the TFT 13. A dummy pad 19 is printed on an edge portion of the array substrate 10, and the dummy pad 19 is used to apply a test signal to the gate signal line 15 and the data signal line 17 during the manufacturing process of the display panel. It is a pad. Reference numeral 21 denotes a charge accumulation capacitor 21.

In the case of the LCD, the counter substrate 30 is formed with a black matrix 35 (BM) as hatched in a diagonal line in an area other than the area where the subpixel 31 is formed. The BM 35 hides signal lines passing between the pixel electrodes 11 and prevents light leakage from each subpixel 31 to the outside. Usually, the BM 35 between the subpixels 31 is very narrow in width so that only one signal line having a width of approximately several tens of micrometers can be wired. Therefore, as shown, the gate signal line 15 is inevitably wired in the transverse direction, and the data signal line 17 is wired in the longitudinal direction, that is, the two signal lines 15 and 17 have a rule in which the wires cross each other. It became.

2 shows the display panel 40 in which the array substrate 10 and the counter substrate 30 are bonded to each other. Referring to this, it can be seen that a large number of components are mounted on the outside of the display panel 40, thereby greatly increasing the width of the image non-display area 50, which is hatched on the outside of the display panel 40. . Hereinafter, the cause of the image non-display area 50 of the LCD will be described. Of course, some of the examples below also apply to the case of AMOLED.

First, based on the above rule of signal line wiring, gate ICs 41 for applying a gate signal to the gate signal line 15 are mounted on one side edge portion of the display panel 40. Similarly, source ICs 43 for applying a source signal to the data signal line 17 are mounted on the lower edge portion of the display panel 40. In the illustrated example, the gate IC 41 and the source IC 43 are respectively mounted in the form of a chip on the film (COF), but may be mounted in the form of a chip on the glass (COG) on a glass substrate. In addition, an ASG (Amorphous Silicon Gate Circuit) may be mounted on the glass substrate outside the display panel 40 in place of the gate IC 41. Reference numeral 70 in the figure is a T_con block 70 for applying a drive signal to the drive ICs.

In general, display devices are gradually being designed with high resolution. For example, to realize a resolution of 640 × 480, 307200 unit pixels are required. This means that 307 200 x 3 subpixels are arranged. That is, in order to perform a fanout for wiring a myriad of signal lines in a drive IC such as the gate IC 41 and the source IC 43, an absolute space is required in the image non-display area 50. . As the resolution increases, the absolute space for the fan-out becomes wider, thereby increasing the image non-display area 50 outside the display panel 40.

Second, as shown in FIG. 2, the Vcom line 45 is formed along the outer line of the display panel 40. The Vcom line 45 is used to provide a reference voltage to the array substrate 10 and the counter substrate 30 side, and is used as a bias voltage of the charge storage capacitor 21 formed on the array substrate 10. It may also be used to apply the Vcom signal to the opposite substrate 30 side.

The Vcom line 45 forms a plurality of short points 47 along the edges and the outer lines of the display panel 40. The conducting portions 47 provide reference potentials to the array substrate 10 and the counter substrate 30. In this case, in order to suppress the flicker and the afterimage phenomenon in the large-screen display device, each of the energization units 47 may provide different reference potentials according to their positions. As shown in FIG. 2, a plurality of Vcom lines 45 are required to form a plurality of energizing parts 47 having potentials different from each other. Thus, an image non-display area (outside the display panel 40) is required. 50) acts as a cause to increase.

Thirdly, the array substrate 10 and the counter substrate 30 are each coated with a seal in the outer region, and are bonded to each other by the seal. The sealing structure is structurally stabilized by bonding the array substrate 10 and the counter substrate 30 to each other, and in the case of LCD, seals the liquid crystal injected therein, and in the case of AMOLED, seals the organic material injected therein. Do it. In the large-screen display device of about 40 inches or more, the array substrate 10 and the counter substrate 30 require a higher bonding strength. Therefore, the width of the seal line should be as wide as that. However, such a seal line should be concealed by BM, etc., and also acts as a cause of increasing the image non-display area 50 outside the display panel 40.

The mounting area of the drive IC, the space for fanout, the area for Vcom line mounting, and the area for application of the seal line need enough space so as not to interfere with each other. The area 50 will have a width of approximately several tens of millimeters. Thus, the bezel width outside the display device occupies a considerable area correspondingly.

The increase in the bezel width of the outer portion of a display device, such as LCD and AMOLED, is not a big problem. However, as shown in FIG. 3, when a plurality of large-screen display devices 80 of about 40 inches or more are combined to form a so-called " Tiled " type multi-screen 82, bezels 84 outside the respective display devices 80 Occupies a considerable width, and the image is disconnected and displayed, and the continuity of the screen is greatly degraded. For example, assuming that the distance between the unit pixels 33 is 0.5 mm and the width of the bezel 84 is 15 mm, the border portion of the display device 80 in FIG. 3 has a width of 30 mm. This means that up to 60 lines of information are lost at the border. Even if the information to be displayed on the 60 lines is shifted and displayed by the side display apparatus 80, the phenomenon of disconnection of the image will be inevitable.

Therefore, a phenomenon inevitably missing information occurs between the display apparatuses 80. For example, among the large display devices made of tiled multi-screen 82, the disconnection of the image in the advertisement display device installed on the roof of a building, the large display device installed in a racetrack or casino, the display market display, etc. You may be missing important information.

On the other hand, such a large display device is usually seen at a long distance (for example, a distance of 100m or more), it does not need to be implemented in high resolution. That is, even if the size of the unit pixel is relatively large, the display information acquired at a long distance is not significantly affected. As a result of large display devices that are seen at a long distance as described above, electronic displays using LEDs (Light Emitting Diodes) are often used. Although LED displays have a large resolution, the pixel size is large and the spacing between pixels is large. Therefore, when multiple modules are connected, no pixel drop occurs at the connection point. Therefore, the phenomenon of image interruption or degradation of screen continuity is rarely occurred at a long distance.

However, if individual LED packages are collected to produce medium-sized modules, and the medium-sized modules are connected to produce large modules, which are hundreds of inches in size, the manufacturing process takes a lot of time, compared to multi-screens composed of LCDs for the same area. There is a problem that takes more than three or four times the cost. In addition, the LED signboard easily causes eye fatigue, and the current driving method, the power consumption is considerable, the heat dissipation system is complicated, fine current control is difficult, there are a number of problems such as the gray scale is limited.

The present invention has been proposed to solve the above problems, the large screen display device for long-distance use is a new structure that solves the disadvantages of the conventional LED display board by focusing on the fact that there is no significant effect on the information acquisition even if the resolution is not high. Display device, but the size of the unit pixel is increased to reduce the total number of pixels, which greatly simplifies the components and greatly reduces the manufacturing cost, to ensure sufficient space between the unit pixels to form a partition and multiple By accommodating the signal lines and reducing the space for fan-out in the drive ICs outside the panel, the panel can be designed to slim the bezel width by reducing the image non-display area of the panel. Eliminates image interruption at the border of display devices It is an object of the present invention to provide a display device having an inter-pixel partition wall that improves continuity.

In addition, the present invention mounts the gate IC and the source IC together at one edge portion of the panel, and implements signal line wiring from each IC through the partition wall to design the bezel width of the three-side edge portion relatively slimmer. There is a purpose.

In addition, another object of the present invention is to allow the gate signal line and the data signal line to be wired through each other through the deformed metal layer, so that the space for fan-out of the drive IC can be minimized.

In addition, the present invention is another object to allow a narrower bezel design by wiring the Vcom line to the partition wall to reduce or eliminate the space for the Vcom line wiring outside the panel.

In addition, the present invention is another object of the Vcom line to be connected to the partition wall to be wired by using the metal layer of the data signal line and the metal layer of the gate signal line, so that it is not necessary to form an additional metal layer for the Vcom line wiring. have.

In the display device having the inter-pixel partition wall of the present invention for achieving the above object, the array substrate 110 and the opposing substrate 130 are bonded to each other to form a display panel 140, R, G, B sub In the display device in which the unit pixels 133 in which the pixels 131 are combined are arranged in a matrix form, the array substrate 110 includes a pixel electrode 111 corresponding to a region where the subpixel 131 is formed. A switching element 113 for switching and supplying a data signal to the pixel electrode 111; Partition walls 101 and 103 defining at least one or more subpixels 131 or unit pixels 133 are formed on the array substrate 110 or the opposing substrate 130, and the partition walls 110 are formed on the array substrate 110. The signal lines 115 and 117 for applying the gate signal and the data signal to the switching element 113 are wired in correspondence to the areas where the 101 and 103 are formed.

According to a preferred embodiment, the partitions (101, 103) is a vertical partition partitioning in the longitudinal direction and the horizontal partition wall (101) partitioning the sub-pixel 131 or unit pixel 133 in the horizontal direction ( 103).

In one embodiment, at least one gate signal line 115 for applying a gate signal to the switching device 113 is wired on the horizontal partition wall 101, and the switching device is connected to the vertical partition wall 103. At least one data signal line 117 for applying a source signal is wired to 113, and a gate IC 141 is mounted on at least one side edge portion of the array substrate 110, from the gate IC 141. The wiring to the gate signal line 115 is made via the partition wall 103 in the longitudinal direction.

In another embodiment, at least one gate signal line 115 for applying a gate signal to the switching device 113 is wired on the horizontal partition wall 101, and the switching device is connected to the vertical partition wall 103. At least one data signal line 117 for applying a source signal is wired to 113, and a source IC 143 is mounted on an upper or lower edge portion of the array substrate 110, and the source IC 143 is provided from the source IC 143. Wiring to the data signal line 117 is made via the partition 101 in the transverse direction.

In another embodiment, at least one gate signal line 115 for applying a gate signal to the switching element 113 is wired on the horizontal partition wall 101, and the switching is performed on the vertical partition wall 103. At least one data signal line 117 for applying a source signal to the device 113 is wired, and a gate IC 141 and a source IC 143 are mounted together at one edge of the array substrate 110. Wiring from the gate IC 141 to the gate signal line 115 is made via a partial partition 103 in the longitudinal direction.

In addition, wiring from the source IC 143 to the data signal line 117 is made via the partition 101 in the transverse direction.

In the present embodiment, the gate signal line 115 or the data signal line 117 are respectively routed through the release metal layer of each other, and are connected by the contact mask 118 at the point where the gate signal line 115 is bent by the release metal layer.

According to a more preferred embodiment, the Vcom line 145 is mounted along the partitions 101 and 103, and the Vcom line 145 is connected to the energization unit 135 formed along the outer line of the display panel 140. do.

In this embodiment, multiple Vcom lines 145 may be configured to deliver different Vcom voltages depending on the location of the energizer 135.

The Vcom line 145 is wired using a metal layer of the gate signal line 115 or a metal layer of the data signal line 117.

In addition, the Vcom line 145 is connected by a contact mask 118 at the point where the Vcom line 145 is inflected into a deformed metal layer.

According to the display device having an inter-pixel partition of the present invention, a partition is formed so as to partition one or more subpixels or unit pixels, and a plurality of signal lines are wired to the partition, thereby freely inflecting the signal line into a horizontal partition and a longitudinal partition. As a result, the space for the fanout from the drive IC of the panel edge can be greatly reduced, and thus the bezel width of the display device can be designed to be slimmer. The additional occupied area can be designed to be the same as or similar to the actual inter-pixel partition wall, thereby eliminating image disconnection at the border portion and improving screen continuity. Furthermore, it is possible to use display devices such as LCD and AMOLED, which have proven many advantages such as mass production, in place of the LED display boards, which have been mainly used as outdoor displays for remote long-distance roads. There is no need to build a complicated heat dissipation system, so the product can be aimed at simplification. Fine voltage driving control enables free gray scale expression and stable image quality. Furthermore, although the resolution is reduced by increasing the size of the unit pixel, this does not pose a significant problem in the long-distance display device, but rather prevents unnecessary pixel waste and reduces the components of the drive IC and the driving device. It can be designed, and the manufacturing cost can be drastically reduced.

In addition, according to the present invention, by accommodating heterogeneous drive ICs together at the edge portion of one side of the panel together, and freely wiring the wirings from the drive ICs into the space of the partition wall and transferring them to the respective switching elements, the three side edge portions of the panel are relatively There is an effect that can be designed more slim.

Further, according to the present invention, the gate signal line and the data signal line are freely wired in the vertical and horizontal directions, respectively, and each signal line is wired by using a release metal layer, and a contact mask is formed at a point where the release metal layer is bent. Thus, even in the case of multiple wiring of signal lines, there is an effect that it is not necessary to construct an additional metal layer.

In addition, according to the present invention, by mounting the Vcom line in the area where the partition wall is formed, it is possible to minimize or eliminate the area where the Vcom line is mounted on the outside of the panel, and ultimately design a slimmer bezel width of the outside of the panel. It has an effect.

In addition, according to the present invention, even in the case of designing multiple Vcom lines transmitting different Vcom voltages in order to eliminate flicker and afterimage in the large-screen display device, multiple Vcoms are formed by using the horizontal bulkhead and the vertical bulkhead. As the lines can be distributed and mounted, the bezel width of the outside of the panel does not increase as the Vcom line increases.

In addition, according to the present invention, when mounting a Vcom line using a partition wall, the metal layer of the gate signal line and the data signal line can be wired without forming a separate metal layer, and even if the metal layer is bent by a deformed metal layer. There is an effect that wiring can be made by forming a connection point using a contact mask.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

First, the present invention is to provide a large-screen display device for the purpose of being viewed from a long distance, the display device of the present invention provides a large-screen display as a single display device or combine a plurality of display devices to form a multi-screen screen Can be used in the case. More specifically, the display apparatus of the present invention is applicable to all display apparatuses in which three subpixels of R, G, and B form one unit pixel (or dot), and basically, the array substrate and the opposing substrate mutually It is bonded to form a display panel. In this case, a switching element such as a TFT is disposed on the array substrate corresponding to the subpixels, and the counter substrate is configured to enclose a liquid crystal or an organic material between the array substrate and the array substrate. For example, the display device of the present invention includes LCD, OLED, AMOLED. In the following description, an embodiment of a display panel in which an array substrate and an opposing substrate are bonded to an LCD, for example, will be described.

On the other hand, although not mentioned in the following embodiments, in the case of LCD, the liquid crystal is encapsulated between the array substrate and the opposing substrate, the BLU is mounted on the rear of the display panel, and in the case of AMOLED, the organic material is encapsulated inside and a separate BLU The need for such a configuration is extremely obvious in the art.

4 and 5 are partial exploded views showing the configuration of a display device according to the present invention. Referring to this, in the display device of the present invention, the array substrate 110 and the counter substrate 130 are bonded to each other to form the display panel 140. The present embodiment relates to an LCD. In the LCD, a color filter is printed or coated on the counter substrate 130 to form a unit pixel 133 in which R, G, and B subpixels 131 are combined. In contrast, AMOLED is used only for the purpose that the opposing substrate only encapsulates the organic material and protects the array substrate. "Pixel" may be referred to in other words as "pixel", and "unit pixel" may be referred to as "dot." 4 and 5, the BM 135 is printed in an area other than the area where the subpixel 131 is formed, thereby concealing signal lines and the like.

The pixel electrode 111 is formed on the array substrate 110 at a position corresponding to the position of the subpixel 131. The pixel electrode 111 is controlled by the source voltage supplied through the switching element 113. In the present invention, the switching element 113 includes all the switching elements of the gate driving method, and is preferably a TFT. Hereinafter, the TFT 113 will be referred to for convenience.

As shown, the pixel electrode 111 is connected to the drain terminal of the TFT 113. A gate signal line 115 that is wired in the lateral direction is connected to the gate terminal of the TFT 113, and a data signal line 117 that is wired in the longitudinal direction is connected to the source terminal. Therefore, the TFT 113 is triggered by the gate IC 141 described later, and receives the source signal from the source IC 143. As shown in FIGS. 4 and 5, the dummy pad 119 may be printed on the left edge portion and the upper edge portion of the array substrate 110. The dummy pad 119 is a pad for applying a test signal to the gate signal line 115 and the data signal line 117 during the manufacturing process of the display panel. In addition, reference numeral 121 which is not described is a charge accumulation capacitor 121.

Here, barrier ribs 101 and 103 are formed around each unit pixel 133 to partition each unit pixel 133. The partitions 101 and 103 mean an area that partitions around the unit pixels 133, and do not necessarily mean that a physical barrier is erected. In the present invention, the partitions 101 and 103 have a sufficient space so that at least two or more signal lines 115 and 117 can be wired. More preferably, the partitions 101 and 103 may be coated with a thread. In this case, the partitions 101 and 103 may partition the unit pixels 133 as physical barriers.

As shown, the partitions 101 and 103 are constituted by a horizontal partition 101 partitioning the unit pixels 133 in the horizontal direction and a vertical partition 103 partitioning in the longitudinal direction. In the illustrated example, the partition walls 101 and 103 are formed to partition each unit pixel 133, but the partition walls 101 and 103 may be formed to partition two or more unit pixels 133, and It may be formed to partition the subpixel 131.

As shown in the drawing, the BM 135 between the subpixels 131 is usually narrow enough to allow one signal line 115 or 117 to pass therethrough, and thus is an area in which yarn cannot be applied. Although the drawings are exaggerated for clarity, the width of the BM 135 between the subpixels 131 is about 100 μm, and the widths of the signal lines 115 and 117 are about a few tens of μm. However, since the width of the narrowest seal line is about 1 mm in the state of the art, it is not possible to apply the seal line to the narrow width BM 135 as in the prior art.

However, the display device of the present invention is provided for long-distance use, and has a relatively large unit pixel 133 although the resolution is reduced. For example, each unit pixel 133 has a width of approximately several mm. Accordingly, the partitions 101 and 103 may be formed by securing a space of several mm between the unit pixels 133. For example, the unit pixel 133 has a width of 4 mm, and partition walls 101 and 103 of 2 mm are formed between the unit pixels 133. That is, the unit pixels 133 are arranged at a pitch of 6 mm. Such a wide width of the barrier ribs 101 and 103 can be formed in a kind of space where the space of the barrier ribs 101 and 103 in which an image is not displayed by the light emitted from the unit pixel 133 at a distance is not recognized. This is due to optical illusions.

In the embodiment shown in FIG. 4, the partitions 101 and 103 partition the unit pixel 133 to be completely sealed. As mentioned above, since the partitions 101 and 103 may not be physical barriers, even when the partitions 101 and 103 are formed to partition the unit pixel 133, the liquid crystals enclosed therein may be freely moved.

However, when seal lines are applied to the partition walls 101 and 103, the partition walls 101 and 103 may seal the periphery of the unit pixel 133. Therefore, when the seal lines are applied to the partitions 101 and 103, as in the embodiment shown in FIG. 5, the horizontal partitions 101 and the vertical partitions 103 are formed to be cut off, respectively. To be spaced apart a predetermined interval. As a result, the enclosed liquid crystal or the like may communicate more freely.

FIG. 6 is a plan view illustrating an embodiment of a display panel in the present invention, and FIG. 7 is a partially extracted plan view illustrating a fanout according to FIG. 6. An example of the multiple signal line wiring of the present invention will be described with reference to this.

As shown in FIG. 6, the array substrate 110 and the opposing substrate 130 are bonded to form a display panel 140. Gate ICs 141 for applying a gate signal to the gate signal line 115 are mounted on the right edge portion of the display panel 140. Similarly, source ICs 143 for applying a source signal to the data signal line 117 are mounted on the lower edge portion of the display panel 140. The gate IC 141 and the source IC 143 may be bonded and mounted in the form of a chip on the film (COF) as in the illustrated example, or may be mounted in the form of a chip on the glass (COG) on a glass substrate. In this case, the gate IC 141 in the present invention may be replaced with an ASG as a drive IC for applying a gate signal to the TFT 113. At least the gate IC 141 mentioned in the present invention is understood to be equivalent to ASG. Reference numeral 170 in the figure denotes a T_con block 170 for applying a drive signal to the drive ICs.

An image non-display area 150 is formed along the outer line of the display panel 140. The image non-display area 150 is an area where the seal line is applied and is an area where no image is displayed. At this time, as shown in the drawing, the fan-out in the image non-display area 150 is required to wire the signal lines 115 and 117 in the drive ICs such as the gate IC 41 and the source IC 43. For the fan out, the image non-display area 150 needs a space having an absolute width d4.

The embodiment of FIG. 7 presents a method for minimizing the absolute space for fanout to a minimum.

As shown in FIGS. 4 and 5, at least one gate signal line 115 and data signal line 117 should be wired around each TFT 113. In this case, since the partition walls 101 and 103 of the relatively wide space are formed around the unit pixel 133, the multiple signal lines 115 and 117 may be wired thereto.

As in the illustrated embodiment, the fanouts at the gate IC 141 and the source IC 143 are wired through the partitions 101 and 103 rather than the image non-display area 150. Accordingly, the image non-display area 150 may be designed to be more slim, and the bezel width of the display device may also be very slim.

In FIG. 7, the basic horizontal signal line 115 and the vertical data signal line 117 are not shown, but at least one signal line 115 or 117 is vertically and horizontally circumscribed around each subpixel 131. The signal lines 115 and 117 may be multiplexed at the point where a fan IC of the drive IC is made through the partitions 101 and 103. In this case, since the width of the partition walls 101 and 103 is sufficiently wider than the width of the signal lines 115 and 117, the multiple signal lines 115 and 117 may be wired without interfering with each other.

Referring to FIG. 7, the wiring from the source IC 143 to the data signal line 117 is made partially through the partition 101 in the lateral direction. Although not shown, wiring from the gate IC 141 to the gate signal line 115 is also made via the partition 103 in the longitudinal direction. That is, according to the present invention, the wirings from the respective drive ICs 141 and 143 may be freely passed through the partition 101 in the lateral direction and the partition 103 in the longitudinal direction.

At this time, the fan out from the drive ICs 141 and 143 may be performed through a new metal layer different from the metal layer of the gate signal line 115 and the metal layer of the data signal line 117. However, preferably, the wirings from the drive ICs 141 and 143 are wired using existing metal layers.

Usually, the metal layer of the gate signal line 115 and the metal layer of the data signal line 117 are heterogeneous layers insulated by an insulator. At this time, when the wirings in the drive ICs 141 and 143 pass through the heterogeneous metal layer, the inflection point is connected to the contact mask 118 as shown in the inflection point by the heterometal layer.

For example, look at the second wiring of the source IC 143 in FIG. As shown, the wiring of the source IC 143 first passes one pitch of the longitudinal partition walls 103. At this time, the wiring of the source IC 143 is spaced apart from the data signal line 117 already wired corresponding to the sub-pixel 131 of the right vertical line. The wiring of the source IC 143 is bent and wired into the horizontal partition wall 101 on the left side at the point where the longitudinal partition wall 103 ends. Then, the plurality of lines are branched again in the longitudinal direction from the transverse partition wall 101 to be connected to the data signal lines 117 in the longitudinal direction. At this time, at the point where the wiring of the source IC 143 is bent from the partition 103 in the longitudinal direction to the partition 101 in the transverse direction, the wiring should be converted to a metal lamination of the heteromorphism. Therefore, as shown in FIG. 7, the contact mask 118 is formed at the inflection point to interconnect the release metal layers, thereby making it possible to connect the partitions 101 and 103.

Although not illustrated in the drawings, the fanout at the gate IC 141 may be similarly performed in a space in which the partitions 101 and 103 are formed. In addition, the exemplary embodiments shown in FIG. 7 are only one exemplary embodiment, and the wirings in the respective drive ICs 141 and 143 may be freely bent vertically and horizontally.

FIG. 8 is a front view illustrating an example of a multi-screen configuration according to the present invention. The display device 180 of the present invention is combined to form a tiled multi-screen 182. FIG. 8 illustrates that each display device 180 has a 3 × 3 unit pixel 133 to improve understanding of the present invention. Of course, the actual display device will be designed with a higher resolution than this.

As shown, the partitions 101 and 103 formed between the unit pixels 133 have a width d1. In this case, the barrier 180 has a space large enough to accommodate the multiple signal lines 115 and 117. For example, the partition wall 180 has a width of approximately 2 mm. This means that the interval between the unit pixels 133 is 2 mm. In this case, as described above, the display device of the present invention requires little space for fan-out in the image non-display area 150 outside the panel. Therefore, the image non-display area 150 may be designed to have a minimum width (about 1 mm) at the outer portion of the display device 180. This means that the width of the bezel 184 on the outside of the display device 180 may be designed to a little more than about 1 mm. As mentioned above, if the width d1 of the barrier ribs 101 and 103 is 2 mm, the border width d2 between the display devices 180 may also be narrowed to about 2 mm.

That is, when the multi-screen 182 is configured by using the display device 180 of the present invention, the distance d1 between the unit pixels 133 and the width of the border portion d2 of the display devices 180 approximately match. You can. Accordingly, no pixels are lost at the borders of the display apparatuses 180. Therefore, it is possible to eliminate the image disconnection phenomenon at the border portion of the display device 180 and to improve the screen continuity.

FIG. 9 is a plan view illustrating another embodiment of a display panel in the present invention, and FIG. 10 is a front view illustrating an example of a multi-screen configuration according to the embodiment of FIG. 9. Referring to this, a more advanced embodiment of the present invention will be described.

In the display device of the present invention, as described above, multiple signal lines 115 and 117 may be wired on the partition walls 101 and 103. In addition, fan-out of the drive ICs 141 and 143 may be performed through the partitions 101 and 103. As a result, a wide space (a considerably wider space than the width of the drive IC) is not required in the image display area 150 to fan out the drive ICs 141 and 143. Further, the signal lines 115 and 117 can be freely wired to the TFT 113 at a distance regardless of the positions of the drive ICs 141 and 143.

Accordingly, as illustrated in FIG. 9, the gate IC 141 and the source IC 143 may be driven by being mounted at one side edge of the panel. Although not shown in FIG. 9, the signal lines 115 and 117 can be wired to the TFT 113 in the entire region of the panel in the same manner as the wiring example shown in FIG. 7 in the gate IC 141 and the source IC 143. have. As such, when the heterogeneous drive ICs 141 and 143 are mounted together with one side edge portion of the panel, the remaining three side edge portions of the display apparatus have a slimmer bezel width.

In this way, if the three-sided edge portion of the display device is designed to be slim, the width of the border portion may be further reduced when the tiled multi-screen is configured. As shown in FIG. 10, when the display apparatus 180 is arranged in 3 × 2, two display apparatuses 180 disposed at the center thereof are in contact with the other display apparatus 180. If the central display apparatuses 180 are manufactured as shown in the embodiment shown in FIG. 9, the borders between the display apparatuses 180 may be further narrowed, and screen continuity may be improved.

11 is a plan view showing a wiring example of the Vcom line in the present invention, showing another embodiment of the present invention.

Referring to FIG. 11, Vcom lines 145 may be mounted on the partitions 101 and 103. The Vcom line 145 is used to provide a reference voltage to the array substrate 110 and the counter substrate 130 as is commonly known, and is used as a bias voltage of the charge storage capacitor 121 formed on the array substrate 110. do. It may also be used to apply the Vcom signal to the opposing substrate 130 side.

As shown in FIG. 11, the Vcom line 145 is wired by freely bending between the horizontal partition wall 101 and the vertical partition wall 103. In this case, the Vcom line 145 is spaced apart from the signal lines 115 and 117 in order to prevent short circuits with the signal lines 115 and 117 wired through the partition walls 101 and 103. The Vcom line 145 wired through the partition walls 101 and 103 is connected to the energizing portion 147 of the panel outer portion as shown in FIG. 9. In this energizing portion 147, a reference potential is provided to the array substrate 110 or the counter substrate 130 side.

More preferably, in order to suppress the flicker and the afterimage phenomenon, as in a conventional large screen display device, each of the energizing parts 147 may provide different reference potentials depending on the position. To this end, the Vcom lines 145 connected to the respective energization units 147 transmit the reference voltages differentiated according to the position of the energization unit 147 to the energization unit 147. Since the display device of the present invention can wire the plurality of Vcom lines 145 through the partitions 101 and 103, even if the differential is mounted with a plurality of Vcom lines 145 to provide a reference potential, the outside of the panel The image non-display area 150 does not increase.

The Vcom line 145 wired through the partition walls 101 and 103 may also be wired using a new metal layer different from the existing metal layer. However, when a new metal layer is used as described above, an insulation layer and the like must be added, and thus an increase in thickness of the panel and a delay in the manufacturing process are expected. Therefore, more preferably, the existing metal layer is also used for the wiring of the Vcom line 145.

The Vcom line 145 is wired using the metal layer for the existing signal lines 115 and 117, as described above, in which fanouts of the drive ICs 141 and 143 are wired using the heterogeneous metal layer. Similar to When the Vcom line 145 is connected to the metal layers of the signal lines 115 and 117 via the partitions 101 and 103, the Vcom line 145 may be spaced apart from the signal lines 115 and 117 that are previously wired. Short does not occur. At the point where the Vcom line 145 is bent from the transverse bulkhead 101 to the longitudinal bulkhead 103 or vice versa, the release metal layer is formed using the contact mask 118 as described above. By connecting, free wiring inflection is possible through a release metal layer.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the technical field of the present invention without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

1 is a partial exploded view showing a general configuration of a conventional display device

2 is a plan view illustrating a state in which a conventional array substrate and an opposite substrate are bonded to each other;

3 is a front view showing a conventional multi-screen configuration example

Figure 4 is an exploded view showing a part of the configuration of the display device according to the present invention

5 is a partial exploded view showing another embodiment of the present invention

Figure 6 is a plan view illustrating an embodiment of a display panel in the present invention

FIG. 7 is a fragmentary top view illustrating the fanout according to FIG. 6. FIG.

8 is a front view showing an example of a multi-screen configuration according to the present invention

9 is a plan view illustrating another embodiment of a display panel in the present invention;

10 is a front view showing an example of the multi-screen configuration according to the embodiment of FIG.

11 is a plan view showing a wiring example of the Vcom line in the present invention;

<Explanation of symbols for the main parts of the drawings>

101: partition 103: partition

110: array substrate 111: pixel electrode

113: switching element, TFT 115: gate signal line

117: data signal line 118: contact mask

119: dummy pad 121: capacitor

130: opposing substrate 131: subpixel

133: unit pixel 135: BM

140: display panel 141: gate IC

143: Source IC 145: Vcom Line

147: power supply unit 150: video non-display area

170: T_con block 180: display device

182: Multiscreen 184: Bezel

Claims (11)

A display device in which an array substrate 110 and an opposing substrate 130 are bonded to each other to form a display panel 140, and unit pixels 133 in which R, G, and B subpixels 131 are combined are arranged in a matrix form. To A pixel electrode 111 and a switching element 113 for switching and supplying a data signal to the pixel electrode 111 are disposed in the array substrate 110 to correspond to a region where the subpixel 131 is formed; Partition walls 101 and 103 defining at least one or more subpixels 131 or unit pixels 133 are formed on the array substrate 110 or the opposing substrate 130, and the partition walls 110 are formed on the array substrate 110. And a plurality of signal lines (115, 117) for applying a gate signal and a data signal to the switching element (113) corresponding to a region where the portions (101, 103) are formed. The method of claim 1, The partitions 101 and 103 may include a horizontal partition 101 partitioning the subpixels 131 or unit pixels 133 in a horizontal direction and a vertical partition 103 partitioning in a longitudinal direction. A display device having an inter-pixel partition wall. 3. The method of claim 2, At least one gate signal line 115 for applying a gate signal to the switching element 113 is wired to the transverse partition wall 101, and a source of the switching element 113 is sourced to the longitudinal partition wall 103. At least one data signal line 117 for applying a signal is wired, A gate IC 141 is mounted on at least one edge portion of the array substrate 110, and wiring from the gate IC 141 to the gate signal line 115 partially passes through a longitudinal partition 103. Display device having an inter-pixel partition wall, characterized in that made. 3. The method of claim 2, At least one gate signal line 115 for applying a gate signal to the switching element 113 is wired to the transverse partition wall 101, and a source of the switching element 113 is sourced to the longitudinal partition wall 103. At least one data signal line 117 for applying a signal is wired, The source IC 143 is mounted on the upper or lower edge portion of the array substrate 110, and the wiring from the source IC 143 to the data signal line 117 partially passes through the horizontal partition wall 101. Display device having a partition between the pixels, characterized in that made by. 3. The method of claim 2, At least one gate signal line 115 for applying a gate signal to the switching element 113 is wired to the transverse partition wall 101, and a source of the switching element 113 is sourced to the longitudinal partition wall 103. At least one data signal line 117 for applying a signal is wired, The gate IC 141 and the source IC 143 are mounted together at one edge of the array substrate 110, and the wiring from the gate IC 141 to the gate signal line 115 is vertically partitioned 103. Display panel having an inter-pixel partition wall, characterized in that it is partially via). The method of claim 5, And the wiring from the source IC (143) to the data signal line (117) is partially via the partition wall (101) in the transverse direction. The method according to any one of claims 3 to 6, The gate signal line 115 or the data signal line 117 is wired through each of the heterogeneous metal layers, and connected to each other by the contact mask 118 at a point where the gate signal line 115 is inverted by the hetero metal layer. Display device having a. The method of claim 1, The Vcom line 145 is mounted along the partitions 101 and 103, and the Vcom line 145 is connected to an energization unit 135 formed along an outer line of the display panel 140. Display device having a partition. The method of claim 8, A display device having an inter-pixel partition wall, wherein the plurality of Vcom lines 145 transmit different Vcom voltages according to positions of the energization unit 135. The method according to claim 8 or 9, And the Vcom line (145) is wired using a metal layer of a gate signal line (115) or a metal layer of a data signal line (117). The method of claim 10, And the Vcom line (145) is connected by a contact mask (118) at the point where the metal layer of the heteromorphism is inflected.

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