KR20100015040A - Semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A semiconductor memory device and a manufacturing method thereof are provided to implement a simple processes by generating a contact plug and a signal lien through one process. CONSTITUTION: A plurality of active areas are formed on a semiconductor substrate. A plurality of word lines are parallel with a plurality of active areas. The contact line(105) is formed at between least two among a plurality of word lines. The contact plug(104) is formed between a plurality of word lines. The contact plug is electrically connected to one among a plurality of active areas. The contact plug is electrically connected to a variable resistor element.

Description

Semiconductor memory device and manufacturing method therefor {SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF}

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a semiconductor memory device using a variable resistance device and a method of manufacturing the same.

In general, semiconductor memory devices include many memory cells that are circuitry connected. Representative semiconductor memory devices include DRAM (DRAM). A unit memory cell of a DRAM is generally composed of one switch and one capacitor, and has the advantage of high integration and fast operation speed, while realizing "0" and "1" based on the change of charge amount. After the power is turned off, data storage is difficult due to volatile memory devices in which all stored data is lost. In order to solve this problem, a new memory technology capable of implementing a binary state corresponding to “0” and “1” in DRAM by using a new variable rather than a charge amount is being researched.

Non-volatile memory devices that are currently being researched include magnetic random access memory (MRAM) using magnetic-resistance effects, and ferroelectric random access (FRAM) using polarization characteristics of ferroelectric materials. Memory) and Phase-Change Random Access Memory (PRAM) using phase change materials. In addition, research on resistive switching random access memory (ReRAM) devices using the characteristic that the physical property changes as a phase indicating the state of metal or semiconductor characteristics when it exists as an insulator in the intrinsic state and an external voltage is applied. And development is proceeding at a rapid pace. A memory device based on such a variable resistance device needs to flow a current in order to write and read information. In order to construct a highly integrated memory, it is necessary to minimize the influence of external resistance such as the resistance of signal lines that transmit and receive signals. .

Meanwhile, in order to improve the degree of integration of semiconductor devices, in the case of D-RAM devices including transistors and capacitors, a Self Align Contact (SAC) process is used to electrically connect an impurity region of a semiconductor substrate with a bit line and a storage node. Landing plug contact (LPC) is formed using. 1 to 5 show a manufacturing process of a conventional semiconductor memory device using the LPC process. 1 to 5, (a) is a plan view of the semiconductor device as seen from above, (b) is a cross sectional view of the portion A-A ', and (c) is a cross sectional view of the portion B-B'.

Referring to FIG. 1, a device isolation layer 10a is formed on a semiconductor substrate S on which a memory cell array is to be formed to distinguish a plurality of active regions 10. Thereafter, as shown in FIG. 2, a plurality of word lines 11 are formed on the semiconductor substrate in which the active region 10 is defined. The word line 11 is formed across the active regions 10, and is sequentially formed on the semiconductor substrate by a gate oxide film 11a, a polysilicon, or the like, and a gate conductive film 11b in a subsequent etching process. Has a structure in which a hard mask film 11c is protected. Furthermore, insulating spacers 11d are formed to protect sidewalls of the word line patterns of these stacked structures. Then, an impurity of an appropriate concentration is implanted into the active region 10 exposed on both sides of these word lines 11 to form a source or drain diffusion region 11e.

Next, FIGS. 3 and 4 illustrate a process of forming a landing plug using a self alignment contact (SAC) technique. That is, after the insulating film is formed over the entire semiconductor substrate on which the word line 11 is formed, the planarization process is performed using, for example, chemical mechanical polishing (CMP), and the like, as shown in FIG. 3. The spaces between the two layers are filled with the insulating film 13. Then, a part of the exposed insulating film 13 is selectively removed using a landing plug contact mask perpendicular to the word line 11.

In this case, the landing plug contact mask alternately exposes a portion of the word line 11 and a portion of the insulating layer 13, and the upper portion of the word line 11 is protected by the hard mask layer 11c, so that the insulating plug contact layer is formed during the etching process. Only part of (13) can be selectively removed. When a portion of the insulating layer 13 is selectively removed in this way, a contact hole through which a portion of the active region 10 is exposed is formed. The landing plug 14 is formed as shown in FIG. 4 by filling the contact hole with a conductive material.

Thereafter, as shown in FIG. 5, after the interlayer insulating film 15b is formed on the structure thus formed, the source line 15 electrically connected to the series of landing plugs 14 by the contact plug 15a is formed. To form.

The above-described self-aligned contact process is used in the fabrication of DRAM devices, and signal lines for transmitting and receiving external signals are formed through a plurality of plugs in order of the source line 15, the contact plug 15a, and the landing plug 14. However, in the case where the electrical passage is formed through several plugs as described above, the contact area due to the scale-down of the memory device is reduced, the resistance of the plug itself is increased due to the low electrical conductivity of polysilicon, and the plug and source lines and There is a limit in reducing the resistance of the entire signal line due to the interface resistance generated at the contact portion of the. In particular, the conventional self-aligned contact process is difficult to apply to the memory device based on the variable resistance element, which is essential to reduce the size of the external resistance generated by sending and receiving an external signal, so that the high integration of the memory element based on the variable resistance element The development of new manufacturing processes is required.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor memory device and a method for manufacturing the same, which can reduce the electrical resistance of a signal line that transmits and receives an external signal.

Furthermore, another object of the present invention is to provide a method of manufacturing a semiconductor memory device which can simplify the overall process by simultaneously forming a contact plug in contact with a memory cell and a signal line in the form of a line for inputting an external signal in one process. It is.

A method of manufacturing a semiconductor memory device according to the present invention includes forming a device isolation film on a semiconductor substrate to define a plurality of active regions, and forming a plurality of word lines across the plurality of active regions and parallel to each other on the semiconductor substrate. Forming a photoresist film including a first opening perpendicular to the word line and a second opening parallel to the word line; Selectively forming an opening for a contact line parallel to the contact hole and the word line by selectively etching the insulating film by the first opening and the second opening of the photosensitive film, and forming a conductive material in the contact hole and the opening for the contact line. Embedding a contact plug and a contact line electrically connected to the active region.

Here, the first opening of the photoresist layer is formed to overlap at least a portion of the active region and to expose a portion of the word line and a portion of the insulating layer alternately and repeatedly. In addition, the second opening of the photoresist layer is formed to overlap at least a portion of the active region and to expose the upper portion of the insulating layer.

In addition, the semiconductor memory device according to the present invention includes a plurality of active regions divided by an isolation layer formed on a semiconductor substrate, a plurality of word lines arranged in parallel with each other over the plurality of active regions, and at least two of the plurality of word lines. A contact line is formed between the word lines and is formed in parallel with the word line, and a contact plug is formed between the plurality of word lines and electrically connected to any one of the plurality of active regions.

Here, the contact line is electrically connected to a part of each of two or more active regions of the plurality of active regions. In addition, the plurality of word lines, contact lines and contact plugs are formed at the same layer level. Furthermore, the contact line functions as a signal line to which an external signal is input or output.

According to the present invention, a semiconductor manufacturing process can be simplified by simultaneously forming a contact hole and a signal line in a line shape through which external signals are inputted and outputted using a self-aligned contact (SAC) process.

In addition, the semiconductor device according to the present invention can be significantly reduced in the electrical resistance of the entire signal line, since the entire signal line is composed of a smaller number of contact plugs compared to the prior art and can further increase the cross-sectional area of the signal line. .

In particular, when the present invention is applied to a memory device based on a variable resistance device, the present invention can greatly contribute to realizing high integration and high speed operation of the device.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; Before the detailed description, it should be noted that the reference numerals added to the components of the respective drawings are denoted by the same reference numerals as much as possible, even if the same components are shown in different drawings. In describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

6 to 10 are diagrams illustrating a manufacturing process of a semiconductor memory device according to the present invention. 6 to 10 (a) is a plan view of the semiconductor device as viewed from above, (b) is a cross sectional view of the portion A-A ', and (c) is a cross sectional view of the portion B-B'.

First, referring to FIG. 6, a device isolation layer 100a is formed on a semiconductor substrate S on which a memory cell array is to be formed to distinguish a plurality of active regions 100. Thereafter, as shown in FIG. 7, a plurality of word lines 101 are formed on the semiconductor substrate on which the active region 100 is defined. The word line 101 is formed across the plurality of active regions 100, and is formed on the semiconductor substrate in order to form a gate conductive film 101b formed of a gate oxide film 101a, polysilicon, or the like, in a subsequent etching process. The hard mask film 101c protecting the film 101b is laminated. Furthermore, an insulating spacer 101d is formed to protect sidewalls of the word line pattern of the stacked structure. In this case, the hard mask film 101c and the insulating spacer 101d may be formed of a nitride film. Then, an impurity of an appropriate concentration is implanted into the active region 10 exposed on both sides of these word lines 101 to form a source or drain diffusion region 101e.

Next, after the insulating film is formed over the entire semiconductor substrate on which the word line 101 is formed, the planarization process is performed using, for example, chemical mechanical polishing (CMP), and the like. All the spaces between the 101 are filled with the insulating film 103.

Next, as shown in FIG. 9, the photosensitive film pattern 110 is formed on the semiconductor substrate on which the above-described structure is formed. Here, the photoresist pattern 110 is formed on the plurality of word lines 101 and the insulating layer 103, the first opening 110a perpendicular to the word line 101, and two word lines 101 adjacent to each other. Has a second opening 110b parallel to the wordline 101. In other words, the first opening 110a of the photoresist pattern 110 is partially overlapped with the active region 100, whereby a portion of the word line 101 and a portion of the insulating layer 103 are alternately repeated to be exposed. do. In addition, the second opening 110b of the photoresist pattern 110 is partially overlapped with the active region 110, and an upper portion of the insulating layer 103 between two adjacent word lines 101 is exposed.

Next, the insulating film 103 exposed through the first opening 110a and the second opening 110b is selectively etched using the photoresist pattern 110 formed in FIG. 9 as an etching mask. At this time, either the dry process or the wet process may be used. During this etching process, only the exposed insulating layer 103 is selectively etched without being etched because the word line 101 is protected by the hard mask film 101c. As a result, a plurality of contact holes (not shown) in which a portion of the active region 100 is exposed are formed along the first opening 110a, and a portion of the active region 100 and the device isolation layer (not shown) are formed along the second opening. A portion of 100a is alternately repeated to form exposed contact line openings (not shown).

The contact plug 104 and the contact line 105 as shown in FIG. 10 are formed by filling the conductive material in the contact holes and the contact line openings thus formed. Here, the contact plug 104 functions as a landing plug contact electrically connected to one active region (ie, either the source or drain diffusion region), and the contact line 105 includes at least two active regions 100. It is electrically connected to) and functions as a signal line for sending and receiving external signals. In addition, the contact plug 104 and the contact line 105 may preferably use a metal material having a low electrical resistance, such as tungsten (W), aluminum (Al), copper (Cu), or the like. Furthermore, before filling the conductive metal material into the contact hole and the contact line, the silicide layer may be formed in advance so as to minimize the interface resistance when bonding the exposed source or drain diffusion region with the silicon substrate. For example, a material such as titanium (Ti) or cobalt (Co) may be formed and then reacted with silicon through heat treatment to form silicide.

11 shows an example in which a spin transfer torque MRAM (STT-MRAM) is configured by using the method of manufacturing a semiconductor memory device according to the present invention. Here, the contact plug 104 is connected to one end of the magnetoresistive element 112, and the other end of the magnetoresistive element 112 is connected to the bit line 111. Here, reference numeral 113 denotes an interlayer insulating film.

In comparison with FIG. 11 and FIG. 5B manufactured by the conventional method, in FIG. 11, the contact line 105 to which an external signal is input is directly connected to the active regions 100, whereas FIG. In the case of b), the source line 15 is connected to the active regions 10 via the contact plug 15a and the landing plug 14. Therefore, it can be seen that in the semiconductor memory device according to the present invention, the electrical resistance of the entire signal line can be reduced as compared with the related art.

In addition, in the semiconductor device of FIG. 11, it can be seen that the word line 101, the contact plug 104, and the contact line 105 are formed at the same layer level. Therefore, compared with the conventional semiconductor device shown in Fig. 5B, the number of layers of the interlayer insulating film can be reduced. This means that the manufacturing method according to the present invention is simpler even with the same level of integration. Furthermore, the height of the entire structure formed on the semiconductor substrate may be lowered, and the height of the word line 101 may be relatively increased, and as a result, the cross-sectional area of the contact line 105 may be increased. Therefore, the electrical resistance of the contact line 105 itself can be further reduced when an external signal is input. In addition to the MRAM, the present invention can be more advantageously applied to high integration and high speed operation of the device when applied to semiconductor memory devices based on variable resistance devices such as PRMA, FRAM, and ReRAM.

The above description is merely illustrative of the technical idea of the present invention, and those skilled in the art to which the present invention pertains may make various modifications and changes without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention but to describe the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

1 to 5 are views illustrating a manufacturing process of a conventional semiconductor memory device, (a) is a plan view of the semiconductor device as viewed from above, (b) is a cross-sectional view of the AA 'portion, and (c) is a portion of the BB' portion. It is a cross section.

6 to 10 are views illustrating a manufacturing process of a semiconductor memory device according to the present invention, (a) is a plan view of the semiconductor device as viewed from above, (b) is a cross-sectional view of the AA ′ portion, and (c) is BB. It is a cross section of the part.

11 is a cross-sectional view of an MRAM manufactured using the method of manufacturing a semiconductor memory device according to the present invention.

* Description of the symbols for the main parts of the drawings *

100 active areas 101 wordlines

103 Insulation 104 Contact Plug

105 Contact Line 111 Bit Line

Claims (10)

Forming a device isolation film on the semiconductor substrate to define a plurality of active regions; Forming a plurality of word lines across the plurality of active regions and parallel to each other on the semiconductor substrate; Filling an insulating film between the plurality of word lines; Forming a photoresist film on the plurality of word lines and the insulating film, the photoresist film including a first opening perpendicular to the word line and a second opening parallel to the word line; Selectively etching the insulating film by the first opening and the second opening of the photosensitive film, thereby simultaneously forming a contact hole and a contact line opening parallel to the word line; Embedding a conductive material in the contact hole and the opening for the contact line to form a contact plug and a contact line electrically connected to the active region. The method of claim 1, The word lines have a structure in which a gate oxide film, a gate conductive film, and a hard mask film are sequentially stacked on the semiconductor substrate, and insulating spacers are formed on sidewalls of the word lines. The method of claim 1, The first opening of the photoresist layer overlaps at least a portion of the active region and alternately repeatedly exposes a portion of the word line and a portion of the insulating layer. The method of claim 1, The second opening of the photoresist layer overlaps at least a portion of the active region and exposes an upper portion of the insulating layer. The method of claim 1, The conductive material is a method of manufacturing a semiconductor memory device, characterized in that any one of tungsten (W), aluminum (Al) and copper (Cu). A plurality of active regions divided by device isolation layers formed on the semiconductor substrate, A plurality of word lines arranged parallel to each other over the plurality of active regions; A contact line formed between at least two word lines of the plurality of word lines, the contact line being formed in parallel with the word lines; And a contact plug formed between the plurality of word lines and electrically connected to any one of the plurality of active regions. The method of claim 6, And the contact line is electrically connected to a portion of each of at least two active regions of the plurality of active regions. The method of claim 6, And the word lines, the contact lines, and the contact plugs are formed at the same layer level. The method of claim 6, And the contact plug is electrically connected to a variable resistance element. The method of claim 6, And the contact line is a signal line to which an external signal is input.

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