KR20100010733A - Organic light emitting diode display and method for driving the same - Google Patents

Abstract

PURPOSE: An organic light emitting diode display device and a driving method thereof are provided to prevent a threshold voltage of a driving switching element from leaning to one polarity by supplying a gate low voltage of a scan line to a gate electrode of the driving switching element by a discharge transistor for a preset period. CONSTITUTION: A pixel circuit outputs a driving current using a first driving power and a second driving power. A light emitting device emits the light by a driving current from a pixel circuit. A switching transistor(Tr_S) is turned on and off according to a scan signal from a scan line and connects a data line with a first node(N1) when being turned on. A control transistor(Tr_C) is turned on and off according to a control signal from a control line and connects a second node(N2) with a third node(N3) when being turned on. A driving transistor(Tr_D) is turned on and off according to the potential of the second node and connects the third node and a second driving power line when being turned on. A discharge transistor(Tr_dis) discharges the voltage of the second node by connecting the scan line with the second node.

Description

Organic light emitting diode display and its driving method {ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD FOR DRIVING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting diode display, and more particularly, to an organic light emitting diode display and a driving method thereof capable of preventing deterioration of a driving transistor.

Recently, various flat panel display devices having a smaller weight and volume than the cathode ray tube have been developed. In particular, a light emitting display device having excellent luminous efficiency, brightness, viewing angle, and fast response speed has been attracting attention.

The light emitting device has a structure in which a light emitting layer, which is a thin film that emits light, is positioned between a cathode electrode and an anode electrode, and excitons are generated by injecting electrons and holes into the light emitting layer to recombine them, and the excitons fall to low energy to emit light. have.

In the light emitting device, the light emitting layer is formed of an inorganic material or an organic material, and is classified into an inorganic light emitting device and an organic light emitting device according to the type of the light emitting layer.

The driving current flowing through the light emitting device is controlled by the driving switching device. In other words, the driving switching element controls the magnitude of the driving current according to the data signal supplied to its gate electrode. However, since this data signal always exhibits only positive polarity, as the driving time of the driving switching device increases, the threshold voltage of the driving switching device continues to increase in either direction, thereby deteriorating the driving switching device. .

The present invention has been made to solve the above problems, by connecting the scan lines of the gate electrode low voltage state of the driving switching device to each other for a predetermined period to recover the threshold voltage of the driving switching device to its original value. An object of the present invention is to provide an organic light emitting diode display and a driving method thereof that can prevent deterioration of a driving switching device.

The organic light emitting diode display device according to the present invention for achieving the above object, from the data line using a first drive power supply from the first drive power supply line, and a second drive power supply from the second drive power supply line. A pixel circuit for outputting a driving current corresponding to a real data voltage, and a light emitting element for emitting light by the driving current from the pixel circuit; The pixel circuit may include a switching transistor that is turned on / off according to a scan signal from a scan line and connects a data line and a first node at turn-on; A control transistor that is turned on / off according to a control signal from the control line and connects the second node and the third node at turn-on; A driving transistor that is turned on / off according to the potential of the second node and connects the third node and the second driving power line when turned on; And a discharge transistor configured to be turned on during a period during which the scan line is maintained at a low voltage to connect the scan line and the second node to discharge the voltage of the second node. It is done.

An organic light emitting diode display according to the present invention comprises: a first storage capacitor connected between the first node and a second node; A second storage capacitor connected between the second node and the second driving power line; And a variable capacitor connected between the control line and the second node.

The pixel circuit and the light emitting device may detect a first initialization period for initializing the voltage of the third node, a threshold voltage detection preparation period for increasing the voltage of the second and third nodes, and detect a threshold voltage of the driving transistor. A threshold voltage detection period stored in the second storage capacitor, a second initialization period for initializing a voltage of a third node, a real data input period for supplying the real data voltage to the data line, and the real data voltage A driving current is generated and driven by a light emission period in which the light emitting element emits light by the driving current; Some of the periods during which the scan line is maintained at the low voltage correspond to some of the emission periods.

The first driving power source is a signal having a high voltage having a relatively high voltage, a low voltage having a relatively low voltage, and an intermediate voltage having a value between the high voltage and the low voltage, the first driving power supply being a first initialization period. And remain in a low voltage state for a part of the threshold voltage detection preparation period, remain at an intermediate voltage from the remaining part of the threshold voltage detection period to the actual data input period, and remain at a high voltage during the light emission period; The second driving power source is a direct current signal maintained in a low voltage state for all periods; The control signal is maintained at a high voltage (H) for a part of the threshold voltage detection period and at a low voltage for the remainder of the period; The scan signal is maintained at a high voltage during a portion of a first initialization period, a threshold voltage detection period, and a second initialization period, and is held at a high voltage for a portion of the actual data input period; The real data voltage is maintained at a high voltage for the real data input period and at a low voltage for the remaining period.

The discharge transistor is turned on / off in response to a discharge signal from the outside; The discharge signal may be maintained at a high voltage for a part of the light emitting period and at a low voltage for the remaining period.

In addition, the driving method of the organic light emitting diode display device according to the present invention for achieving the above object, by using the first driving power source from the first driving power line, and the second driving power source from the second driving power supply line. A pixel circuit for outputting a drive current corresponding to the actual data voltage from the data line, and a light emitting element for emitting light by the drive current from the pixel circuit; A switching transistor, wherein the pixel circuit is turned on / off according to a scan signal from a scan line and connects the data line and the first node when the pixel circuit is turned on; A control transistor that is turned on / off according to a control signal from the control line and connects the second node and the third node at turn-on; A driving method of an organic light emitting display device, comprising: a driving transistor turned on / off according to a potential of the second node, the driving transistor connecting a connection between the third node and the second driving power line when turned on; Initializing a voltage of the third node; Increasing the voltage at the second and third nodes; Detecting a threshold voltage of the driving transistor and storing the threshold voltage in the second storage capacitor; Initializing a voltage of the third node; Supplying the real data voltage to the data line: generating a driving current corresponding to the real data voltage and emitting the light emitting element with the driving current; And discharging the voltage of the second node by connecting between the scan line and the second node during a part of the light emission period corresponding to a period in which the scan line is maintained at a low voltage. It is done.

Discharging the voltage of the second node is performed by a discharge transistor; The discharge transistor may be turned on / off according to a discharge signal from an external device, and may be connected between the second node and the scan line during turn-on.

The discharge signal is maintained at a high voltage for a part of the light emitting period and at a low voltage for the remaining period.

An organic light emitting diode display and a driving method thereof according to the present invention have the following effects.

According to the organic light emitting diode display according to the present invention, the gate low voltage of the scan line is supplied to the gate electrode of the driving switching element by a discharge transistor for a predetermined period so that the threshold voltage of the driving switching element is biased to either polarity. You can prevent it.

1 is a view showing a light emitting display device according to the present invention.

Referring to FIG. 1, a light emitting display device according to an exemplary embodiment of the present invention includes m data lines DL1 to DLm to which a data voltage Data is supplied, where m is a natural number, and n to which a scan signal is supplied. Is a natural number different from m), the first scan power supply VDD line (not shown) to which the first driving power supply VDD is supplied, and the second driving power supply VSS are supplied. A display unit 100 including a second driving power line (not shown), a control signal line (not shown) to which a control signal Vc is supplied, and a plurality of pixel cells PXL; And a scan driver 200 for driving each scan line SL1 through SLn, and a data driver 300 for supplying a data voltage Data to each of the data lines DL1 through DLm.

The scan driver 200 generates a scan signal using a start pulse and a clock signal (not shown), and supplies the generated scan signal to each scan line SL1 to SLn. The characteristics of these scan signals will be described in more detail later.

The data driver 300 generates a data voltage Data according to data control signals (not shown) and supplies the data voltages to the data lines DL1 to DLm. At this time, the data driver 300 supplies the data voltage Data for each horizontal line to each data line DL1 to DLm every one horizontal period.

The m pixel cells PXL in one horizontal line are commonly connected to one scan line and individually connected to the m data lines. For example, all of the first to m th pixel cells PXL arranged along the first horizontal line HL1 are commonly connected to the first scan line SL1, and the first to m th data lines DL1 to m. DLm) are each individually connected. In other words, the first pixel cell PXL of the first horizontal line HL1 is connected to the first data line DL1, and the second pixel cell PXL of the first horizontal line HL1 is second data. The third pixel cell PXL of the first horizontal line HL1 is connected to the third data line DL3, ..., and the mth of the first horizontal line HL1. The pixel cell PXL is connected to the m th data line DLm.

The first and second driving power lines and the control line are commonly connected to all the pixel cells PXL.

Herein, the structure of each pixel cell PXL will be described in more detail.

FIG. 2 is a diagram illustrating a circuit configuration of an arbitrary pixel cell PXL of FIG. 1.

As illustrated in FIG. 2, the pixel cell PXL uses a plurality of transistors Tr_C, Tr_S, Tr_D, and Tr_dis, a scan signal, a first driving power source VDD, and a second driving power source VSS. And a pixel circuit PD which outputs a driving current corresponding to the data voltage Data from the data line, and a light emitting element OLED which emits light by the driving current from the pixel circuit PD.

The pixel circuit further includes first and second storage capacitors CPst1 and CPst2 and a variable capacitor CPv in addition to the above-described transistors. The transistors include a switching transistor Tr_S, a control transistor Tr_C, a driving transistor Tr_D, and a discharge transistor Tr_dis.

The switching transistor Tr_S is turned on / off according to a scan signal from the scan line and connects the data line and the first node N1 at turn-on. For this purpose, the gate electrode of the switching transistor Tr_S is connected to the scan line, the source electrode (or drain electrode) is connected to the data line, and the source electrode (or drain electrode) is connected to the first node N1. do.

The control transistor Tr_C is turned on / off according to a control signal from the control line and connects the second node N2 and the third node N3 at turn-on. To this end, the gate electrode of the control transistor Tr_C is connected to the control line, the drain electrode (or source electrode) is connected to the second node N2, and the source electrode (or drain electrode) is connected to the third node N3. ) Is connected.

The driving transistor Tr_D is turned on / off according to the potential of the second node N2 and connects the third node N3 and the second driving power line during turn-on. To this end, the gate electrode of the driving transistor Tr_D is connected to the second node N2, the drain electrode (or source electrode) is connected to the third node N3, and the source electrode (or drain electrode) is It is connected to the second drive power line.

The discharge transistor Tr_dis is turned on for a part of the period during which the scan line is maintained at a low voltage to connect the scan line with the second node N2 to discharge the voltage of the second node N2. It is a switching device that serves to make. The discharge switching element is turned on / off according to a discharge signal Voff from the outside and electrically connects the second node N2 and the scan line at turn-on.

The first storage capacitor CPst1 is connected between the first node N1 and the second node N2. The first storage capacitor CPst1 maintains the voltage of the second node N2 stably and prevents the voltage of the second node N2 and the voltage of the first node N1 from being mixed with each other.

The second storage capacitor CPst2 is connected between the first node N1 and the second driving power line. The second storage capacitor CPst2 prevents the voltage of the first node N1 from changing when the switching transistor Tr_S is turned off and the first node N1 is in a floating state.

The variable capacitor CPv is connected between the control line and the second node N2. This variable capacitor (CPv) is the capacitance of the parasitic capacitor of each transistor And the parasitic capacitances Cgs and Cgd, which are parasitic components of the driving transistor Tr_D, and the channel capacitance cancel their error deviations during the compensating operation of the pixel with their own capacitances, thereby preventing a change in the voltage of the first node N1. . As a result, it contributes to improving the compensation characteristics.

The light emitting device OLED includes a cathode electrode connected to the third node N3, an anode electrode connected to the first driving power supply line VDD, and a light emitting layer formed between the cathode electrode and the anode electrode. The light emitting layer may be a light emitting layer of an organic material or a light emitting layer of an inorganic material. The light emitting element OLED emits light by the driving current from the driving transistor Tr_D.

The scan signal, the data voltage Data, the first driving power supply VDD, the second driving power supply VSS, and the control signal Vc supplied to the pixel cell PXL configured as described above will be described in detail as follows. same.

3 is a diagram illustrating various signal waveforms supplied to the display unit 100 including a plurality of pixel cells PXL having the structure as illustrated in FIG. 2.

First, as shown in FIG. 3, the driving of the light emitting display device according to the present invention includes a first initialization period D1, a threshold voltage detection preparation period D2, a threshold voltage detection period D3, and a second initialization period. The description can be made by dividing into (D4), the actual data input period D5, and the light emission period D6.

As illustrated in FIG. 3, the first driving power supply VDD is an AC signal having three different levels. That is, the first driving power supply VDD has a high voltage H having a relatively high voltage, a low voltage L having a relatively low voltage, and an intermediate voltage having a value between the high voltage H and the low voltage L. As a signal having M), this first drive power source VDD periodically exhibits a low voltage L, an intermediate voltage M and a high voltage H.

The high voltage (H) can be set to about 15 [V], the medium voltage (M) to about 0 [V], and the low voltage (L) to about -10 [V]. Can be varied.

The first driving power source VDD is maintained at the low voltage L state for a part of the first initialization period D1 and the threshold voltage detection preparation period D2, and is actually started from the remaining part of the threshold voltage detection period D3. The intermediate voltage M is maintained until the data input period D5. In addition, the first driving power supply VDD is maintained at a high voltage H during the light emission period D6.

As shown in FIG. 3, the second driving power source VSS is a DC signal maintained at a low voltage L state for all periods.

As shown in FIG. 3, the control signal Vc is maintained at the high voltage H for a part of the threshold voltage detection period D3 and at the low voltage L for the remaining period. Unlike the scan signals SC1 to SCn inputted for each horizontal line, the control signal Vc, like the first driving power source VDD and the second driving power source VSS, includes all the pixel cells PXL of the entire display unit 100. These signals are commonly input to the.

As shown in FIG. 3, the discharge signal Voff is maintained at a high voltage H for a part of the light emission period D6 and at a low voltage L for the remaining period.

Each scan signal is maintained at a high voltage H during a part of the first initialization period D1, the threshold voltage detection period D3, and the second initialization period D4. D5) is sequentially maintained at the high voltage H. That is, as shown in FIG. 3, the first scan signal SC1 is maintained at the high voltage H during the first 10-1 period T10-1 of the actual data input period D5 and the second scan. The signal SC2 is maintained at the high voltage H for the second preceding 10-2 period T10-2 of the actual data input period D5, and the third scan signal SC3 is the actual data input period ( The third one of D5) is maintained at the high voltage H for the tenth prior period T10-3.

The data voltage Data is maintained at the high voltage H during the first initialization period D1, the second initialization period D4, and the real data input period D5, and is maintained at the low voltage L for the remaining periods.

The magnitudes of the high voltages H between the signals described above may have the same value, or may have different values. Similarly, the magnitudes of the low voltages L between the signals may have the same value or may have different values.

The operation of the pixel cell PXL receiving such signals will be described in detail as follows.

4A to 4L are flowcharts illustrating operations of the light emitting display device according to the embodiment of the present invention.

Here, since the operations of all the pixel cells PXL are the same, operations of the first pixel cell PXL connected to the first scan line SL1 and the first data line DL1 will be representatively described.

An operation of the first period T1 will now be described with reference to FIGS. 4A and 3.

In the first period T1, as shown in FIG. 3, only the data voltage Data is in the high voltage H state, and the first driving power supply VDD, the second driving power supply VSS, and the control signal Vc are shown. , And scan signals are all at low voltage (L). As shown in FIG. 4A, the data voltage Data is supplied to the first data line DL1 to charge the first data line DL1 to the high voltage H. As shown in FIG. In this first period T1, all the transistors and the light emitting element OLED are all turned off.

Since the data of the high voltage H is supplied to the first data line DL1 during the first period T1 before the switching transistor Tr_S is turned on, the first data line DL1 will be described later. In the two period T2, the battery is sufficiently charged to the target voltage.

On the other hand, in the period immediately before the first period T1, since the first driving power supply VDD was sufficiently maintained at the low voltage L, the third node N3 in this period and the first period T1. ) Is very low. That is, due to the parasitic capacitor of the light emitting device OLED formed between the first power line and the third node N3 to which the first driving power supply VDD is supplied, the first driving power supply VDD is low voltage (L). The voltage at the third node N3 is also lowered when the voltage drops to.

An operation of the second period T2 will now be described with reference to FIGS. 4B and 3.

In the second period T2, as shown in FIG. 3, the data voltage Data and all the scan signals are in the high voltage H state, and the first driving power source VDD, the second driving power source VSS, and the control are shown. The signal Vc is in the low voltage L state. That is, in the second period T2, the scan signals are changed from the low voltage L to the high voltage H.

Since all scan signals including the first scan signal SC1 are in a high voltage state, as shown in FIG. 4B, the switching transistor Tr_S receiving the first scan signal SC1 through a gate electrode is provided. Is turned on. Then, the data voltage Data (data voltage Data in the high voltage H state) from the first data line DL1 is supplied to the first node N1 through the turned-on switching transistor Tr_S. do. Accordingly, the first node N1 is charged to the high voltage H state. At this time, the voltage of the second node N2 is increased by the first storage capacitor CPst1 connected between the first node N1 and the second node N2. Accordingly, the driving transistor Tr_D connected to the second node N2 through the gate electrode is turned on. Then, the second driving power source VSS in the low voltage L state is supplied to the third node N3 through the turned-on driving transistor Tr_D. Accordingly, the third node N3 is initialized.

An operation of the third period T3 will be described with reference to FIGS. 4C and 3 as follows.

In the third period T3, as shown in FIG. 3, all the scan signals are in the high voltage H state, the data voltage Data, the first driving power supply VDD, the second driving power supply VSS, and the control. The signal Vc and the scan signal are in the low voltage L state. That is, in this third period T3, the data voltage Data is changed from the high voltage H to the low voltage L.

Since all scan signals including the first scan signal SC1 are in the high voltage H state, as shown in FIG. 4C, the switching transistor Tr_S maintains the turn-on state. The data voltage Data (data voltage Data in the low voltage L state) from the first data line DL1 is supplied to the first node N1 through the turned-on switching transistor Tr_S. Accordingly, the first node N1 is discharged to the low voltage L state. At this time, the voltage of the second node N2 is also lowered by the first storage capacitor CPst1 connected between the first node N1 and the second node N2. Accordingly, the driving transistor Tr_D connected to the second node N2 through the gate electrode is turned off.

In this way, the third node N3 is initialized to the low voltage L during the first initialization period D1 including the first to third periods T3. That is, the third node N3 is initialized with the second driving power source VSS. The second driving power supply VSS is set to a voltage of about 0 [V], so that the third node N3 is increased from a negative voltage to a voltage of 0 [V].

An operation of the fourth period T4 will be described with reference to FIGS. 4D and 3 as follows.

In the fourth period T4, as shown in FIG. 3, the second driving power source VSS, the control signal Vc, all the scan signals, and the data voltage Data low voltage L are in the first driving state. The power supply VDD is changed from the low voltage L to the intermediate voltage M. FIG.

Since all scan signals including the first scan signal SC1 are in the low voltage L state, as shown in FIG. 4D, the switching transistor Tr_S is turned off. As a result, the first node N1 is in a floating state.

Meanwhile, as the first driving power source VDD rises from the low voltage L to the intermediate voltage M, the voltage of the third node N3 also increases. That is, the voltage of the third node N3 is increased by the parasitic capacitor of the light emitting device OLED formed between the first power line and the third node N3 to which the first driving power source VDD is supplied. In this case, the third node N3 receives a voltage obtained by subtracting the threshold voltage Vth of the light emitting device OLED from the first driving power supply VDD in the high voltage H state.

The third node N3 is a drain electrode of the driving transistor Tr_D. The voltage of the gate electrode and the drain electrode of the driving transistor Tr_D must be increased before the threshold voltage of the driving transistor Tr_D is increased. It is advantageous in detecting (Vth). Accordingly, the size of the first driving power supply VDD is increased from the low voltage L to the intermediate voltage M during the fourth period T4, which is the threshold voltage detection preparation period D2, of the driving transistor Tr_D. The voltage of the drain electrode can be raised.

Here, when the voltage of the drain electrode of the driving transistor Tr_D rises slightly in the state where the first node N1 is floated, the voltage of the gate electrode of the driving transistor Tr_D is increased due to the coupling phenomenon. It can rise slightly. This coupling phenomenon is caused by a parasitic capacitor formed between the gate electrode and the drain electrode of the driving transistor Tr_D.

In this manner, the voltages of the second and third nodes N3 are increased in the fourth period T4.

An operation of the fifth period T5 will be described with reference to FIGS. 4E and 3 as follows.

In the fifth period T5, as shown in FIG. 3, the first driving power supply VDD is maintained at the intermediate voltage M state, and the second driving power supply VSS, the control signal Vc, and the data voltage are maintained. While (Data) remains at the low voltage (L) state, all scan signals are changed from the low voltage (L) to the high voltage (H).

As the first scan signal SC1 rises to the high voltage H, as shown in FIG. 4E, the switching transistor Tr_S is turned on. Then, the data voltage Data (data voltage Data in the low voltage L state) from the first data line DL1 is supplied to the first node N1 through the turned-on switching transistor Tr_S. do. Since the first node N1 was in a state of being maintained at the data voltage Data of the low voltage L state in a floating state until the previous period, the first node N1 in the fifth period T5. The potentials of N1) and the second node N2 are not changed.

An operation of the sixth period T6 will be described with reference to FIGS. 4F and 3 as follows.

In the sixth period T6, as shown in FIG. 3, the first driving power source VDD is maintained at the intermediate voltage M state, and the second driving power source VSS and the data voltage Data are low voltage ( State L), and all the scan signals remain in the high voltage H state, while the control signal Vc is changed from the low voltage L to the high voltage H.

As the control signal Vc rises to the high voltage H, as shown in FIG. 4F, the control transistor Tr_C is turned on. Then, the second node N2 and the third node N3 are short-circuited to each other through the turned-on control transistor Tr_C, thereby shortening the gate electrode and the drain electrode of the driving transistor Tr_D to each other. Accordingly, the voltage of the second node N2 and the voltage of the third node N3 are mixed with each other, and the mixed voltage is charged to the second and third nodes N3 with the same value. This mixed voltage should be set higher than the threshold voltage Vth of the driving transistor Tr_D. For this purpose, the threshold voltage is changed from the voltage of the second node N2 and the voltage of the third node N3 in the previous period. It was set larger than the pressure (Vth).

The driving transistor Tr_D having the gate electrode and the drain electrode shorted to each other is turned on to operate like a diode. At this time, the mixed voltage gradually decreases toward the threshold voltage Vth of the driving transistor Tr_D, and the driving transistor Tr_D is turned on at the moment when the mixed voltage becomes equal to the threshold voltage Vth. -Off. As a result, the threshold voltage Vth of the driving transistor Tr_D is stored in the second and third nodes N3 at the moment when the driving transistor Tr_D is turned off.

As described above, the threshold voltage Vth of the driving transistor Tr_D is stored in the second and third nodes N3 during the threshold voltage detection period D3 including the sixth period T6. During this threshold voltage detection period, the threshold voltage Vth of the driving transistor Tr_D is stored in each of the second and third nodes N3 of all the pixel cells PXL. Since the characteristics of the driving transistors Tr_D included in each pixel cell PXL may be different depending on the manufacturing environment, the threshold voltages stored in the second and third nodes N3 of each pixel cell PXL may be different. The size of Vth) may be different.

An operation of the seventh period T7 will be described with reference to FIGS. 4G and 3 as follows.

In the seventh period T7, as shown in FIG. 3, the first driving power supply VDD is maintained at the intermediate voltage M state, and the second driving power supply VSS and the data voltage Data are low voltage ( State L), and all the scan signals remain in the high voltage H state, while the control signal Vc is changed from the high voltage H to the low voltage L.

As the control signal Vc drops to the low voltage L, the control transistor Tr_C is turned off, as shown in FIG. 4G. In the seventh period T7, the threshold voltage Vth of the driving transistor Tr_D is stored in the second and third nodes N3, respectively.

An operation of the eighth period T8 will be described with reference to FIGS. 4H and 3 as follows.

In the eighth period T8, as shown in FIG. 3, the first driving power supply VDD is maintained at the intermediate voltage M state, and the second driving power supply VSS and the control signal Vc are low voltage ( L) and all the scan signals remain at the high voltage (H) state, while the data voltage (Data) is changed from the low voltage (L) to the high voltage (H).

As the data voltage Data rises to the high voltage H, both the voltage of the first node N1 and the voltage of the second node N2 increase. Accordingly, the driving transistor Tr_D is turned on, and the second driving power VSS having the low voltage L state is supplied to the third node N3 through the turned-on driving transistor Tr_D. . Accordingly, all of the third nodes N3 of all the pixel cells PXL are initialized to the same voltage value.

The eighth period T8 is a period in which the third node N3 is initialized in advance in order to prepare for driving of the light emitting device OLED by actual data input.

As described above, since the threshold voltage Vth of the driving transistor Tr_D of each pixel cell PXL may be different from each other, the voltage value of the third node N3 in which the threshold voltage Vth is stored is equal to each pixel. All may vary by cell (PXL). Accordingly, by supplying the data of the high voltage H state to all the pixel cells PXL in the eighth period T8, the second driving power source VSS is identical to all of the third nodes N3 in all the pixel cells PXL. Is preferably initialized to

An operation of the ninth period T9 will be described with reference to FIGS. 4I and 3 as follows.

In the ninth period T9, as shown in FIG. 3, the first driving power supply VDD is maintained at the intermediate voltage M state, and the second driving power supply VSS and the control signal Vc are low voltage ( L) state, and all the scan signals remain at the high voltage (H) state, while the data voltage Data is changed from the high voltage (H) to the low voltage (L).

As the data voltage Data falls to the low voltage L, both the voltage of the first node N1 and the voltage of the second node N2 fall. The second node N2 returns to the threshold voltage Vth value previously set. As a result, the driving transistor Tr_D is turned off. As a result, the third node N3 is initialized to the second driving power source VSS, and the second node N2 stores the threshold voltage Vth.

An operation of the tenth period T10 will be described with reference to FIGS. 4J and 3 as follows.

In the tenth period T10, as shown in FIG. 3, the first driving power supply VDD is maintained at the intermediate voltage M state, and the second driving power supply VSS and the control signal Vc are low voltage ( L) is maintained.

All scan signals are in turn kept in a high voltage (H) state for a period of time. That is, the tenth period T10 is a real data input period D5, which includes the tenth to tenth to ten-n periods T10-1 to T10-n. The first to nth scan signals SC1 to SCn are sequentially maintained in the high voltage H state for the corresponding periods during the 10-1 to 10-n periods T10-1 to T10-n. In addition, the data supplied to the m data lines during the tenth period T10 are actual data to be represented, and each of these real data are all 0 [V] to several tens [during the tenth period T10. Maintain high voltage (H) state between V].

Only the first scan line SL1 of the plurality of scan lines is driven during the tenth-first period T10-1, and the second scan of the plurality of scan lines during the tenth-second period T10-2. Only the line SL2 is driven, and only the third scan line of the plurality of scan lines is driven during the 10-3 time period T10-3, ..., during the 10-n period T10-n. Is the n th scan line SLn of the plurality of scan lines.

When each scan line is driven, all of the pixel cells PXL for one horizontal line connected to the corresponding scan line are driven. Accordingly, when one scan line is driven, real data is supplied to the pixel cells PXL for one horizontal line connected to the scan line.

A process of supplying the real data will be described below with reference to the first pixel cell PXL.

The first pixel cell PXL receives the data of the high voltage H state in the 10-1 period T10-1. This data is supplied to the first node N1 through the first data line DL1. Then, the voltage of the first node N1 is increased to the data voltage Data, and as the voltage of the first node N1 is increased, the voltage of the second node N2 also increases. That is, the voltage of the second node N2 is increased by the first storage capacitor CPst1 connected between the first node N1 and the second node N2. At this time, the voltage of the second node N2 is further increased by the magnitude of the voltage input to the first node N1.

If this is explained in more detail as follows. Here, for convenience of description, the number of real data supplied to the first node N1 will be expressed as Vdata.

That is, since the threshold voltage Vth of the driving transistor Tr_D detected during the above-described threshold voltage detection period D3 is stored in the second node N2, the actual data is stored in the first node N1. As is applied, the voltage of the second node N2 is defined as the sum of the real data and the threshold voltage Vth. However, since the voltage of the second node N2 is affected by various parasitic capacitors and the first storage capacitor CPst1 present in the driving transistor Tr_D, the voltage of the second node N2 is It is defined by the first equation of.

In the first equation, Vn2 denotes the voltage of the second node N2, first Cst1 denotes the capacitance of the first storage capacitor CPst1, and Cgs denotes the gate electrode and the source of the driving transistor Tr_D. The capacitance of the parasitic capacitor Cgs existing between the electrodes, and Cgd means the capacitance of the parasitic capacitor Cgd existing between the gate electrode and the drain electrode of the driving transistor Tr_D.

As described above, the size of the second node N2 is different from the compensation value (threshold voltage Vth + real data voltage Data) originally intended by the parasitic capacitors Cgs and Cgd to compensate for the threshold voltage Vth. Although the capability may be somewhat degraded, this problem may be solved by the variable capacitor CPv. That is, the variable capacitor CPv is designed to be appropriately sized to compensate for the voltage deviation of the second node N2 generated according to the magnitude of the parasitic capacitance generated by the parasitic capacitors Cgs and Cgd described above. To change their compensation capacity. Specifically, the variable capacitor CPv minimizes the parasitic capacitance by canceling the parasitic capacitance to the opposite compensation capacitance.

During the real data input period D5, a voltage corresponding to the sum of the threshold voltage Vth and the real data voltage Data of the driving transistor Tr_D at each second node N2 of all the pixel cells PXL. These are stored sequentially in horizontal line units. That is, in the 10-1 period T10-1, each of the m pixel cells PXL arranged along the first horizontal line HL1 is connected to its second node N2 with a driving voltage (a driving transistor) Threshold voltage Vth + real data voltage Vdata of Tr_D is stored, and m pixel cells PXL arranged along a second horizontal line HL2 in a 10-2 period T10-2. Each of the pixels stores the driving voltage in its second node N2, and then each of the m pixel cells PXL arranged along the third horizontal line HL3 in the 10-3 period T10-3. The driving voltage is stored in its own second node N2, and then m pixel cells PXL arranged along the nth horizontal line HLn in the tenth-n period T10-n. ) Stores a driving voltage at its second node N2. Accordingly, the driving transistors Tr_D of all the pixel cells PXL are sequentially turned on in the horizontal line unit. At this time, since the first driving power source VDD is at the low voltage L state, a driving current is not generated even when the driving transistor Tr_D is turned on. Therefore, the light emitting element OLED does not emit light in this tenth period T10.

An operation of the eleventh period T11 will be described with reference to FIGS. 4K and 3 as follows.

In the eleventh period T11, as shown in FIG. 3, the second driving power source VSS, the control signal Vc, and all the scan signals are kept at the low voltage L, while the data voltage Data is maintained. The voltage is changed from the high voltage H to the low voltage L. In particular, the eleventh period T11 is a light emitting period D6 for emitting the light emitting elements OLED of all the pixel cells PXL. For this purpose, the first driving power source VDD is used during the eleventh period T11. The intermediate voltage M is changed to the high voltage H.

As the first driving power source VDD is raised to the high voltage H, the turned-on driving transistors Tr_D of all the pixel cells PXL flow a driving current through their drain and source electrodes. As each driving current is transmitted to the cathode through the anode electrode of each light emitting device OLED, the light emitting devices OLED of all the pixel cells PXL emit light with luminance according to the size of the driving current supplied thereto.

In this case, the driving current supplied to each light emitting device OLED is defined by the following second equation.

Here, I _OLED denotes a current flowing from the drain electrode of the driving transistor Tr_D toward the source electrode, Vgs denotes the voltage between the gate and source electrodes of the driving transistor Tr_D, and β denotes a constant value. it means.

On the other hand, as shown in FIGS. 4L and 3, the discharge transistor Tr_dis is turned on as the discharge signal Voff is maintained at the high voltage H during a part of the light emission period D6. Then, the second node N2 and the scan line are electrically connected to each other by the turned-on discharge transistor Tr_dis, and thus, the gate electrode of the second node N2, that is, the discharge transistor Tr_dis. The applied data voltage is discharged. Therefore, the voltage of the second node N2 is changed from the electrode property to the negative voltage, and the discharge transistor Tr_dis is turned off.

Every frame period, the first initialization period D1, the threshold voltage detection preparation period D2, the threshold voltage detection period D3, the second initialization period D4, the actual data input period D5, and the light emission period D6. ) Is repeatedly performed to prevent deterioration of the discharge transistor Tr_dis as the voltage of the second node N2 periodically changes from positive polarity to negative polarity.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 is a view showing a light emitting display device according to the present invention;

FIG. 2 is a circuit diagram illustrating an arbitrary pixel cell of FIG. 1.

3 is a diagram illustrating various signal waveforms supplied to a display unit including a plurality of pixel cells having a structure as illustrated in FIG. 2.

4A to 4L are flowcharts illustrating operations of a light emitting display device according to an exemplary embodiment of the present invention.

Claims (8)

A pixel circuit for outputting a driving current corresponding to a real data voltage from a data line by using a first driving power supply from a first driving power supply line and a second driving power supply from a second driving power supply line; A light emitting device that emits light by a driving current of; The pixel circuit, A switching transistor that is turned on / off according to a scan signal from the scan line and connects the data line and the first node at turn-on; A control transistor that is turned on / off according to a control signal from the control line and connects the second node and the third node at turn-on; A driving transistor that is turned on / off according to the potential of the second node and connects the third node and the second driving power line when turned on; And, And a discharge transistor which is turned on for a part of the period during which the scan line is maintained at a low voltage to connect the scan line and the second node to discharge the voltage of the second node. Diode display. The method of claim 1, A first storage capacitor connected between the first node and a second node; A second storage capacitor connected between the second node and the second driving power line; And, And a variable capacitor connected between the control line and the second node. The method of claim 2, The pixel circuit and the light emitting device may detect a first initialization period for initializing the voltage of the third node, a threshold voltage detection preparation period for increasing the voltage of the second and third nodes, and detect a threshold voltage of the driving transistor. A threshold voltage detection period stored in the second storage capacitor, a second initialization period for initializing a voltage of a third node, a real data input period for supplying the real data voltage to the data line, and the real data voltage A driving current is generated and driven by a light emission period in which the light emitting element emits light by the driving current; And a part of the period during which the scan line is maintained at a low voltage corresponds to a part of the light emitting period. The method of claim 3, wherein The first driving power source is a signal having a high voltage having a relatively high voltage, a low voltage having a relatively low voltage, and an intermediate voltage having a value between the high voltage and the low voltage. Is kept in a low voltage state for a part of the threshold voltage detection preparation period, remains at an intermediate voltage from the remaining part of the threshold voltage detection period to the actual data input period, and is maintained at a high voltage during the light emission period; The second driving power source is a direct current signal maintained in a low voltage state for all periods; The control signal is maintained at a high voltage (H) for a part of the threshold voltage detection period, and at a low voltage for the remainder of the period; The scan signal is maintained at a high voltage during a portion of a first initialization period, a threshold voltage detection period, and a second initialization period, and is held at a high voltage for a portion of the actual data input period; And, And the real data voltage is maintained at a high voltage for the real data input period and at a low voltage for the remaining period. The method of claim 4, wherein The discharge transistor is turned on / off in response to a discharge signal from the outside; And, And the discharge signal is maintained at a high voltage for some of the light emitting periods and at a low voltage for the remaining periods. A pixel circuit for outputting a driving current corresponding to a real data voltage from a data line by using a first driving power supply from a first driving power supply line and a second driving power supply from a second driving power supply line; A light emitting element emitting light by a driving current of; A switching transistor, wherein the pixel circuit is turned on / off according to a scan signal from a scan line and connects the data line and the first node when the pixel circuit is turned on; A control transistor that is turned on / off according to a control signal from the control line and connects the second node and the third node at turn-on; A driving method of an organic light emitting display device, comprising: a driving transistor turned on / off according to a potential of the second node, the driving transistor connecting a connection between the third node and the second driving power line when turned on; Initializing a voltage of the third node; Increasing the voltage at the second and third nodes; Detecting a threshold voltage of the driving transistor and storing the threshold voltage in the second storage capacitor; Initializing a voltage of the third node; Supplying the real data voltage to the data line: Generating a driving current corresponding to the real data voltage and emitting the light emitting element with the driving current; And, And discharging a voltage of the second node by connecting between the scan line and the second node during a part of the emission period corresponding to a period in which the scan line is maintained at a low voltage. Method of driving a diode display device. The method of claim 6, Discharging the voltage of the second node is performed by a discharge transistor; And, And the discharge transistor is turned on / off in response to a discharge signal from an external device, and connects the second node and the scan line when the discharge transistor is turned on. The method of claim 7, wherein And the discharge signal is maintained at a high voltage for some of the light emitting periods and at a low voltage for the remaining periods of the light emitting period.

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