KR101419244B1 - Organic light emitting diode display and method for driving the same - Google Patents

Abstract

The present invention relates to an organic light emitting diode (OLED) display device capable of preventing deterioration of a driving transistor and a method of driving the same, A pixel circuit for outputting a driving current corresponding to an actual data voltage from the data line using the pixel circuit and a light emitting element for emitting light by a driving current from the pixel circuit; The pixel circuit may include a switching transistor that is turned on / off according to a scan signal from the scan line and connects the data line and the first node when the turn-on transistor is turned on. A control transistor which is turned on / off according to a control signal from the control line and connects between the second node and the third node when the transistor is turned on; A driving transistor which is turned on / off according to a potential of the second node and connects the third node and the second driving power source when the first node is turned on; And a discharging transistor for turning on the scan line for a part of the period during which the scan line is maintained at a low voltage and connecting the scan line and the second node to discharge the voltage of the second node. .

Organic light emitting diode display device, driving switching device, deterioration, light emitting device

Description

Technical Field [0001] The present invention relates to an organic light emitting diode (OLED) display device and a method of driving the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting diode (OLED) display device, and more particularly, to an organic light emitting diode display device capable of preventing deterioration of a driving transistor and a driving method thereof.

2. Description of the Related Art Various flat panel display devices having smaller weight and volume than those of a cathode ray tube have been developed in recent years. Particularly, a light emitting display device having excellent luminous efficiency, luminance and viewing angle and fast response speed has been attracting attention.

The light emitting device has a structure in which a light emitting layer, which is a thin film that emits light, is positioned between the cathode electrode and the anode electrode, and excitons are generated by injecting electrons and holes into the light emitting layer and recombining them, have.

In such a light emitting device, the light emitting layer is made of an inorganic material or an organic material, and is classified into an inorganic light emitting device and an organic light emitting device depending on the type of the light emitting layer.

The drive current flowing through the light emitting element is controlled in size by a drive switching element. That is, this drive switching element controls the magnitude of the drive current according to the data signal supplied to its gate electrode. However, since the data signal always exhibits only positive polarity, the threshold voltage of the driving switching element continuously increases in one direction as the driving time of the driving switching element increases, which deteriorates the driving switching element .

SUMMARY OF THE INVENTION The present invention has been made in order to solve the problems described above, and it is an object of the present invention to provide a method and a device for controlling a threshold voltage of a driving switching element by connecting scan- An organic light emitting diode (OLED) display device capable of preventing deterioration of a driving switching element and a driving method thereof.

According to an aspect of the present invention, there is provided an organic light emitting diode (OLED) display device, including: a first driving power source supplying a first driving power from a first driving power supply line and a second driving power from a second driving power supply line, A pixel circuit for outputting a driving current corresponding to a real data voltage, and a light emitting element for emitting light by a driving current from the pixel circuit; The pixel circuit may include a switching transistor that is turned on / off according to a scan signal from the scan line and connects the data line and the first node when the turn-on transistor is turned on. A control transistor which is turned on / off according to a control signal from the control line and connects between the second node and the third node when the transistor is turned on; A driving transistor which is turned on / off according to a potential of the second node and connects the third node and the second driving power source when the first node is turned on; And a discharging transistor for turning on the scan line for a part of the period during which the scan line is maintained at a low voltage and connecting the scan line and the second node to discharge the voltage of the second node. .

An organic light emitting diode display device according to the present invention includes: a first storage capacitor connected between a first node and a second node; A second storage capacitor connected between the second node and the second driving power supply line; And a variable capacitor connected between the control line and a second node.

Wherein the pixel circuit and the light emitting element detect a threshold voltage of the driving transistor by a first initializing period for initializing a voltage of the third node, a threshold voltage detecting preparation period for increasing a voltage of the second and third nodes, A second initialization period for initializing the voltage of the third node, and a real data input period for supplying the actual data voltage to the data line, And a light emitting period for emitting the light emitting element with the driving current; And a part of the period during which the scan line is maintained at a low voltage corresponds to a part of the light emission period.

The first driving power source is a signal having a high voltage having a relatively high voltage, a low voltage having a relatively low voltage, and an intermediate voltage having a value between the high voltage and the low voltage, And is maintained at a low voltage state during a part of the threshold voltage detection preparation period, is maintained at an intermediate voltage from a remaining part of the threshold voltage detection period to a real data input period, and is maintained at a high voltage during the light emission period; The second driving power source is a direct current signal maintained at a low voltage state for all periods; The control signal is maintained at a high voltage (H) during a portion of the threshold voltage detection period and is maintained at a low voltage during the remaining period; The scan signal is maintained at a high voltage during a portion of the first initialization period, during the threshold voltage detection period, and during the second initialization period, and is maintained at a high voltage during some of the real data input periods; The real data voltage is maintained at a high voltage during the actual data input period and is maintained at a low voltage during the remaining period.

The discharge transistor is turned on / off in response to a discharge signal from the outside; The discharge signal is maintained at a high voltage for a certain period of the light emission period, and is maintained at a low voltage for a remaining period of time.

According to another aspect of the present invention, there is provided a method of driving an organic light emitting diode (OLED) display device, the method including driving a first driving power from a first driving power line and a second driving power from a second driving power line, A pixel circuit for outputting a driving current corresponding to an actual data voltage from the data line, and a light emitting element for emitting light by a driving current from the pixel circuit; The pixel circuit is turned on / off according to a scan signal from the scan line, and the switching transistor connects the data line and the first node when turned on; A control transistor which is turned on / off according to a control signal from the control line and connects between the second node and the third node when the transistor is turned on; And a driving transistor for turning on / off according to a potential of the second node, and for connecting the third node and the second driving power source to each other in a turn-on state, the driving method comprising: Initializing a voltage of the third node; Increasing a voltage at the second and third nodes; Detecting a threshold voltage of the driving transistor and storing the threshold voltage in the second storage capacitor; Initializing a voltage of the third node; Supplying the real data voltage to the data line; generating a driving current corresponding to the real data voltage and causing the light emitting element to emit light with the driving current; And discharging a voltage of the second node by connecting the scan line and the second node during a part of the light emission period corresponding to a period during which the scan line is maintained at a low voltage. .

The step of discharging the voltage of the second node is performed by a discharging transistor; The discharge transistor is turned on / off according to a discharge signal from the outside, and connects the second node and the scan electrode when the discharge transistor is turned on.

The discharge signal is maintained at a high voltage for a part of the light emission period, and is maintained at a low voltage for a remaining period of time.

The organic light emitting diode display device and the driving method thereof according to the present invention have the following effects.

According to the organic light emitting diode display device of the present invention, since the gate low voltage of the scan line is supplied to the gate electrode of the driving switching element for a predetermined period by the discharge transistor, the threshold voltage of the driving switching element is biased to one polarity .

1 is a view showing a light emitting display device according to the present invention.

1, a light emitting display according to the present invention includes m data lines DL1 to DLm (m is a natural number) to which a data voltage Data is supplied, n (n A first driving power VDD line (not shown) to which the first driving power VDD is supplied and a second driving power VSS are supplied to the scan lines SL1 to SLn, (Not shown), a control signal line (not shown) to which a control signal Vc is supplied, a display unit 100 including a plurality of pixel cells PXL, A scan driver 200 for driving each of the scan lines SL1 to SLn and a data driver 300 for supplying a data voltage Data to each of the data lines DL1 to DLm.

The scan driver 200 generates scan signals using start pulses and clock signals (not shown), and supplies the generated scan signals to the scan lines SL1 to SLn. The characteristics of these scan signals will be described in more detail later.

The data driver 300 generates a data voltage Data according to data control signals (not shown) and supplies the data voltage Data to the data lines DL1 to DLm. At this time, the data driver 300 supplies a data voltage Data for one horizontal line to each data line DL1 to DLm for every one horizontal period.

M pixel cells PXL in one horizontal line are commonly connected to one scan line and individually connected to m data lines. For example, the first to m-th pixel cells PXL arranged along the first horizontal line HL1 are commonly connected to the first scan line SL1, and the first to m-th data lines DL1 to DLn, DLm, respectively. In other words, the first pixel cell PXL of the first horizontal line HL1 is connected to the first data line DL1, the second pixel cell PXL of the first horizontal line HL1 is connected to the second data line DL1, The third pixel cell PXL of the first horizontal line HL1 is connected to the third data line DL3 and the mth pixel cell PXL of the first horizontal line HL1 is connected to the line DL2, And the pixel cell PXL is connected to the m-th data line DLm.

The first and second driving power supply lines, and the control line are commonly connected to all the pixel cells PXL.

Here, the structure of each pixel cell PXL will be described in more detail as follows.

2 is a diagram showing a circuit configuration of any pixel cell PXL in Fig.

The pixel cell PXL uses a plurality of transistors Tr_C, Tr_S, Tr_D and Tr_dis, a scan signal, a first driving power VDD and a second driving power VSS as shown in FIG. A pixel circuit PD for outputting a driving current corresponding to the data voltage Data from the data line and a light emitting element OLED for emitting light by the driving current from the pixel circuit PD.

The pixel circuit further includes first and second storage capacitors CPst1 and CPst2 and a variable capacitor CPv in addition to the above-described transistors. The transistors include a switching transistor Tr_S, a control transistor Tr_C, a driving transistor Tr_D, and a discharging transistor Tr_dis.

The switching transistor Tr_S is turned on / off according to the scan signal from the scan line, and connects the data line and the first node N1 at the turn-on time. To this end, the gate electrode of the switching transistor Tr_S is connected to the scan line, the source electrode (or drain electrode) is connected to the data line and the source electrode (or drain electrode) is connected to the first node N1 do.

The control transistor Tr_C is turned on / off according to a control signal from the control line, and connects the second node N2 and the third node N3 when turned on. To this end, the gate electrode of the control transistor Tr_C is connected to the control line, the drain electrode (or source electrode) is connected to the second node N2, and the source electrode (or drain electrode) .

The driving transistor Tr_D is turned on / off according to the potential of the second node N2, and connects the third node N3 and the second driving power source at the turn-on time. To this end, the gate electrode of the driving transistor Tr_D is connected to the second node N2, the drain electrode (or the source electrode) is connected to the third node N3, and the source electrode (or the drain electrode) And is connected to the second driving power supply line.

The discharge transistor Tr_dis is turned on for a part of the period during which the scan line is maintained at the low voltage to connect the scan line and the second node N2 to discharge the voltage of the second node N2 And the like. The discharge switching element is turned on / off according to the discharge signal Voff from the outside, and electrically connects the second node N2 to the scan electrode in the turn-on state.

The first storage capacitor CPst1 is connected between the first node N1 and the second node N2. The first storage capacitor CPst1 stably maintains the voltage of the second node N2 and prevents the voltage of the second node N2 from being mixed with the voltage of the first node N1.

The second storage capacitor CPst2 is connected between the first node N1 and the second driving power supply line. This second storage capacitor CPst2 prevents the voltage of the first node N1 from fluctuating when the switching transistor Tr_S is turned off to bring the first node N1 into a floating state.

The variable capacitor CPv is connected between the control line and the second node N2. This variable capacitor (CPv) is connected to the capacitance of the parasitic capacitor of each transistor And the parasitic capacitances (Cgs and Cgd) of the driving transistor (Tr_D) and the channel capacitance are offset by the capacitance of the first transistor (N1) during the compensation operation of the pixel, thereby preventing the voltage of the first node (N1) from fluctuating . And consequently contributes to improving the compensation characteristic.

The light emitting device OLED includes a cathode electrode connected to the third node N3, an anode electrode connected to the first driving power supply (VDD) line, and a light emitting layer formed between the cathode electrode and the anode electrode. The light emitting layer may be an organic light emitting layer or an inorganic light emitting layer. The light emitting element OLED emits light by the driving current from the driving transistor Tr_D.

The scan signal, the data voltage Data, the first drive power supply VDD, the second drive power supply VSS, and the control signal Vc, which are supplied to the pixel cell PXL constructed as above, will be described in detail. same.

FIG. 3 is a diagram showing various signal waveforms supplied to the display unit 100 including a plurality of pixel cells PXL having the structure as shown in FIG.

3, the driving of the light emitting display according to the present invention includes a first initializing period D1, a threshold voltage detecting preparation period D2, a threshold voltage detecting period D3, a second initializing period D1, (D4), an actual data input period (D5), and a light emission period (D6).

As shown in Fig. 3, the first driving power supply VDD is an AC signal having three different levels. That is, the first driving power supply VDD supplies a high voltage H having a relatively high voltage, a low voltage L having a relatively low voltage, and an intermediate voltage VL having a value between the high voltage H and the low voltage L M), and the first drive power supply VDD periodically shows the low voltage L, the intermediate voltage M, and the high voltage H.

The high voltage (H) can be set to about 15 [V], the intermediate voltage (M) to about 0 [V], and the low voltage (L) to about -10 [V] Can be varied.

The first driving power supply VDD is maintained in the low voltage state L during the first initialization period D1 and the partial voltage V2 during the threshold voltage detection preparation period D2, And is maintained at the intermediate voltage M until the data input period D5. Also, the first driving power supply VDD is maintained at the high voltage H during the light emission period D6.

The second driving power supply VSS is a DC signal maintained in a low voltage (L) state for all the periods as shown in Fig.

The control signal Vc is maintained at the high voltage H for a part of the threshold voltage detection period D3 and at the low voltage L for the remaining period as shown in Fig. The control signal Vc is different from the scan signals SC1 to SCn input to the respective horizontal lines and is supplied to all the pixel cells PXL of the display unit 100 as the first drive power supply VDD and the second drive power supply VSS ) That are commonly input to the input / output terminals.

As shown in FIG. 3, the discharge signal Voff is maintained at a high voltage (H) during a part of the light emission period (D6) and maintained at a low voltage (L) during the remaining period.

Each scan signal is maintained at a high voltage H during a partial period of the first initialization period D1, the threshold voltage detection period D3 and the second initialization period D4, D5). ≪ / RTI > That is, as shown in FIG. 3, the first scan signal SC1 is maintained at the high voltage H during the 10-1th period (T10-1) preceding the actual data input period D5, The signal SC2 is maintained at the high voltage H during the second 10-2 second period T10-2 of the real data input period D5 and the third scan signal SC3 is maintained in the real data input period (H) during the preceding 10 < -3 > period (T10-3).

The data voltage Data is maintained at the high voltage H during the first initialization period D1, the second initialization period D4 and the actual data input period D5 and is maintained at the low voltage L for the remaining period.

The magnitude of the high voltage H between the above-described signals may have the same value or may have different values. Similarly, the magnitudes of the undervoltage (L) between the signals may have the same value or may have different values.

The operation of the pixel cell PXL receiving such signals will be described in detail as follows.

4A to 4L are operation flowcharts for explaining the operation of the light emitting display according to the embodiment of the present invention.

Here, since the operation of all the pixel cells PXL is the same, the operation of the first pixel cell PXL connected to the first scan line SL1 and the first data line DL1 will be exemplarily described.

The operation of the first period T1 will be described with reference to FIGS. 4A and 3 as follows.

In the first period T1, as shown in FIG. 3, only the data voltage Data is in the high voltage H state and the first driving power VDD, the second driving power VSS, the control signal Vc, , And the scan signal are all in the low voltage (L) state. The data voltage Data is supplied to the first data line DL1 to charge the first data line DL1 at a high voltage H, as shown in FIG. 4A. In this first period T1, all the transistors and the light emitting element OLED are both turned off.

The first data line DL1 is supplied with data of the high voltage H to the first data line DL1 during the first period T1 before the switching transistor Tr_S is turned on, And is sufficiently charged to the target voltage in the second period T2.

On the other hand, since the first driving power supply VDD is maintained at a sufficiently low voltage L in the period immediately preceding the first period T1, the third node N3 in this period and the first period T1 Is very low. That is, the first driving power supply VDD is driven by the low voltage L due to the parasitic capacitor of the light emitting device OLED formed between the first power supply line and the third node N3 to which the first driving power supply VDD is supplied, The voltage of the third node N3 is also lowered.

The operation of the second period T2 will be described with reference to FIGS. 4B and 3 as follows.

In the second period T2, as shown in FIG. 3, the data voltage Data and all of the scan signals are in a high voltage (H) state, and the first drive power VDD, the second drive power VSS, The signal Vc is in a low voltage (L) state. That is, in the second period T2, the scan signals are changed from a low voltage (L) to a high voltage (H).

All the scan signals including the first scan signal SC1 are in a high voltage state and therefore the switching transistor Tr_S receiving the first scan signal SC1 through the gate electrode Turn on. Then, the data voltage Data (data voltage Data in a high voltage (H) state) from the first data line DL1 is supplied to the first node N1 through the turned-on switching transistor Tr_S do. Accordingly, the first node N1 is charged to a high voltage (H) state. At this time, the voltage of the second node N2 is raised by the first storage capacitor CPst1 connected between the first node N1 and the second node N2. Accordingly, the driving transistor Tr_D connected to the second node N2 through the gate electrode is turned on. Then, the second driving power supply VSS in the low voltage (L) state is supplied to the third node N3 through the turn-on driving transistor Tr_D. Thus, the third node N3 is initialized.

The operation of the third period T3 will be described with reference to FIG. 4C and FIG.

3, all of the scan signals are in a high voltage (H) state, and the data voltage Data, the first driving power VDD, the second driving power VSS, The signal Vc, and the scan signal are in a low voltage (L) state. That is, the data voltage Data is changed from the high voltage H to the low voltage L in the third period T3.

Since all the scan signals including the first scan signal SC1 are in a high voltage H state, the switching transistor Tr_S maintains the turn-on state as shown in FIG. 4C. The data voltage Data (data voltage Data in a low voltage (L) state) from the first data line DL1 is supplied to the first node N1 through the turned-on switching transistor Tr_S. Accordingly, the first node N1 is discharged to a low voltage (L) state. At this time, the voltage of the second node N2 is also lowered by the first storage capacitor CPst1 connected between the first node N1 and the second node N2. Thus, the driving transistor Tr_D connected to the second node N2 through the gate electrode is turned off.

Thus, during the first initialization period D1 including the first to third periods T3, the third node N3 is initialized to the low voltage L. That is, the third node N3 is initialized to the second driving power source VSS. The second driving power source VSS is set to a voltage of about 0 V so that the third node N3 rises from a negative voltage to a voltage of 0 [V].

The operation of the fourth period T4 will be described with reference to FIGS. 4D and 3 as follows.

In the fourth period T4, as shown in FIG. 3, the second driving power VSS, the control signal Vc, all the scan signals and the data voltage Data are in the low voltage L state, The power supply voltage VDD is changed from the low voltage L to the intermediate voltage M.

All of the scan signals including the first scan signal SC1 are in the low voltage state, so that the switching transistor Tr_S is turned off as shown in FIG. 4D. Thus, the first node N1 is brought into a floating state.

On the other hand, as the first driving power supply VDD rises from the low voltage L to the intermediate voltage M, the voltage of the third node N3 also rises. That is, the voltage of the third node N3 is raised by the parasitic capacitor of the light emitting device OLED formed between the first power supply line to which the first driving power supply VDD is supplied and the third node N3. At this time, a voltage obtained by subtracting the threshold voltage (Vth) of the light emitting device (OLED) from the first driving power supply (VDD) in a high voltage (H) state is applied to the third node (N3).

The third node N3 is a drain electrode of the driving transistor Tr_D and the voltage of the gate electrode of the driving transistor Tr_D and the voltage of the drain electrode must be increased before the threshold voltage of the driving transistor Tr_D (Vth). Therefore, by increasing the size of the first driving power supply VDD from the low voltage L to the intermediate voltage M during the fourth period T4, which is the threshold voltage detection preparation period D2, The voltage of the drain electrode can be raised.

Here, when the voltage of the drain electrode of the driving transistor Tr_D slightly increases in a state in which the first node N1 is floating, the voltage of the gate electrode of the driving transistor Tr_D It may increase slightly. This coupling phenomenon is caused by a parasitic capacitor formed between the gate electrode and the drain electrode of the driving transistor Tr_D.

Thus, the voltages of the second and third nodes N3 are raised in the fourth period T4.

The operation of the fifth period T5 will be described with reference to FIGS. 4E and 3 as follows.

In the fifth period T5, as shown in FIG. 3, the first driving power supply VDD is maintained in the intermediate voltage M state and the second driving power VSS, the control signal Vc, All the scan signals are changed from the low voltage L to the high voltage H while the data Data is maintained in the low voltage L state.

As the first scan signal SC1 rises to the high voltage H, the switching transistor Tr_S is turned on, as shown in Fig. 4E. Then, the data voltage Data (data voltage Data in a low voltage (L) state) from the first data line DL1 is supplied to the first node N1 through the turned-on switching transistor Tr_S do. Since this first node N1 has been held in a state of being in a low voltage (L) state as a data voltage Data in a floating state until the previous period, N1 and the potential of the second node N2 do not change.

The operation of the sixth period T6 will be described with reference to FIG. 4F and FIG.

In the sixth period T6, the first driving power supply VDD is maintained at the intermediate voltage M state and the second driving power supply VSS and the data voltage Data are at the low voltage L) state, and all the scan signals are maintained in the high voltage (H) state, while the control signal Vc is changed from the low voltage (L) to the high voltage (H).

As the control signal Vc rises to the high voltage H, the control transistor Tr_C is turned on, as shown in Fig. 4F. Then, the second node N2 and the third node N3 are short-circuited through the turn-on control transistor Tr_C, so that the gate electrode and the drain electrode of the driving transistor Tr_D are short-circuited to each other. Accordingly, the voltage of the second node N2 and the voltage of the third node N3 are mixed with each other, and the mixed voltage is charged to the second and third nodes N3 with the same value. This mixed voltage must be set to be higher than the threshold voltage Vth of the driving transistor Tr_D. To this end, the voltage of the second node N2 and the voltage of the third node N3 in the previous period should be set to the threshold voltage Vth Is set to be larger than the pressure (Vth).

The driving transistor Tr_D having the gate electrode and the drain electrode shorted to each other is turned on to perform the same operation as the diode. At this time, the mixed voltage gradually decreases toward the threshold voltage (Vth) of the driving transistor (Tr_D). When the mixed voltage becomes equal to the threshold voltage (Vth), the driving transistor (Tr_D) - Off. As a result, the threshold voltage (Vth) of the driving transistor (Tr_D) is stored in the second and third node (N3) as soon as the driving transistor (Tr_D) is turned off.

As described above, the threshold voltage Vth of the driving transistor Tr_D is stored in the second and third nodes N3 during the threshold voltage detection period D3 including the sixth period T6. During this threshold voltage detection period, the threshold voltage Vth of the corresponding driver transistor Tr_D is stored in each of the second and third nodes N3 of all the pixel cells PXL. The characteristics between the driving transistors Tr_D provided in the respective pixel cells PXL may be different from each other depending on the manufacturing environment thereof and therefore the threshold voltage Vth (Vth) stored in the second and third nodes N3 of each pixel cell PXL Vth) may be different from each other.

Referring to FIG. 4G and FIG. 3, the operation of the seventh period T7 will be described below.

In the seventh period T7, the first drive power supply VDD is maintained at the intermediate voltage M state and the second drive power supply VSS and the data voltage Data are maintained at the low voltage L and the control signal Vc is changed from the high voltage H to the low voltage L while all the scan signals are maintained in the high voltage H state.

As the control signal Vc is lowered to the low voltage L, the control transistor Tr_C is turned off as shown in Fig. 4G. The threshold voltage Vth of the driving transistor Tr_D is stored in the second and third nodes N3 in the seventh period T7.

The operation of the eighth period T8 will be described with reference to FIGS. 4H and 3 as follows.

In the eighth period T8, the first driving power supply VDD is maintained at the intermediate voltage M state and the second driving power supply VSS and the control signal Vc are maintained at the low voltage L and the data voltage Data is changed from the low voltage L to the high voltage H while all the scan signals are maintained in the high voltage H state.

As this data voltage Data rises to the high voltage H, both the voltage of the first node N1 and the voltage of the second node N2 are raised. Accordingly, the driving transistor Tr_D is turned on, and the second driving power supply VSS in the low voltage (L) state is supplied to the third node N3 through the turned-on driving transistor Tr_D . Thus, all the third nodes N3 of all the pixel cells PXL are initialized to the same voltage value.

The eighth period T8 is a period for initializing the third node N3 in advance in order to prepare for driving the light emitting device OLED by inputting real data.

As described above, since the threshold voltage Vth of the driving transistor Tr_D of each pixel cell PXL may be different from each other, the voltage value of the third node N3 in which the threshold voltage Vth is stored is smaller than the voltage value of each pixel Cell (PXL). Therefore, by supplying the data of the high voltage (H) state to all the pixel cells PXL in the eighth period T8, all the third nodes N3 in all the pixel cells PXL are supplied with the same second driving power VSS ).

The operation of the ninth period T9 will be described with reference to FIGS. 4I and 3 as follows.

In the ninth period T9, the first drive power supply VDD is maintained at the intermediate voltage M state and the second drive power supply VSS and the control signal Vc are maintained at the low voltage L and the data voltage Data is changed from the high voltage H to the low voltage L while all the scan signals are maintained in the high voltage H state.

As the data voltage Data is lowered to the low voltage L, both the voltage of the first node N1 and the voltage of the second node N2 are lowered. Then, the second node N2 returns to the previously set threshold voltage (Vth) value. Thus, the driving transistor Tr_D is turned off. As a result, the third node N3 is initialized to the second driving power source VSS, and the second node N2 stores the threshold voltage Vth.

The operation of the tenth period T10 will be described with reference to FIG. 4J and FIG.

In the tenth period T10, the first drive power supply VDD is maintained at the intermediate voltage M state and the second drive power supply VSS and the control signal Vc are maintained at the low voltage L) state.

All of the scan signals are maintained in a high voltage (H) state for a predetermined period in turn. That is, the tenth period T10 is an actual data input period D5, which includes the tenth through tenth-nth periods T10-1 through T10-n. During the 10th to 10th-nth periods T10-1 to T10-n, the first to nth scan signals SC1 to SCn are maintained in the high voltage state for the corresponding period in turn. The data supplied to the m data lines during the tenth period T10 is actual data to be actually expressed and each of the real data is divided into 0 [V] to several tens [ V] between the high voltage and the high voltage.

During the 10-1th period T10-1, only the first one of the plurality of scan lines SL1 is driven, and during the 10-2 second period T10-2, the second scan Only the line SL2 is driven and only the third one of the plurality of scan lines is driven during the 10 < th > -3 period (T10-3) Only the nth scan line SLn among the plurality of scan lines is driven.

When each scan line is driven, all the pixel cells PXL of one horizontal line connected to the corresponding scan line are driven. Accordingly, when one scan line is driven, the real data is supplied to the pixel cells PXL of one horizontal line connected to the scan line.

The process of supplying the real data will be described with reference to the first pixel cell PXL as an example.

The first pixel cell PXL is supplied with data in a high voltage (H) state during the 10-1th period (T10-1). This data is supplied to the first node N1 through the first data line DL1. Then, the voltage of the first node N1 rises to the data voltage Data, and the voltage of the second node N2 rises as the voltage of the first node N1 rises. That is, the voltage of the second node N2 is raised by the first storage capacitor CPst1 connected between the first node N1 and the second node N2. At this time, the voltage of the second node N2 is further increased by the voltage inputted to the first node N1.

This will be described in more detail as follows. Here, for convenience of explanation, the drawing number of the real data supplied to the first node N1 is represented by Vdata.

That is, since the threshold voltage Vth of the driving transistor Tr_D detected during the above-described threshold voltage detection period D3 is stored in the second node N2, The voltage of the second node N2 is defined as the sum of the actual data and the threshold voltage Vth. However, since the voltage of the second node N2 is affected by various parasitic capacitors and the first storage capacitor CPst1 present in the driving transistor Tr_D, the voltage of the second node N2 is ≪ / RTI >

In the first equation, Vn2 denotes the voltage of the second node N2, the first Cst1 denotes the capacitance of the first storage capacitor CPst1, the Cgs denotes the gate electrode of the driving transistor Tr_D, Denotes the capacitance of the parasitic capacitor Cgs existing between the electrodes, and Cgd denotes the capacitance of the parasitic capacitor Cgd existing between the gate electrode and the drain electrode of the driving transistor Tr_D.

The magnitude of the second node N2 is different from the compensation value (threshold voltage Vth + actual data voltage Data) originally intended by the parasitic capacitors Cgs and Cgd to compensate the threshold voltage Vth The capability may be somewhat reduced, but this problem can be overcome by a variable capacitor (CPv). The variable capacitor (CPv) is capacitively adjusted and fixed by the manufacturer or designer in the manufacturing or design stage. That is, the variable capacitor CPv is designed to have a proper size so as to compensate for the voltage deviation of the second node N2 generated according to the magnitude of the parasitic capacitance generated by the above-mentioned parasitic capacitors Cgs and Cgd. And its own compensation capacity is determined. Specifically, the variable capacitor (CPv) minimizes the parasitic capacitance by offsetting the parasitic capacitance to the opposite compensation capacitance.

The voltage corresponding to the sum of the threshold voltage Vth of the driving transistor Tr_D and the actual data voltage Data is applied to each second node N2 of all the pixel cells PXL during the real data input period D5. Are sequentially stored in units of one horizontal line. That is, in the 10-1th period T10-1, each of the m pixel cells PXL arranged along the first horizontal line HL1 is supplied with a driving voltage (driving transistor The mth pixel cell PXL arranged along the second horizontal line HL2 is stored in the 10-2 second period T10-2. Each of the m pixel cells PXL stores the driving voltage in its second node N2 and then in the 10 < th > -3 period T10-3, m pixel cells PXL arranged along the third horizontal line HL3 (N-1) -th horizontal line HLn, the driving voltage is stored in its own second node N2, and in the 10-n period T10-n, m pixel cells PXL Each store a driving voltage at its second node N2. Thus, the driving transistors Tr_D of all the pixel cells PXL are sequentially turned on in units of horizontal lines. At this time, since the first driving power supply VDD is in a low voltage (L) state, no driving current is generated even if the driving transistor Tr_D is turned on. Therefore, in the tenth period T10, the light emitting device OLED does not emit light.

The operation of the eleventh period T11 will be described with reference to FIGS. 4K and 3 as follows.

In the eleventh period T11, the second driving power VSS, the control signal Vc, and all the scan signals are maintained at the low voltage L, as shown in FIG. 3, Is changed from the high voltage (H) to the low voltage (L). Particularly, the eleventh period T11 is a light emitting period D6 for emitting the light emitting devices OLED of all the pixel cells PXL. For this purpose, the first driving power source VDD is turned on during the eleventh period T11, Is changed from the intermediate voltage (M) to the high voltage (H).

As the first driving power supply VDD rises to the high voltage H, the driving transistor Tr_D turned on in all the pixel cells PXL flows a driving current through the drain electrode and the source electrode of the driving transistor Tr_D. As each driving current is transmitted to the cathode electrode through the anode electrode of each light emitting device OLED, the light emitting devices OLED of all the pixel cells PXL emit light with luminance corresponding to the magnitude of the driving current supplied thereto.

At this time, the driving current supplied to each light emitting device OLED is defined by the following second equation.

Here, I _OLED denotes a current flowing from the drain electrode of the driving transistor Tr_D toward the source electrode, Vgs denotes a gate-source electrode voltage of the driving transistor Tr_D, and? Denotes a constant value it means.

Meanwhile, as shown in FIG. 4L and FIG. 3, the discharge transistor Tr_dis is turned on as the discharge signal Voff is maintained at the high voltage H for a part of the light emission period D6. Then, the second node N2 and the scan line are electrically connected to each other by the turn-on discharge transistor Tr_dis, and thus the gate electrode of the second node N2, that is, the discharge transistor Tr_dis The data voltage that has been applied is discharged. Therefore, the voltage of the second node N2 is changed from a positive polarity to a negative polarity, and the discharging transistor Tr_dis is turned off.

The threshold voltage detection preparation period D2, the threshold voltage detection period D3, the second initialization period D4, the actual data input period D5, and the light emission period D6 Is repeatedly changed so that the voltage of the second node N2 periodically changes from the positive polarity to the negative polarity, deterioration of the discharge transistor Tr_dis is prevented.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

1 shows a light-emitting display device according to the present invention;

Fig. 2 is a diagram showing a circuit configuration of any pixel cell in Fig. 1

FIG. 3 is a view showing various signal waveforms supplied to a display unit including a plurality of pixel cells having the structure as shown in FIG. 2

4A to 4L are flow charts for explaining the operation of the light emitting display according to the embodiment of the present invention.

Claims (8)

A pixel circuit for outputting a driving current corresponding to an actual data voltage from a data line using a first driving power from a first driving power supply line and a second driving power from a second driving power supply line; And a light emitting element which emits light by a driving current of the light emitting element; The pixel circuit includes: A switching transistor that is turned on / off according to a scan signal from the scan line and connects the data line and the first node at the turn-on time; A control transistor which is turned on / off according to a control signal from the control line and connects between the second node and the third node when the transistor is turned on; A driving transistor which is turned on / off according to a potential of the second node and connects the third node and the second driving power source when the first node is turned on; A discharging transistor connected between the scan line and the second node to discharge a voltage of the second node during a period during which the scan line is maintained at a low voltage; And And a first storage capacitor connected between the first node and the second node. The method according to claim 1, A second storage capacitor connected between the second node and the second driving power supply line; And And a variable capacitor connected between the control line and a second node. 3. The method of claim 2, Wherein the pixel circuit and the light emitting element detect a threshold voltage of the driving transistor by a first initializing period for initializing a voltage of the third node, a threshold voltage detecting preparation period for increasing a voltage of the second and third nodes, A second initialization period for initializing the voltage of the third node, and a real data input period for supplying the actual data voltage to the data line, And a light emitting period for emitting the light emitting element with the driving current; Wherein a part of the period during which the scan line is maintained at a low voltage corresponds to a part of the light emission period. The method of claim 3, The first drive power source is a signal having a high voltage having a relatively high voltage, a low voltage having a relatively low voltage, and an intermediate voltage having a value between the high voltage and the low voltage, Maintained at a low voltage state during a part of the threshold voltage detection preparation period, maintained at an intermediate voltage from the remaining part of the threshold voltage detection period to the real data input period, and maintained at a high voltage during the light emission period; The second driving power source is a direct current signal maintained at a low voltage state for all periods; The control signal is maintained at a high voltage (H) during a portion of the threshold voltage detection period and is maintained at a low voltage during the remaining period; The scan signal is maintained at a high voltage during a portion of the first initialization period, during the threshold voltage detection period, and during the second initialization period, and is maintained at a high voltage during some of the real data input periods; And, Wherein the real data voltage is maintained at a high voltage during the real data input period and is maintained at a low voltage during the remaining period. 5. The method of claim 4, The discharge transistor is turned on / off in response to a discharge signal from the outside; And, Wherein the discharge signal is maintained at a high voltage for a part of the light emission period, and is maintained at a low voltage for a remaining period of time. A pixel circuit for outputting a driving current corresponding to an actual data voltage from a data line using a first driving power from a first driving power supply line and a second driving power from a second driving power supply line; And a light emitting element which emits light by a driving current of the light emitting element; The pixel circuit is turned on / off according to a scan signal from the scan line, and the switching transistor connects the data line and the first node when turned on; A control transistor which is turned on / off according to a control signal from the control line and connects between the second node and the third node when the transistor is turned on; A driving transistor which is turned on / off according to a potential of the second node and connects the third node and the second driving power source when the first node is turned on; A first storage capacitor connected between the first node and a second node; And a second storage capacitor connected between the second node and the second driving power supply line, the driving method comprising: Initializing a voltage of the third node; Increasing a voltage at the second and third nodes; Detecting a threshold voltage of the driving transistor and storing the threshold voltage in the second storage capacitor; Initializing a voltage of the third node; Supplying the real data voltage to the data line; Generating a driving current corresponding to the actual data voltage and causing the light emitting element to emit light with the driving current; And And discharging a voltage of the second node by connecting the scan line and the second node during a part of the emission period corresponding to a period during which the scan line is maintained at a low voltage, A method of driving a diode display device. The method according to claim 6, The step of discharging the voltage of the second node is performed by a discharging transistor; And, Wherein the discharge transistor is turned on / off according to a discharge signal from the outside, and connects the second node and the scan electrode when the scan electrode is turned on. 8. The method of claim 7, Wherein the discharge signal is maintained at a high voltage for a part of the light emission period, and is maintained at a low voltage for a remaining period of time.

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