KR20100005600A

KR20100005600A - Method for fabricating semiconductor device

Info

Publication number: KR20100005600A
Application number: KR1020080065695A
Authority: KR
Inventors: 송주경
Original assignee: 주식회사 하이닉스반도체
Priority date: 2008-07-07
Filing date: 2008-07-07
Publication date: 2010-01-15

Abstract

A method of manufacturing a semiconductor device of the present invention is a pattern formation method of a semiconductor device having a gate pattern disposed in a main chip region and a test pattern disposed in a peripheral circuit region, wherein the gate pattern is formed to have a uniform length in the main chip. The test pattern is arranged to have a uniform length in the peripheral circuit area, and the dummy test pattern is arranged so that the test pattern has the same peripheral environment as the gate pattern of the main chip.

Description

Method for fabricating semiconductor device {Method for fabricating semiconductor device}

The present invention relates to a method of manufacturing a semiconductor device, and in particular, the characteristics of the device tested by the test pattern is minimized by minimizing the difference between the critical dimension (hereinafter, referred to as CD) of the gate pattern and the test pattern of the main chip. It relates to a method for manufacturing a semiconductor device that can represent the characteristics for.

Recently, as the development of semiconductor manufacturing technology and the application field of memory devices are expanded, there is an urgent need to develop a large-capacity memory device in which the integration degree is improved while the electrical characteristics thereof are not degraded. In order to meet these demands, as the design rules of semiconductor devices become smaller, more critical control of the pattern line width and process margin is required. Even in the case of the gate pattern, a small variation in the pattern line width (CD), which has not been a problem under conventional loose conditions, can greatly affect the device characteristics. It can cause problems.

In general, a semiconductor device includes a test pattern in order to test whether there is an abnormality of a device generated during a manufacturing process and to evaluate process characteristics. The test pattern analyzes the electrical characteristics of each part of the semiconductor device to detect abnormalities in the manufacturing process of the semiconductor device, and evaluates the process characteristics to secure process limits and process margins. The test pattern is formed in a region other than the cell region in the same manner as the element formed in the cell region, but has a different electrical characteristic from the element formed in the cell region because it is formed in a region having a lower integration degree than the cell region.

Among the various patterns formed to manufacture the semiconductor device, the line width CD of the gate pattern becomes an important factor for determining the characteristics of the semiconductor device. Therefore, keeping CD of the gate pattern uniform in a chip has become a very important issue. However, even when the optical proximity correction (OPC) is performed and the gate patterns having the same left and right duty ratios are exposed in the same field, that is, the same exposure shot, the length and the surrounding environment of the gate pattern Depending on the difference, the CD of the pattern is changed. In particular, a large variation in CD causes a large difference in CD in the test pattern inserted under the same conditions as the cell transistors of the main chip. As a result, there is a problem in that accurate characterization of the device is not performed.

The technical problem to be achieved by the present invention is to provide a method for manufacturing a semiconductor device in which the characteristics of the device tested by the test pattern can represent the characteristics of the main chip by minimizing the CD difference between the main pattern and the test pattern. have.

In order to achieve the above technical problem, a method of manufacturing a semiconductor device according to the present invention includes a gate pattern disposed in a main chip region and a test pattern disposed in a peripheral circuit region. The gate pattern is arranged to have a uniform length in the circuit, the test pattern is arranged to have a uniform length in the peripheral circuit region, and the dummy test pattern is arranged so that the test pattern has the same surrounding environment as the gate pattern of the main chip. It is done.

The dummy test pattern may be disposed such that the pattern density around the test pattern is the same as the pattern density around the gate pattern.

According to the method of manufacturing a semiconductor device according to the present invention, the length of the gate of the main pattern region is extended and unified, and the length of the test pattern is extended and unified like the main pattern, and the test pattern is formed to have the same peripheral environment as the main pattern. By placing dummy test patterns in the periphery, CD uniformity (uinofrmity) can be improved to minimize CD differences between the main chip and the test pattern. Therefore, the transistor characteristics tested by the test pattern may represent the characteristics of the main chip, so that accurate device characteristics may be predicted to manufacture devices having better characteristics.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

In the present invention, by identifying the cause or condition of the CD difference in the gate pattern and the test pattern of the main chip, and by minimizing the CD difference between the gate pattern and the test pattern, the characteristics of the test pattern to represent the characteristics of the gate pattern of the device It suggests ways to effectively characterize and present conditions of manufacturing process.

1 is a map showing a distribution of a pattern CD (Develop Inspection CD) measured after the photoresist development step to form a gate pattern having a target CD of 130 nm, and FIG. 2A is a DICD of a main pattern. 2B is a graph illustrating DICD for each position of a test pattern.

In the drawings, reference numerals "A", "B", and "C" denote areas where test patterns are arranged, and reference numeral "110" denotes a length of a gate of 2.85 占 퐉, and "120" denotes a gate length of 5.65 占 퐉. "130" indicates the case where the gate length is 3.65 mu m, and "140" indicates the case where the gate length is 5. 85 mu m, respectively. The layout of the main pattern and the test pattern for forming the gate of the cell transistor are the same, and the optical proximity correction (OPC) is also performed the same.

1 to 2B, CDs of the main pattern and the test pattern are different depending on the length of the gate. Comparing the average of the DICD, the DICD of the test pattern is about 3.9 μm larger than the main pattern.

3 is a map showing the distribution of Final Inspection CD (FICD) measured after forming a gate pattern having a target CD of 130 nm, FIG. 4A is a graph showing the FICD of the main pattern, and FIG. It is a graph showing FICD by location.

In FIG. 4A, the part indicated by an ellipse represents the FICD of the main pattern at the center of the chip. The uniformity of the FICD was degraded in both the main pattern and the test pattern, and in the case of the main pattern, the FICD was largely formed at the center of the chip. The FICD variability of the test pattern along the length of the gate shows the same tendency as for the DICD.

As described above, the CD of the gate pattern, which is an important factor in the characteristics of the device, is exposed to the same layout in the same field, but the CD is different due to the difference in the length of the gate and the surrounding environment. This CD variation is particularly large in the test pattern, which causes a problem that accurate characterization of the device is not performed. The present invention proposes a method of minimizing the CD difference between the main pattern and the test pattern by minimizing the difference in gate length causing the CD difference in the main pattern and the test pattern and the difference in the surrounding environment in which the pattern is disposed.

5A through 6C are views illustrating a method of forming a gate of a semiconductor device according to the present invention.

First, FIG. 5A is a plan view showing the pattern arrangement of the main pattern region before applying the method of the present invention, and FIG. 5B is a plan view showing the pattern arrangement of the main pattern region to which the method of the present invention is applied.

In the case of the conventional pattern arrangement shown in FIG. 5A, the lengths of the gate patterns 210 are different from each other without being uniform. When the lengths of the gate patterns are different from each other, when the DICD and the FICD are measured, a difference occurs depending on the length of the gate pattern, and thus the CD uniformity is not excellent.

In the pattern arrangement of the present invention illustrated in FIG. 5B, the length of the gate pattern 220 is expanded while the length of the gate pattern 220 is unified. Dummy patterns 230 are disposed in a region where the gate pattern 220 is not disposed to have a similar pattern density with a region where the gate pattern 220 is disposed. As such, if the lengths of the main gate patterns are unified to each other and the lengths of the patterns are expanded, the patterns have a more uniform pattern arrangement in terms of regularity of the pattern array. Can be improved.

On the other hand, even in the test pattern, CD uniformity can be further improved by unifying and extending the pattern length. Further, when the arrangement is made to have the same peripheral environment as the gate pattern disposed on the buried chip, it is possible to minimize the CD difference from the gate pattern.

6A to 6C are diagrams illustrating a pattern arrangement process of a test pattern region.

Referring to the arrangement of the conventional test pattern 310 prior to applying the method of the present invention shown in FIG. 6A, the environment, such as the density of the surrounding pattern, in which the test pattern 310 is disposed, is connected to the main gate pattern (220 of FIG. 5B). It is arranged differently. As mentioned, since the CD difference between the main gate pattern and the test pattern is also caused by the difference in the surrounding environment of the main gate pattern and the test pattern, the present invention makes the surrounding environment in which the test pattern is disposed similar to the main gate pattern. .

6B and 6C, first, the length of the test pattern is unified and extended like the main gate pattern (220 of FIG. 5B). The length of the test pattern is unified and extended like the main pattern, and then a peripheral environment similar to the main gate pattern (220 in FIG. 5B) is formed around the test pattern 320 having a uniform length as shown in FIG. 6C. The dummy test pattern 330 is disposed to have.

As such, when the length of the gate is extended and unified in the main pattern region, the length of the test pattern is extended and unified like the main pattern, and the dummy test pattern is disposed around the test pattern to have the same surrounding environment as the main pattern. In addition, it is possible to improve the difference according to the position of the test pattern in DICD and FICD, and to minimize the CD difference between the main gate pattern and the test pattern.

According to the present invention, the CD uniformity of the gate pattern and the test pattern can be improved by unifying and extending the length of the pattern, and by placing the dummy test pattern to have the same peripheral environment as the gate pattern of the main chip, between the gate pattern and the test pattern. CD differences can be minimized. Therefore, the transistor characteristics tested by the test pattern may represent the characteristics of the main chip, thereby making it possible to manufacture the device having better characteristics by predicting accurate device characteristics.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

FIG. 1 is a map showing a distribution of pattern CD (DICD) measured after the photoresist development step to form a gate pattern having a target CD of 130 nm.

FIG. 2A is a graph illustrating DICD of a main pattern, and FIG. 2B is a graph illustrating DICD for each position of a test pattern.

3 is a map showing a distribution of FICDs measured after forming a gate pattern having a target CD of 130 nm.

4A is a graph showing the FICD of the main pattern, and FIG. 4B is a graph showing the FICD for each position of the test pattern.

5A to 6C are diagrams for describing a gate forming method of a semiconductor device according to the present invention.

Claims

In the pattern forming method of a semiconductor device having a gate pattern disposed in the main chip region and a test pattern disposed in the peripheral circuit region,

Disposing the gate pattern to have a uniform length in the main chip,

And arranging the test pattern to have a uniform length in the peripheral circuit region, and disposing a dummy test pattern such that the test pattern has the same peripheral environment as the gate pattern of the main chip.

The method of claim 1,

The dummy test pattern may be arranged such that the pattern density around the test pattern is the same as the pattern density around the gate pattern.