KR20100005448A - Magnetic ram and manufacturing method of the same - Google Patents

Abstract

PURPOSE: A magnetic RAM and a manufacturing method thereof are provided to increase a size of cell arrangement by reducing the resistance difference due to a source line connected to each cell. CONSTITUTION: A magnetic tunnel junction(MTJ) is formed between source lines(SL) and bit lines. The magnetic tunnel junction changes the magnetization direction according to the direction of the current flowing between source lines and data lines. Metal lines(ML) are extended to the same direction as the source lines and are formed in the different layer from the source lines. Metal line contacts(MLC) electrically connect the corresponding source line and the metal line at a plurality of points.

Description

Magnetic RAM and manufacturing method of the same

The present invention relates to an MRAM (Magnetic RAM), and more particularly, by reducing the resistance difference caused by the source line to each cell in the MRAM that stores different data according to the current direction between the source line and the bit line. The present invention relates to an MRAM capable of increasing a cell arrangement and a method of manufacturing the same.

As the demand for portable devices and communication devices soars, the need for nonvolatile and memory to overcome the limitations of volatile memory that loses data when power is cut off increases the need for memory. .

In order to satisfy this problem, magnetoresistive random access memory (MRAM) using a difference in magnetoresistance to a relative arrangement of magnetic poles has been developed.

MRAM is a type of memory that stores magnetic polarization in a thin film of magnetic material. A write / read operation is performed by changing or detecting magnetic polarization by a magnetic field generated by a combination of bit line current and word line current. .

In general, the MRAM stores data using a device using magnetic phenomena such as Giant Magneto Resistance (GMR) and Magnetic Tunnel Junction (MTJ) as a memory cell. In other words, MRAM is a method of implementing a memory device using a large magnetoresistance (GMR) phenomenon or spin polarization magnetic permeation phenomenon caused by the spin has a significant effect on the electron transfer phenomenon.

First, in the case of MRAM using a large magnetic resistance (GMR) phenomenon, a GMR magnetic memory device is implemented by using a phenomenon in which the resistance in the case where the spin directions are different in the two magnetic layers having a nonmagnetic layer between them is different.

In addition, the MRAM using the spin polarization magnetic permeation phenomenon is a magnetic permeation junction memory device using a phenomenon that current transmission occurs much better than the case where the spin direction is the same in two magnetic layers having an insulating layer interposed therebetween.

Recently, an MRAM has been developed that uses a spin-transfer function to write data according to the resistance difference by changing the magnetization of the MTJ according to the direction of the current by applying a current to the MTJ in both directions.

1 is a circuit diagram briefly illustrating a circuit configuration of a basic unit cell of an MRAM using a conventional spin movement function.

The unit cell of the MRAM (hereinafter, referred to as an MRAM cell) includes one transistor 10 and one MTJ 20 connected between two metal lines, a bit line BL and a source line SL.

The transistor 10 is connected between the source line SL and the MTJ 20 and is turned on according to the voltage applied through the word line WL during read / write of data, and is connected to the source line SL through the MTJ 20. The current flows between the bit lines BL.

The MTJ 20 is connected between the source / drain regions of the transistor 10 and the bit line BL and has two magnetic layers 22 and 26 and a tunnel barrier 24 therebetween. Is formed. At this time, the lower layer of the tunnel barrier layer 24 is composed of a fixed magnetic layer 22 is fixed in the magnetization direction, the upper layer of the tunnel barrier layer 24 is free to change the magnetization direction in accordance with the direction of the current flowing through the MTJ (20) It is made of a magnetic layer 26.

In this case, the magnetization direction of the free magnetic layer 26 is fixed when the current flows from the source line SL toward the bit line BL, that is, when the current flows from the stator magnetic layer 22 to the free magnetic layer 26. The magnetic layer 22 is switched in anti-parallel with the magnetization direction. That is, high resistance is formed in the MTJ 20 and data "1" is stored in the corresponding cell.

On the other hand, when the current flows from the bit line BL toward the source line SL, that is, when the current flows from the free magnetic layer 26 to the pinned magnetic layer 22, the magnetization direction of the free magnetic layer 26 is fixed. It is switched in parallel with the magnetization direction of the magnetic layer 22. That is, a low resistance is formed in the MTJ 20 and data "0" is stored in the corresponding cell.

The method of reading data stored in the MTJ 20 is performed by detecting a difference in the amount of current flowing through the MTJ 20 according to the magnetization state of the MTJ 20 as in the related art.

In order to highly integrate such MRAM cells, it is necessary to increase the size of the cell array, that is, the cell array. However, when the arrangement of the cells is increased, the lengths of the metal lines, ie, the bit lines BL and the source lines SL, for signal transmission between the cells and the peripheral circuits are increased, and accordingly, the bit lines BL and the source lines SL are correspondingly increased. Also, since the resistance increases, there is a limit to growing the cell arrangement.

That is, as the size of the cell array increases, the lengths of the metal wires BL and SL to each cell vary according to the position of the cell, thereby changing the resistance of the metal wires, and thus the difference in the amount of current applied to the MTJ through such metal wires. This causes a disadvantage in writing or reading data to the MTJ.

The present invention improves the structure of the MRAM to increase the size of the cell array, thereby reducing the difference in the resistance of the source line for each cell irrespective of the position of the cells in the cell array to make it easier to grow the cell array of the MRAM have.

The magnetic RAM of the present invention comprises: a plurality of MTJs formed between source lines and bit lines and whose magnetization direction is changed according to a direction of a current flowing between the source lines and the bit lines; A plurality of metal lines extending in the same direction as the source lines and formed in different layers from the source lines; And a plurality of metal line contacts for electrically connecting the corresponding source line and the metal line at a plurality of points.

In the present invention, the metal line is formed on top of the source line to have a one-to-one correspondence with the source line, and the resistance value is made of copper smaller than the resistance value of the source line.

In the present invention, the metal line contacts are formed between the bit lines at regular intervals or between the bit lines at different intervals according to a distance from a peripheral circuit. In this case, the metal line contacts are formed on the active region between the bit lines or on the device isolation layer between the bit lines.

In the present invention, the bit line is not formed on the active region where the metal line contact is formed, and the MTJ is not formed on the active region where the metal line contact is formed. The source line is formed to have a width wider than a portion that is not connected to the metal line contact.

A method of manufacturing a magnetic RAM according to the present invention may include forming a source line on a semiconductor substrate including a cell transistor, the source line being connected to a source / drain region of the cell transistor and extending in a first direction; Forming a metal line contact on the source line; And forming a metal line connected to the metal line contact on the source line and extending in the first direction.

The forming of the source line may include forming a first interlayer insulating layer on the semiconductor substrate including the cell transistor; Selectively etching the first interlayer insulating layer until the source / drain regions are exposed to form a first contact hole; Forming a first contact plug to fill the first contact hole; Forming a first conductive film on the first interlayer insulating film having the first contact plug formed thereon; And patterning the first conductive layer to be connected to the first contact plug and extend in the first direction. In this case, the first conductive layer is formed of tungsten (W) or platinum (Pt).

In the present invention, the forming of the metal line contact may include forming a second interlayer insulating layer on the source line; Selectively etching the second interlayer insulating layer until the source line is exposed to form a second contact hole; Forming a second contact plug to fill the second contact hole; Patterning a second conductive film connected to the second contact plug on the second interlayer cutting film including the second contact plug; Forming a third interlayer insulating film over the second conductive film; Selectively etching the third interlayer insulating layer until the second conductive layer is exposed to form a third contact hole; And forming a third contact plug to fill the third contact hole. In this case, the metal line is formed of copper (Cu), and is formed wider than the source line on the source line so as to overlap the source line.

The present invention further forms a metal line having a smaller resistance than the source line in parallel with the source line, and then connects the metal line and the source line to supply current to the MTJ through the metal line, regardless of the position of each cell. By reducing the difference in resistance between the cells by each other can easily increase the size of the cell array of the memory device without affecting the operation characteristics of the device.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2 is a plan view showing a structure of a cell array region of an MRAM according to the present invention.

In the MRAM of the present invention, a metal line (eg, Cu) ML having a one-to-one correspondence with the source line SL on the source line SL and having a lower resistance than the source line SL is disposed in the same direction as the source line SL. It is formed to extend. At this time, the width of the metal line ML is formed wider than the width of the source line SL so that the source line SL overlaps inside the metal line ML.

The metal line ML and the source line SL are electrically connected to each other through the metal line contact MLC at regular intervals.

In order to connect the metal line ML and the source line SL, the present embodiment does not uniformly form all the bit lines BL at regular intervals, but instead of a predetermined number of bit lines (a few to several tens of bits). The metal line contact MLC is formed in the region without forming one bit line BL per line).

In FIG. 2, as an embodiment, one bit line is not formed in units of four bit lines. That is, four bit lines BL2 to BL5 are formed in succession, bit lines are not formed in the next active regions, and then four bit lines are continuously formed at regular intervals. As such, a pattern for preventing bit lines from being formed on the active region at regular intervals is performed throughout the cell array.

As such, in the present invention, a metal line ML having a lower resistance than the source line SL is further formed on the source line SL, and the bit line BL is not formed at regular intervals. Instead, the source line SL is formed. ) And a metal line contact (MLC) to electrically connect the metal line (ML).

That is, the reason why the bit lines BL are not formed at regular intervals as described above in the present invention is a space for connecting the source lines SL and the metal lines ML at regular intervals, that is, the metal line contacts MLC. This is to secure a space for forming.

In addition, a portion of the source line SL connected to the metal line contact MLC is wider than that of the portion of the source line SL, thereby increasing the process margin when forming the metal line contact MLC.

The MTJ is formed between the source / drain region of the active region 30 and the bit line BL. Therefore, no MTJ is formed in the active region where the bit line BL is not formed, that is, the active region where the metal line contact MLC is formed.

In the above-described configuration, when the current is to flow from the source line SL to the bit line BL, the metal circuit ML does not supply current only through the source line SL in the peripheral circuit not shown in the related art. ) Or supply current through both the source line SL and the metal line ML.

As described above, in the present invention, the current is supplied to the MTJ of the cell selected by the addressing to supply the current through the metal line ML having a small resistance value. Without this, the resistance difference between the cells by the source line SL is reduced. That is, the difference in resistance due to the source line SL is greatly reduced between a cell located close to the peripheral circuit (not shown) and a cell located far from the peripheral circuit (not shown). Therefore, even if the cell array is formed large for high integration, the resistance difference according to the position of the cell does not occur as in the prior art.

3 is a cross-sectional view illustrating a process cross section taken along the line AA ′ in FIG. 2.

The metal line ML is formed on the source line SL, and the two metal lines SL and ML are electrically connected to each other through the metal line contact MLC. The bit line BL and the MTJ are not formed on the active region where the metal line contact MLC is formed.

4A to 4C are cross-sectional views illustrating a method of manufacturing an MRAM having the structure of FIG. 3.

Referring to FIG. 4A, first, an isolation layer 40 defining an active region 30 is formed on a silicon substrate using, for example, a shallow trench isolation (STI) method.

Next, cell selection transistors having the gate electrode 34 and the source / drain regions 36 and 38 are formed on the active region 30 and the device isolation film 32 in the same manner as a conventional MOS transistor manufacturing method.

Referring to FIG. 4B, an interlayer insulating film 40 is formed by forming a silicon oxide film on a silicon substrate on which a cell select transistor is formed, for example, by using a CVD method.

Next, a contact hole is formed by selectively etching the interlayer insulating layer 40 until the source / drain region 38 is exposed using a photoresist pattern (not shown) defining a region where the contact plug 42 is to be formed. .

Next, the contact plug 42 electrically connected to the source / drain region 38 is formed by forming a conductive film filling the contact hole. Then, for example, a tungsten (W) film or a platinum (Pt) film is formed on the interlayer insulating film 40 including the contact plug 42 and then patterned to form a source / drain region 38 through the contact plug 42. Source line 44 is electrically connected.

Referring to FIG. 4C, after forming the interlayer insulating layer 46 on the resultant including the source line 44, the interlayer insulating layer 46 is selectively etched until the source line 44 is exposed, thereby source source 44. A contact plug 48 is formed to be connected to the contact plug.

Next, a conductive film 50 connected to the contact plug 48 is formed on the interlayer insulating film 46 including the contact plug 48 and then patterned.

Next, after the interlayer insulating film 52 is formed on the resultant including the patterned conductive film 50, the interlayer insulating film 52 is selectively etched until the conductive film 50 is exposed. The contact plug 54 to be connected is formed.

Next, a metal film connected to the contact plug 54 is formed on the interlayer insulating film 52 including the contact plug 54 and then patterned to form a metal line 56. At this time, the metal line 56 is formed of a metal having a lower resistance than the source line 44, for example, copper (Cu).

FIG. 5 is a cross-sectional view illustrating a process cross section taken along the line BB ′ in FIG. 2.

The source line SL and the MTJ are electrically connected to the source / drain regions on both sides of the word line WL. At this time, the stant magnetic layer of the MTJ is connected to the source / drain region and the free magnetic layer is connected to the bit line. Therefore, when a gate voltage is applied to a specific word line WL by addressing and the corresponding cell transistor is turned on, current flows between the source line SL and the bit line BL through the MTJ, and according to the direction of the current. Data "1" or "0" is stored in the.

6A to 6C are cross-sectional views illustrating a method of manufacturing an MRAM having the structure of FIG. 5.

Referring to FIG. 6A, first, an isolation layer 62 defining an active region 60 is formed on a silicon substrate using, for example, a shallow trench isolation (STI) method.

Next, a cell selection transistor having a gate electrode 64 and source / drain regions 66 and 68 is formed on the active region 60 and the device isolation film 62 in the same manner as a conventional MOS transistor manufacturing method. This process of FIG. 6A is performed in the same manner as the process of FIG. 4A described above.

Referring to FIG. 6B, an interlayer insulating film 70 is formed on a silicon substrate on which a cell select transistor is formed by forming a silicon oxide film using, for example, CVD. At this time, the interlayer insulating film 70 is the same film as the interlayer insulating film 40 in FIG. 4B.

Next, by selectively etching the interlayer insulating film 70 until the source / drain regions 66 and 68 are exposed using a photoresist pattern (not shown) defining a region where the contact plugs 72 and 74 are to be formed. A contact hole is formed.

The contact holes are then filled with a conductive material to form contact plugs 72 and 74 electrically connected to the source / drain regions 66 and 68. These contact plugs 72, 74 are formed together with the contact plug 42 in FIG. 4B.

Then, for example, a tungsten film (W) or a platinum (Pt) film is formed on the interlayer insulating film 70 including the contact plugs 72 and 74, and then patterned to form a source / drain through the contact plugs 72 and 74. The conductive film 76 and the source line 78 are electrically connected to the regions 66 and 68, respectively. That is, the conductive layer 76 is connected to the source / drain region 66 through the contact plug 72, and the source line 78 is connected to the source / drain region 68 through the contact plug 74. Like the source line SL of FIG. 2, the source line 78 of FIG. 6 is connected to the source line 44 of FIG. 4B.

Referring to FIG. 6C, after the interlayer insulating layer 80 is formed on the resultant product including the conductive layer 76 and the source line 78, the interlayer insulating layer 80 is selectively etched to contact the conductive layer 76. The plug 82 is formed.

Next, a pinned ferromagnetic 84, a tunnel junction layer 86, and a free ferromagnetic 88 are formed on the interlayer insulating film 80 including the contact plug 82. After forming sequentially, it is patterned to form a magnetic tunnel junction (MTJ).

Next, the interlayer insulating film 90 is formed on the resultant including the MTJ, and then the interlayer insulating film 90 is selectively etched to form a contact plug 92 connected to the free magnetic layer 88 of the MTJ.

Next, the bit line 94 connected to the contact plug 92 is patterned on the interlayer insulating layer 90 including the contact plug 92.

The present invention described above does not form MRAM cells in a corresponding region by not forming bit lines at regular intervals, but this problem is compared with the number of MRAM cells that can be additionally obtained through high integration using the present invention. The degree is very insignificant.

In the above-described embodiment, the metal line contact MLC is formed at the position without forming the bit lines at regular intervals, but is not limited thereto.

That is, the main feature of the present invention is to electrically connect the source line SL and the metal line ML at regular intervals after the metal line ML is additionally formed, that is, the location of the metal line contact MLC. Is formed at the top of the active region. In addition, in the above-described embodiment, the bit lines are not formed at regular intervals to secure a space for forming the metal line contact MLC. Therefore, if the metal line contact (MLC) can be formed sufficiently in the space between the bit lines, the structure of the cell array does not have a bit line non-forming section as in the above-described embodiment, and all bit lines are spaced as in the prior art. It can be formed as. In this case, the metal line contact MLC is formed on the device isolation layer.

In another embodiment, the metal line contact MLC may be formed at a position after the gap between the bit lines is sufficiently wide at a predetermined interval.

In addition, in the above-described embodiment, the case in which the metal line ML and the source line SL are connected at a predetermined interval has been described, but the distance between the metal line contacts MLC may vary depending on the position. For example, the distance between the metal line contacts MLC may be increased in the region close to the peripheral circuit, and conversely, the distance between the metal line contacts MLC may be shortened in the region far from the peripheral circuit. In this case, the interval at which the bit line is not formed in FIG. 2 also depends on the distance from the peripheral circuit.

In addition, the preferred embodiment of the present invention for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1 is a circuit diagram schematically showing a circuit configuration of a basic unit cell of an MRAM using a conventional spin movement function.

2 is a plan view showing the structure of a cell array region of an MRAM according to the present invention;

3 is a cross-sectional view showing a process cross section along the line AA ′ in FIG. 2.

4A to 4C are cross-sectional views illustrating a method of manufacturing an MRAM having the structure of FIG. 3.

5 is a cross-sectional view showing a process cross-section along the line B-B 'in FIG.

6A to 6C are cross-sectional views illustrating a method of manufacturing an MRAM having the structure of FIG. 5.

Claims (18)

A plurality of magnetic tunnel junctions (MTJs) formed between source lines and bit lines and whose magnetization directions are changed according to a direction of a current flowing between the source lines and the bit lines; A plurality of metal lines extending in the same direction as the source lines and formed in different layers from the source lines; And And a plurality of metal line contacts electrically connecting the corresponding source line and the metal line at a plurality of points. The method of claim 1, wherein the metal line Magnetic RAM, characterized in that formed on top of the source line to have a one-to-one correspondence with the source line. The method of claim 1, wherein the resistance of the metal line Magnetic RAM, characterized in that less than the resistance of the source line. The method of claim 3, wherein the metal line A magnetic ram comprising copper (Cu). The method of claim 1, wherein the metal line contacts Magnetic RAM, characterized in that formed between the bit lines at a predetermined interval. The method of claim 1, wherein the metal line contacts Magnetic RAM, characterized in that formed between the bit lines at different intervals in accordance with the distance from the peripheral circuit. The method of claim 5 or 6, wherein the metal line contacts And a magnetic RAM formed over the active region between the bit lines. The method of claim 7, wherein the bit line The magnetic ram of claim 2, wherein the magnetic line is not formed on the active region where the metal line contact is formed. The method of claim 7, wherein the MTJ is It is not formed in the active region where the metal line contact is formed The method of claim 5 or 6, wherein the metal line contacts Magnetic RAM, characterized in that formed on the device isolation layer between the bit lines. The method of claim 1, wherein the source line Magnetic RAM, characterized in that the portion connected to the metal line contact is wider than the portion that is not. Forming a source line connected to the source / drain regions of the cell transistor and extending in a first direction, on the semiconductor substrate including the cell transistor; Forming a metal line contact on the source line; And And forming a metal line connected to the metal line contact on the source line and extending in the first direction. The method of claim 12, wherein the forming of the source line Forming a first interlayer insulating film over the semiconductor substrate including the cell transistor; Selectively etching the first interlayer insulating layer until the source / drain regions are exposed to form a first contact hole; Forming a first contact plug to fill the first contact hole; Forming a first conductive film on the first interlayer insulating film having the first contact plug formed thereon; And And patterning the first conductive layer so as to be connected to the first contact plug and extend in the first direction. The method of claim 13, wherein the first conductive film Method of manufacturing a magnetic ram, characterized in that formed of tungsten (W) or platinum (Pt). The method of claim 13, wherein the forming of the metal line contact is performed. Forming a second interlayer insulating film on the source line; Selectively etching the second interlayer insulating layer until the source line is exposed to form a second contact hole; Forming a second contact plug to fill the second contact hole; Patterning a second conductive film connected to the second contact plug on the second interlayer insulating film including the second contact plug; Forming a third interlayer insulating film over the second conductive film; Selectively etching the third interlayer insulating layer until the second conductive layer is exposed to form a third contact hole; And And forming a third contact plug to fill the third contact hole. The method of claim 12, wherein the metal line Method of producing a magnetic ram, characterized in that formed of copper (Cu). The method of claim 12, wherein the metal line Magnetic RAM manufacturing method is characterized in that formed on the source line so as to overlap the source line. The method of claim 17, wherein the metal line Magnetic RAM manufacturing method characterized in that the width is formed wider than the source line.

Images