KR20100003077A - Internal voltage generation circuit of semicondector memory device - Google Patents

Internal voltage generation circuit of semicondector memory device Download PDF

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Publication number
KR20100003077A
KR20100003077A KR1020080063179A KR20080063179A KR20100003077A KR 20100003077 A KR20100003077 A KR 20100003077A KR 1020080063179 A KR1020080063179 A KR 1020080063179A KR 20080063179 A KR20080063179 A KR 20080063179A KR 20100003077 A KR20100003077 A KR 20100003077A
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KR
South Korea
Prior art keywords
voltage
pumping
high voltage
external power
power supply
Prior art date
Application number
KR1020080063179A
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Korean (ko)
Inventor
김용훈
Original Assignee
주식회사 하이닉스반도체
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Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080063179A priority Critical patent/KR20100003077A/en
Publication of KR20100003077A publication Critical patent/KR20100003077A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/462—Regulating voltage or current wherein the variable actually regulated by the final control device is dc as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
    • G05F1/465—Internal voltage generators for integrated circuits, e.g. step down generators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps

Abstract

PURPOSE: An internal voltage generation circuit of a semiconductor memory device is provided to reduce overall power consumption by reducing the current consumed in a read and write operation. CONSTITUTION: An external voltage sensor(140) senses the level of an external power voltage. A first pumping unit(135) pumps the external voltage once. A second pumping unit(137) pumps the external power voltage twice. A selection operation unit(150) selectively operates the first pumping unit or the second pumping unit according to the level of the external power voltage sensed from the external voltage sensor.

Description

INTERNAL VOLTAGE GENERATION CIRCUIT OF SEMICONDECTOR MEMORY DEVICE}

The present invention relates to a semiconductor memory device, and more particularly to an internal voltage generation circuit for generating a stable high voltage.

In general, a DRAM is a memory device capable of writing or reading data in a memory cell including one transistor and one capacitor. In order to drive the word line of the memory cell, a high voltage VPP, which is one of internal voltages generated inside the semiconductor memory device, is required. The high voltage is generated in the high voltage generation circuit in consideration of the power supply voltage VDD and the threshold voltage Vth of the MOS transistors constituting the cell transistor. The high voltage generation circuit includes an oscillation circuit and a charge pumping circuit, and the oscillation circuit operates in accordance with an enable signal to generate an oscillation signal having a predetermined period, and the charge pumping circuit has an external voltage according to the oscillation signal. The power supply voltage VDD is pumped to generate a high voltage having a predetermined level or more.

On the other hand, the high voltage generated in the memory device using the low power supply voltage VDD has a potential of approximately 3 to 4 volts. The high voltage is higher than the power supply voltage, and was made by pumping the power supply voltage using a pumping circuit. In particular, a high voltage pumping circuit such as a VPP triple generator (TRIPPLER) has been conventionally used.

1 is a block diagram of an internal voltage generation circuit of a conventional semiconductor memory device.

The internal voltage generation circuit of the conventional semiconductor memory device includes a high voltage detection unit 10 that receives the feedback high voltage VPP and generates a detection signal VPP_DET that determines whether a high voltage is generated in comparison with the internal reference potential. When the detection signal VPP_DET of the high voltage detection unit 10 is input, the oscillator OSC output is toggled when the enable state is high (high level state), and when the disable state (low level state) is performed. And a high voltage oscillator 15 to fix the oscillator output.

Accordingly, the pumping unit 30 performs a pumping operation for generating a high voltage when the high voltage oscillator 15 toggles the oscillator output OSC. The configuration of the pumping unit 30, as mentioned above, is composed of a high voltage triple generator for continuously pumping the input external voltage to generate a high voltage (3VDD) about three times the external voltage (VDD).

On the other hand, the external voltage VDD supplied to the semiconductor memory device is gradually decreasing. Therefore, the normal operation at an external voltage below a certain level must ensure the driving force of the high voltage pump and whether or not the target level of the high voltage is formed. This is because when the supply voltage of the semiconductor memory device is lowered, the driving ability is weakened, which leads to a decrease in supply current. If the current consumption exceeds the supply current, the level of the high voltage is lowered, causing additional high voltage oscillator current and cell write time (tWR) damage.

Further, the tripler TRIPPLER, which is a pumping circuit used in the conventional internal voltage generation circuit, is set to a target level obtained by high voltage pumping at about 3.0 volts when the external voltage VDD is 1.05 volts. However, when the finished product is actually mounted and used, the pumping output does not reach the target level due to the line loading or the capacitance component, and the pumping operation must be continuously performed, and thus the operating current consumption and the target level are not reached. There is a problem that causes a decrease in tWR.

Accordingly, an object of the present invention is to provide an internal voltage generation circuit of a semiconductor memory device capable of generating a stable high voltage regardless of the size of an external power source.

A second object of the present invention is to provide an internal voltage generation circuit of a semiconductor memory device that controls a high voltage pumping configuration differently according to the size of an external power source.

An internal voltage generation circuit of a semiconductor memory device according to the present invention for achieving the above object, the external voltage sensing means for detecting the level of the external power supply voltage; First pumping means for pumping an external voltage by a first multiple; Second pumping means for pumping an external voltage by a second multiple; And selection operation means for selectively operating the first pumping means or the second pumping means in accordance with the level of the external power supply voltage detected by the external voltage sensing means.

Accordingly, the present invention uses a triple pumping unit when the external power level is relatively high compared to the normal level, and when the external power level is relatively low, the pump is switched to a quadruple pumping unit to prevent a decrease in the pumping efficiency of the triple pumping unit at a low external power source. Therefore, the present invention reduces the current consumed during the read and write operations after the active operation, thereby reducing the overall power consumption of the semiconductor memory device. In addition, the present invention can increase the IVPP supply capacity compared to the conventional use of only the triple pumping unit, it is possible to prevent the VPP level drop due to IVPP consumption. In addition, the present invention can maintain the VPP level high and stable compared to the use of the triple pump can also obtain the effect of ensuring the tWR performance.

Hereinafter, an internal voltage generation circuit of a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating an embodiment of an internal voltage generation circuit of a semiconductor memory device according to the present invention.

The present invention includes a high voltage detector 100 that receives a feedback high voltage VPP and generates a detection signal VPP_DET that determines whether a high voltage is generated by comparing with an internal reference potential. When the detection signal VPP_DET of the high voltage detection unit 100 is input, the oscillator output is toggled when the enable state is high (high level state), and when the disable state (low level state) is performed. And a high voltage oscillator 115 to fix the oscillator output.

In addition, the present invention includes an external power supply voltage sensing unit 140 for detecting the level of the external power supply (VDD). The external power supply voltage detector 140 compares the external power supply with a reference voltage, and outputs a high level signal when the external power supply is lower than the reference voltage, and outputs a low level signal when the external power supply voltage is equal to or higher than the reference voltage.

In addition, the present invention includes a selection operation unit 150 for logically calculating an oscillator output 0SC of the high voltage oscillator 115 and an output of the external power voltage sensing unit 140 to select a pumping unit to operate. The selection operation unit 150 calculates an oscillator output (OSC) of the high voltage oscillator 115 and an output of the external power voltage sensing unit 140 to operate a triple pumping unit 135 to be described below. TRP_IN) to generate a NOR operator 151. The NAND calculator generates a pumping signal QD_IN for operating the quadruple pumping unit 137 to be described later by calculating an oscillator output OSC of the high voltage oscillator 115 and an output of the external power voltage sensing unit 140. 153 and inverter 155.

Therefore, the configuration of the pumping unit of the present invention, as described above, the triple pumping unit 135 to generate a high voltage (3VDD) of about three times the external voltage (VDD) by continuously pumping the input external voltage, It is configured to include a quadruple pumping unit 137 for continuously pumping the external voltage to generate a high voltage (4VDD) four times the external voltage (VDD).

The internal voltage generation circuit of the semiconductor memory device according to the present invention having the above configuration is operated as follows.

3 is an operation waveform diagram of each part shown in the internal voltage generation circuit of the semiconductor memory device according to the present invention.

The high voltage detection unit 110 receives the high voltage output of the triple pumping unit 135 or the quadruple pumping unit 137. When the feedback high voltage is lower than the reference potential, the feedback signal VPP_DET is controlled to an enable state (high level state).

The detection signal of the high voltage detector 110 is input to the high voltage oscillator 115. The high voltage oscillator 115 toggles an oscillator output OSC when the detection signal is enabled. On the contrary, when the detection signal is in the disabled state (low level state), the oscillator output is fixed (FIX) to stop the toggling operation.

Meanwhile, in order to detect the level of the external power supply voltage VDD, the external power supply voltage detector 140 pumps efficiency (E FF%) according to the change of the external power supply VDD of the reference potential (triple pumping unit and quadruple pumping unit). It judges based on the external power supply VDD which becomes a cross on a characteristic curve. When the external power supply voltage is lower than the reference potential, the detection signal VDD_DET is outputted as an enable state (high level signal). On the contrary, when the external power supply voltage is higher than the reference potential, the detection signal VDD_DET is output as a disabled state (low level signal).

Therefore, the oscillator output generated by the high voltage oscillator 115 and the detection signal sensed by the external power voltage detector 140 are input to the selection operation unit 150.

When the detection signal VDD_DET is at a low level (when the external power supply voltage is relatively high compared to the reference potential), the selection operation unit 150 generates a low signal by the arithmetic operation of the NAND gate 153 and the inverter 155. It is fixed and provided to the quadruple pumping unit 137. Therefore, the quadruple pumping unit 137 is blocked when the external power supply voltage is relatively higher than the reference potential.

In addition, when the detection signal VDD_DET is low level (when the external power supply voltage is relatively high compared to the reference potential), the selection operation unit 150 generates an oscillator output signal OSC by the operation of the noah gate 151. A toggling signal TRP_IN having a state opposite to that of phase is generated. The signal TRP_IN generated in this way is input to the triple pumping unit 135. Therefore, when the external power supply voltage is relatively higher than the reference potential, the triple pumping unit 135 performs a high voltage pumping operation by the toggling signal TRP_IN output from the selection operation unit 150.

Next, when the detection signal VDD_DET generated by the selection operation unit 150 is high level (when the external power supply voltage is relatively low compared to the reference potential), the high signal has no effect on the output of the NAND gate 153. Will not give. That is, in this case, the output signal OSC of the high voltage oscillator 115 is output as it is in the output signal obtained by the calculation of the NAND gate 153 and the inverter 155. Therefore, when the external power supply voltage is relatively lower than the reference potential, the quadruple pumping unit 137 performs the high voltage pumping operation by the toggling signal QD_IN output from the selection operation unit 150.

In addition, when the detection signal VDD_DET is high level (when the external power supply voltage is relatively low compared to the reference potential), the selection operation unit 150 is fixed to the low signal by the noah gate 151 and the triple pumping unit ( 135). Therefore, the triple pumping unit 135 is blocked when the external power supply voltage is relatively lower than the reference potential.

4 and 5 show the pump efficiency characteristics according to the change of the external power supply voltage. As shown in FIG. 4, when the external power supply voltage is lower than the reference potential VDD1, the quadruple pumping unit has excellent pump efficiency, and when the external power supply voltage is higher than the reference potential VDD1, the triple pumping unit has high pump efficiency. great.

Therefore, in the exemplary embodiment of the present invention, as shown in FIG. 5, when the external power supply voltage is lower than the reference potential, the high voltage pumping operation can be performed in the quadruple pumping unit, and when the external power supply voltage is higher than the reference potential, the triple pumping unit In order to control the high voltage pumping operation.

The above-described preferred embodiment of the present invention, which is disclosed for the purpose of illustration, has two pumping modes to generate a stable high voltage, and is applied to the case of differently controlling the pumping mode according to the level of an external power source. Therefore, those skilled in the art will be able to improve, change, substitute or add other embodiments within the technical spirit and scope of the present invention disclosed in the appended claims.

1 is a block diagram of an internal voltage generation circuit according to the prior art;

2 is a block diagram of an internal voltage generation circuit according to an embodiment of the present invention;

3 is a waveform diagram of each part of the internal voltage generation circuit of the present invention;

4 and 5 are pump efficiency characteristics according to the change in the external power supply voltage.

Explanation of symbols on the main parts of the drawings

110: high voltage detector 115: high voltage oscillator

130,135,137: pumping unit 140: external power voltage detection unit

150: selection operation unit

Claims (5)

External voltage sensing means for detecting a level of an external power supply voltage; First pumping means for pumping an external voltage by a first multiple; Second pumping means for pumping an external voltage by a second multiple; And selection operation means for selectively operating the first pumping means or the second pumping means in accordance with the level of the external power supply voltage detected by the external voltage sensing means. The method of claim 1, And a high voltage sensing means for receiving a high voltage generated by the first pumping means or the second pumping means and receiving a feedback signal, and generating a detection signal for determining whether a high voltage is generated in comparison with an internal reference potential. Internal voltage generator circuit. The method of claim 2, And a high voltage oscillating means for toggling an oscillator (OSC) output when the detection signal of the high voltage sensing means is input to enable the oscillator (OSC) output. The method of claim 3, wherein And said selecting operation means selects a pumping means to operate by performing a logical operation on an oscillator output of said high voltage oscillation means and an output of said external power supply voltage sensing means. The method of claim 4, wherein The selection operation means may include: a first calculating part operating the first pumping means by calculating with the enable signal of the high voltage oscillation means when the external power supply voltage is relatively higher than the normal potential level; And a second calculation unit configured to operate the second pumping means by calculating with the enable signal of the high voltage oscillation means when the external power supply voltage is relatively lower than the normal potential level. .
KR1020080063179A 2008-06-30 2008-06-30 Internal voltage generation circuit of semicondector memory device KR20100003077A (en)

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Application Number Priority Date Filing Date Title
KR1020080063179A KR20100003077A (en) 2008-06-30 2008-06-30 Internal voltage generation circuit of semicondector memory device

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9423806B2 (en) 2013-06-21 2016-08-23 SK Hynix Inc. Semiconductor device
US9543827B2 (en) 2014-11-26 2017-01-10 SK Hynix Inc. Internal voltage generation circuits

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9423806B2 (en) 2013-06-21 2016-08-23 SK Hynix Inc. Semiconductor device
US9543827B2 (en) 2014-11-26 2017-01-10 SK Hynix Inc. Internal voltage generation circuits

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