KR20090130556A - Liquid crystal display - Google Patents

Abstract

PURPOSE: A liquid crystal display device is provided to differentiate a structure of an electrode to reduce a disclination region and an inefficient driving region and improve a transmission rate and a contrast ratio. CONSTITUTION: The first gate metal(202a), the second gate metal(202b) and dummy metal(202c) are located on the first substrate. The first insulating layer are located on the first and second gate metal and the dummy metal. An active layer is overlapped with the first gate metal on the first insulating layer. A data line(208), and a source and a drain are located on the first insulating layer. The second insulating layer covers the data line, the source and the drain. A pixel electrode(218) and a common electrode(222) are put on the second insulating layer.

Description

Liquid Crystal Display

The present invention relates to a liquid crystal display device.

With the development of information technology, the market for a display device, which is a connection medium between a user and information, is growing. Accordingly, flat panel displays (FPDs), such as liquid crystal displays (LCDs), organic light emitting diodes (OLEDs), and plasma display panels (PDPs), may be used. Usage is increasing. Among them, a liquid crystal display device capable of realizing high resolution and capable of large size as well as small size is widely used.

Here, the liquid crystal display device is classified into a light receiving display device. Such a liquid crystal display may display an image by receiving a light source from a backlight unit disposed under the liquid crystal panel.

The liquid crystal display is largely composed of a transistor array first substrate and a color filter first substrate. A subpixel including a transistor, a pixel electrode connected to a source or a drain of the transistor, a common electrode, and the like is formed on the transistor array first substrate. A color filter, a black matrix, and the like are formed on the first color filter substrate.

On the other hand, in the conventional liquid crystal display, a discretization region in which light cannot be transmitted in the boundary region due to local alignment defects occurs in a portion of the pixel electrode and the common electrode, thereby decreasing transmittance and contrast ratio. Degradation causes a problem of deterioration of display quality, so a solution for this problem must be prepared.

An object of the present invention for solving the above problems of the background art is to change the structure of the electrode to improve the uniformity of the electric field direction to reduce the disclination region and inefficient driving region, and transmittance and contrast ratio It is to provide a liquid crystal display device that can be improved.

The present invention as a means for solving the above problems, the first substrate; A dummy metal disposed on the first substrate and disposed to face the first gate metal connected to the scan wiring, the second gate metal connected to the common voltage wiring, and the second gate metal so as to form a closed curve open on one plane; A first insulating layer on the first and second gate metals and the dummy metal; An active layer overlapping the first gate metal on the first insulating layer; A data wiring disposed on the first insulating layer along the major axis of the second gate metal, a source in contact with one end of the active layer and connected to the data wiring, and a drain in contact with the other end of the active layer and separated from the source; A second insulating film covering a data line, a source, and a drain on the first insulating film; And a pixel electrode connected to the source or drain on the second insulating layer and connected to the dummy metal, and a common electrode connected to the second gate metal.

On the other hand, the present invention in another aspect, the first substrate; A first gate metal disposed on the first substrate and connected to the scan wiring, and a second gate metal connected to the common voltage wiring; A first insulating layer on the first and second gate metals; An active layer overlapping the first gate metal on the first insulating layer; A data wiring disposed on the first insulating film along the major axis of the second gate metal, a source in contact with one end of the active layer and connected to the data wiring, a drain in contact with the other end of the active layer and separated from the source, and a second gate. Dummy metals disposed opposite to each other to form a closed curve open on one plane with the metals; A second insulating layer covering the data line, the source, the drain, and the dummy metal on the first insulating layer; And a pixel electrode connected to the source or drain on the second insulating layer and connected to the dummy metal, and a common electrode connected to the second gate metal.

The second gate metal, the dummy metal, the pixel electrode, and the common electrode may have an L shape in which a part of the region where they overlap each other is inclined on one plane.

The dummy metal may be formed by the same material and the same process as the first gate metal or the second gate metal.

The dummy metal may be formed by the same material and the same process as the source or drain.

The dummy metal may be located in a region opposite to the minor axis direction of the second gate metal on one plane and may have a smaller minor axis direction area than the minor axis area of the second gate metal.

The dummy metal may be located in an area that faces the long axis and short axis direction of the second gate metal on one plane, and may have a long axis and short axis area that are narrower than the long axis and short axis areas of the second gate metal.

The dummy metal may be positioned in a region of the second gate metal that faces the long axis direction of the second gate metal and may have a longer length area than the long length and short length areas of the second gate metal.

In the pixel electrode and the common electrode, an electrode divided from a short axis direction may extend in a long axis direction.

In the pixel electrode and the common electrode, an electrode divided from a long axis direction may extend in a short axis direction.

The present invention provides an effect of providing a liquid crystal display device which can reduce the disclination region and the inefficient driving region and improve the transmittance and contrast ratio by changing the structure of the electrode so as to improve the uniformity of the electric field direction. There is.

Hereinafter, with reference to the accompanying drawings, the specific content for the practice of the present invention will be described.

1 is an exploded perspective view of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an exemplary view of an edge type light source.

As shown in FIG. 1, the liquid crystal display may include a light source 171 for emitting light. In addition, the optical film layer 176 to guide the light emitted from the light source 171 may be included. The optical film layer 176 may include a diffusion plate 172, a diffusion sheet 173, an optical sheet 174, and a protective sheet 175 positioned on the light source 171.

For the light source 171, for example, Cold Cathode Fluorescent Lamp (CCFL), Hot Cathode Fluorescent Lamp (HCFL), External Electrode Fluorescent Lamp (EEFL) and Luminescence One of a diode (Light Emitting Diode: LED) may be selected, but is not limited thereto.

In addition, the light source 171 may select any one of an edge type in which the lamp is located on one side outside, a dual type in which the lamp is located on both sides, and a direct type in which a plurality of lamps are arranged in a straight line, but is not limited thereto. The light source 171 as described above may be connected to an inverter to receive power by emitting power.

The light source 171 shown in FIG. 1 shows a direct type as an example. Alternatively, referring to FIG. 2, an edge type light source 171 is shown. The edge-type light source 171 as shown may include a lamp 171a and a light guide plate 171b for guiding light emitted from the lamp 171a on one side outside thereof, but is not limited thereto.

In the case of the optical sheet 174 described above, for example, it may have a prism shape as shown, but may be positioned in a shape such as a lenticular lens or a micro lens. And such an optical sheet 174 may include a bead.

Meanwhile, the liquid crystal display may include a liquid crystal panel 183 for displaying an image and an upper case 190 and a lower case 170 in which the light source 171 is accommodated.

Here, the lower case 170 may accommodate the light source 171. The liquid crystal panel 183 may be disposed on the light source 171 at a predetermined interval. The liquid crystal panel 183 and the light source 171 may be fixed and protected by the upper case 190 fastened to the lower case 170.

An opening for exposing an image display area of the liquid crystal panel 183 may be provided on an upper surface of the upper case 190. In addition, a mold frame (not shown) may be further included in which a peripheral portion of the optical film layer 176 positioned between the liquid crystal panel 183 and the light source 171 is seated.

The liquid crystal panel 183 may have a structure in which the first substrate 110 having the thin film transistor array and the second substrate 180 having the color filter are bonded to each other with the liquid crystal layer interposed therebetween. In the liquid crystal panel 183, sub-pixels driven independently by the thin film transistor are arranged in a matrix form.

Each sub-pixel may display an image by adjusting the light transmittance by controlling the liquid crystal array according to the difference voltage between the common voltage supplied to the common electrode and the data signal supplied to the pixel electrode connected to the thin film transistor. The common voltage can be generated by the DC / DC converter, and the common voltage generated by the DC / DC converter is supplied to the common electrode located in the sub pixel via the common voltage wiring.

In addition, the driving unit 189 may be connected to the first substrate 110 of the liquid crystal panel 183. The driver 189 is mounted with a driving chip 130 including a data driver and a scan driver for driving the data wires and the scan wires of the liquid crystal panel 183, respectively, to which the first substrate 110 and one side part are connected. The flexible film 120 and the external circuit board 188 connected to the other side of the plurality of flexible films 120 may be included.

The flexible film 120 having the driving chip 130 mounted thereon may be positioned in a chip on film (COF) or tape carrier package (TCP) method. However, at least one of the data driver and the scan driver included in the driving chip 130 may be directly mounted on the first substrate 110 by a chip on glass (COG) method or may be mounted on the first substrate 110 in a thin film transistor forming process. It can be formed and built in.

Hereinafter, various structures of a subpixel will be described with reference to a schematic cross-sectional view.

First Embodiment

3 is a plan view of a subpixel according to the first exemplary embodiment of the present invention, FIG. 4 is a sectional view of an area A1-A1 of FIG. 3, FIG. 5 is a sectional view of an area B1-B2, and FIG. 6 is an exploded view of FIG. to be.

The subpixel illustrated in FIG. 3 omits the first insulating film 203 and the second insulating film 209, and the omitted first insulating film 203 and the second insulating film 209 may be omitted. Only a cross-sectional view of the thin film transistor located in the region A1-A1 is shown. Meanwhile, the x-axis illustrated in FIG. 3 represents a short axis direction based on the subpixels, and the y-axis represents a long axis direction based on the subpixels.

3 to 6 together, the sub pixel is formed on the first substrate 210.

The first substrate 210 may be selected as a material for forming an element having excellent mechanical strength or dimensional stability. As the material of the substrate 210, a glass plate, a metal plate, a ceramic plate or a plastic plate (polycarbonate resin, acrylic resin, vinyl chloride resin, polyethylene terephthalate resin, polyimide resin, polyester resin, epoxy resin, silicone resin, fluorine) Resin, etc.) is mentioned.

On the first substrate 210, a closed curve shape is opened on one plane together with the first gate metal 202a connected to the scan wiring, the second gate metal 202b connected to the common voltage wiring, and the second gate metal 202b. The dummy metals 202c are disposed to be opposite to each other.

The first gate metal 202a, the second gate metal 202b, and the dummy metal 202c may be formed by the same material and the same process. The first gate metal 202a, the second gate metal 202b, and the dummy metal 202c include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), and nickel (Ni). ), Neodymium (Nd) and copper (Cu) may be made of any one or an alloy thereof. In addition, any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) It may be a multilayer consisting of an alloy of. It may also be a bilayer of molybdenum / aluminum-neodymium or molybdenum / aluminum.

The first insulating layer 203 is positioned on the first and second gate metals 202a and 202b and the dummy metal 202c. The first insulating layer 203 may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or multiple layers thereof, but is not limited thereto.

The active layer 204a overlapping the first gate metal 202a is disposed on the first insulating layer 203. A source region and a drain region may be defined on the active layer 204a, and an ohmic contact layer 204b may be positioned in contact with each other. The active layer 204a may be formed of a-Si, p-Si, or the like, and the ohmic contact layer 204b may be positioned to reduce electrical contact resistance.

The data line 208 may be disposed on the first insulating layer 203 along the long axis direction y of the second gate metal 202b.

Further, on the first insulating layer 203, a source 205 in contact with one end of the active layer 204a and connected to the data line 208, and a drain in contact with the other end of the active layer 204a and separated from the source 205. 206 may be located. The source 205 and the drain 206 may be formed of a single layer or multiple layers, and when the source 205 and the drain 206 are a single layer, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) may be made of any one or an alloy thereof. In addition, when the source 205 and the drain 206 are multiple layers, the double layer of molybdenum / aluminum-neodymium and the triple layer of molybdenum / aluminum / molybdenum or molybdenum / aluminum-neodymium / molybdenum may be used.

The second insulating layer 209 may be disposed on the first insulating layer 203 to cover the data line 208, the source 205, and the drain 206. The second insulating layer 209 may be a silicon oxide layer SiOx, a silicon nitride layer SiNx or a multilayer thereof, but is not limited thereto. The second insulating layer 209 may be a protective layer.

The pixel electrode 218 connected to the source 205 or the drain 206 and connected to the dummy metal 202c may be positioned on the second insulating layer 209. The pixel electrode 218 may be any one of indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO). On the other hand, the pixel electrode 218 located above the second insulating film 209 and the second gate metal 202b located below the second insulating film 209 overlap each other in the long axis direction x. A capacitor cst is formed.

The common insulating layer 222 connected to the second gate metal 202b may be included on the second insulating layer 209. The common electrode 222 may be formed of any one of indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO), like the pixel electrode 218, but is not limited thereto.

The pixel electrode 218 and the common electrode 222 may be separately disposed on the second insulating layer 209 so that the electrodes divided from the short axis direction x extend in the long axis direction y.

In the above description, the pixel electrode 218 may be connected to the source 205 or the drain 206 through the first contact hole C1 and electrically connected to the dummy metal 202c through the third contact hole C3. Can be connected. The common electrode 222 may be electrically connected to the second gate metal 202b through the second contact hole C2.

Meanwhile, the second gate metal 202b, the dummy metal 202c, the pixel electrode 218, and the common electrode 222 may be a portion of the region where they overlap each other, such as regions of “OR1” and “OR2” of FIG. 5. May be L-shaped with an inclination r on one plane.

As such, when a portion of the region where the second gate metal 202b, the dummy metal 202c, the pixel electrode 218, and the common electrode 222 overlap each other is formed as an L (L), the electric field is formed on the upper part of the subpixel and The lower region may be formed in a similar direction. In addition, when the L shape is formed at an inclination r of 90 ° to 160 °, the field directions of the pixel electrode 218 and the common electrode 222 may be uniformly arranged in the subpixel.

Here, the region having the inclination r of the L (L) may correspond to the starting point of the region in which a part of the pixel electrode 218 and the common electrode 222 are divided in the long axis direction. Here, the overlapping region may correspond between the pixel electrode 218 and the dummy metal 202c and between the common electrode 222 and the second gate metal 202b in addition to the region described above.

The dummy metal 202c may be located in a region of the second gate metal 202b that faces the minor axis direction x of the second gate metal 202b and may have a smaller minor axis direction area than that of the second gate metal 202c. (See Figure 6)

As described above, the pixel electrode 218 is formed to be connected to the dummy metal 202c disposed under the second insulating layer 209, and the second gate metal 202b, the dummy metal 202c, and the pixel electrode ( If the region in which the 218 and the common electrode 222 overlap with each other is formed as an L (L), the length of the pixel electrode 218 can be extended, and inefficient driving is performed between the pixel electrode 218 and the common electrode 222. This area can be reduced.

Second Embodiment

7 is a plan view of a subpixel according to a second exemplary embodiment of the present invention, FIG. 8 is a cross-sectional view of an area A2-A2 of FIG. 7, and FIG. 9 is an exploded view of FIG. 7.

The subpixels shown in FIG. 7 omit the first insulating layer 303 and the second insulating layer 309 so as to provide easy division, and the omitted first insulating layer 303 and the second insulating layer 309 are shown in FIG. 8. Only the cross-sectional view of the thin film transistor located in the A2-A2 area | region is shown. Meanwhile, the x-axis illustrated in FIG. 7 represents a short axis direction based on the subpixel, and the y-axis represents a long axis direction based on the subpixel.

7 to 9 together, the sub-pixels are formed on the first substrate 310.

On the first substrate 310, a closed curve shape is opened on one plane together with the first gate metal 302a connected to the scan wiring, the second gate metal 302b connected to the common voltage wiring, and the second gate metal 302b. The dummy metals 302c are disposed to be arranged to face each other.

The first gate metal 302a, the second gate metal 302b, and the dummy metal 302c may be formed by the same material and the same process.

The first insulating layer 303 is positioned on the first and second gate metals 302a and 302b and the dummy metal 302c. The first insulating layer 303 may be a silicon oxide film SiOx, a silicon nitride film SiNx, or a multilayer thereof, but is not limited thereto.

An active layer 304a overlapping the first gate metal 302a is disposed on the first insulating layer 303. A source region and a drain region may be defined on the active layer 304a, and an ohmic contact layer 304b may be positioned in contact with each other. The active layer 304a may be formed of a-Si, p-Si, or the like, and the ohmic contact layer 304b may be positioned to reduce electrical contact resistance.

The data line 308 disposed along the major axis direction y of the second gate metal 302b may be positioned on the first insulating layer 303.

Further, on the first insulating layer 303, a source 305 that contacts one end of the active layer 304a and is connected to the data line 308, and a drain that contacts the other end of the active layer 304a and is separated from the source 305. 306 may be located.

The second insulating layer 309 may be disposed on the first insulating layer 303 to cover the data line 308, the source 305, and the drain 306. The second insulating layer 309 may be a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof, but is not limited thereto. The second insulating layer 309 may be a protective layer.

A pixel electrode 318 connected to the source 305 or the drain 306 and connected to the dummy metal 302c may be disposed on the second insulating layer 309. On the other hand, the pixel electrode 318 positioned above the second insulating layer 309 and the second gate metal 302b positioned below the second insulating layer 309 overlap each other in the long axis direction x. A capacitor cst is formed.

The common insulating layer 322 connected to the second gate metal 302b may be included on the second insulating layer 309. The common electrode 322 may be formed of any one of indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO), like the pixel electrode 318, but is not limited thereto.

The pixel electrode 318 and the common electrode 322 may be separately disposed on the second insulating layer 309 such that the electrode divided from the short axis direction x extends along the long axis direction y.

In the above description, the pixel electrode 318 may be connected to the source 305 or the drain 306 through the first contact hole C1 and electrically connected to the dummy metal 302c through the third contact hole C3. Can be connected. The common electrode 322 may be electrically connected to the second gate metal 302b through the second contact hole C2.

The second gate metal 302b, the dummy metal 302c, the pixel electrode 318, and the common electrode 322 may be partially overlapped with each other, as shown in the “OR1” and “OR2” regions. It may be formed in an L (L) shape having a slope on one plane.

As such, when a portion of the region where the second gate metal 302b, the dummy metal 302c, the pixel electrode 318, and the common electrode 322 overlap each other is formed as an L (L), the electric field is formed on the upper part of the subpixel and The lower region may be formed in a similar direction. In addition, when the L shape is formed at an inclination r of 90 ° to 160 °, the field directions of the pixel electrode 318 and the common electrode 322 may be uniformly disposed in the subpixel.

Here, the region having the inclination of the L (L) may correspond to the starting point of the region in which a part of the pixel electrode 318 and the common electrode 322 are divided in the long axis direction. Here, the overlapping region may correspond to the pixel electrode 318 and the dummy metal 302c and the common electrode 322 and the second gate metal 302b in addition to the above-described region.

The dummy metal 302c is located in a region of the second gate metal 302b opposite to the major axis and minor axis directions (x, y) of the second gate metal 302b and narrower than the major axis and minor axis area of the second gate metal 302b; It may have a uniaxial direction area (see FIG. 9).

As described above, the pixel electrode 318 is formed to be connected to the dummy metal 302c disposed under the second insulating layer 309, and the second gate metal 302b, the dummy metal 302c, and the pixel electrode are formed. If the region where the 318 and the common electrode 322 overlap with each other is formed as an L (L), the length of the pixel electrode 318 can be extended and inefficient driving between the pixel electrode 318 and the common electrode 322 can be achieved. This area can be reduced.

Third Embodiment

10 is a plan view of a subpixel according to a third exemplary embodiment of the present invention, FIG. 11 is a cross-sectional view of an area A3-A3 of FIG. 10, and FIG. 12 is an exploded view of FIG. 10.

The subpixel illustrated in FIG. 10 omits the first insulating film 403 and the second insulating film 409, and the omitted first insulating film 403 and the second insulating film 409 may be omitted. Only the cross-sectional view of the thin film transistor located in the A3-A3 area | region is shown. Meanwhile, the x-axis shown in FIG. 10 represents a short axis direction based on the subpixel, and the y-axis represents a long axis direction based on the subpixel.

10 to 12, the sub pixel is formed on the first substrate 410.

On the first substrate 410, a closed curve shape is opened on one plane together with the first gate metal 402a connected to the scan wiring, the second gate metal 402b connected to the common voltage wiring, and the second gate metal 402b. The dummy metals 402c are disposed so as to form opposite sides.

The first gate metal 402a, the second gate metal 402b, and the dummy metal 402c may be formed by the same material and the same process.

The first insulating layer 403 is positioned on the first and second gate metals 402a and 402b and the dummy metal 402c. The first insulating layer 403 may be a silicon oxide layer SiOx, a silicon nitride layer SiNx, or a multilayer thereof, but is not limited thereto.

The active layer 404a overlapping the first gate metal 402a is positioned on the first insulating layer 403. A source region and a drain region may be defined on the active layer 404a, and an ohmic contact layer 404b may be positioned in contact with each other. The active layer 404a may be formed of a-Si, p-Si, or the like, and the ohmic contact layer 404b may be positioned to reduce electrical contact resistance.

The data line 408 may be disposed on the first insulating layer 403 along the long axis direction y of the second gate metal 402b.

Further, on the first insulating layer 403, a source 405 contacting one end of the active layer 404a and connected to the data line 408, and a drain contacting the other end of the active layer 404a and separated from the source 405. 406 may be located.

The second insulating layer 409 may be disposed on the first insulating layer 403 to cover the data line 408, the source 405, and the drain 406. The second insulating film 409 may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof, but is not limited thereto. The second insulating film 409 may be a protective film.

The pixel electrode 418 connected to the source 405 or the drain 406 and connected to the dummy metal 402c may be positioned on the second insulating layer 409. On the other hand, the pixel electrode 418 positioned on the second insulating layer 409 and the second gate metal 402b positioned on the lower portion of the second insulating layer 409 overlap each other in the long axis direction x. Capacitor cst is formed.

A common electrode 422 connected to the second gate metal 402b may be included on the second insulating layer 409. The common electrode 422 may be formed of any one of indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO), like the pixel electrode 418, but is not limited thereto.

The pixel electrode 418 and the common electrode 422 may be separately disposed on the second insulating layer 409 so that the electrodes divided from the major axis direction y extend in the minor axis direction x.

In the above description, the pixel electrode 418 may be connected to the source 405 or the drain 406 through the first contact hole C1 and electrically connected to the dummy metal 402c through the third contact hole C3. Can be connected. The common electrode 422 may be electrically connected to the second gate metal 402b through the second contact hole C2.

On the other hand, the second gate metal 402b, the dummy metal 402c, the pixel electrode 418 and the common electrode 422, as shown in the "OR1" and "OR2" region, a part of the region where they overlap each other It may be formed in an L (L) shape having a slope on one plane.

As such, when a portion of the region where the second gate metal 402b, the dummy metal 402c, the pixel electrode 418, and the common electrode 422 overlap each other is formed as an L (L), the electric field is formed on the upper part of the subpixel and The lower region may be formed in a similar direction. In addition, when the L shape is formed at an inclination r of 90 ° to 160 °, the field directions of the pixel electrode 418 and the common electrode 422 may be uniformly disposed in the subpixel.

Here, the region having the inclination of the L (L) may correspond to the starting point of the region where the pixel electrode 418 and the common electrode 422 are divided in the long axis direction. Here, the overlapping region may correspond between the pixel electrode 418 and the dummy metal 402c and between the common electrode 422 and the second gate metal 402b in addition to the above-described region.

The dummy metal 402c may be located in a region of the second gate metal 402b that faces the long axis direction y of the second gate metal 402b and may have a smaller length area than the long axis and short axis areas of the second gate metal 402b. (See Figure 12).

As described above, the pixel electrode 418 is formed to be connected to the dummy metal 402c disposed under the second insulating film 409, and the second gate metal 402b, the dummy metal 402c, and the pixel electrode ( If a portion where the 418 and the common electrode 422 overlap with each other is formed as an L (L), the length of the pixel electrode 418 can be extended and inefficient driving between the pixel electrode 418 and the common electrode 422 can be achieved. The area of occurrence can be reduced.

Fourth Embodiment

13 is a plan view of a subpixel according to a fourth exemplary embodiment of the present invention, FIG. 14 is a cross-sectional view of region A4-A4 of FIG. 13, and FIG. 15 is an exploded view of FIG. 13.

The subpixels shown in FIG. 13 omit the first insulating film 503 and the second insulating film 509, and the omitted first insulating film 503 and the second insulating film 509 are shown in FIG. Only the cross-sectional view of the thin film transistor located in the A4-A4 area | region is shown. Meanwhile, the x-axis illustrated in FIG. 13 represents a short axis direction based on the subpixel, and the y-axis represents a long axis direction based on the subpixel.

Referring to FIGS. 13 to 15, the subpixels are formed on the first substrate 510.

The first gate metal 502a connected to the scan wiring and the second gate metal 502b connected to the common voltage wiring are positioned on the first substrate 510.

The first insulating layer 503 is positioned on the first and second gate metals 502a and 502b and the dummy metal 502c. The first insulating layer 503 may be a silicon oxide film SiOx, a silicon nitride film SiNx, or a multilayer thereof, but is not limited thereto.

The active layer 504a overlapping the first gate metal 502a is disposed on the first insulating layer 503. A source region and a drain region may be defined on the active layer 504a, and an ohmic contact layer 504b may be positioned in contact with each other. The active layer 504a may be formed of a-Si, p-Si, or the like, and the ohmic contact layer 504b may be positioned to reduce electrical contact resistance.

The data line 508 may be disposed on the first insulating layer 503 along the long axis direction y of the second gate metal 502b.

Further, on the first insulating film 503, a source 505 that contacts one end of the active layer 504a and is connected to the data line 508, and a drain that contacts the other end of the active layer 504a and is separated from the source 505. 506 and a dummy metal 502c disposed to face each other so as to form an open closed curve together with the second gate metal 502b formed below on one plane. The source 505, drain 506 and dummy metal 502c may be formed by the same material and the same process.

The second insulating layer 509 may be disposed on the first insulating layer 503 to cover the data line 508, the source 505, the drain 506, and the dummy metal 502c. The second insulating layer 509 may be a silicon oxide layer SiOx, a silicon nitride layer SiNx, or a multilayer thereof, but is not limited thereto. The second insulating layer 509 may be a protective layer.

The pixel electrode 518 connected to the source 505 or the drain 506 and connected to the dummy metal 502c may be disposed on the second insulating layer 509. On the other hand, the pixel electrode 518 positioned above the second insulating layer 509 and the second gate metal 502b positioned below the second insulating layer 509 overlap each other in the major axis direction x. A capacitor cst is formed.

The common insulating layer 522 connected to the second gate metal 502b may be included on the second insulating layer 509. The common electrode 522 may be formed of any one of indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO), like the pixel electrode 518, but is not limited thereto.

The pixel electrode 518 and the common electrode 522 may be separately disposed on the second insulating layer 509 such that the electrodes divided from the long axis direction y extend in the short axis direction x.

In the above description, the pixel electrode 518 may be connected to the source 505 or the drain 506 through the first contact hole C1 and electrically connected to the dummy metal 502c through the third contact hole C3. Can be connected. The common electrode 522 may be electrically connected to the second gate metal 502b through the second contact hole C2.

On the other hand, the second gate metal 502b, the dummy metal 502c, the pixel electrode 518 and the common electrode 522, as shown in the "OR1" and "OR2" region, a part of the region where they overlap each other It may be formed in an L (L) shape having a slope on one plane.

As such, when a portion of the region where the second gate metal 502b, the dummy metal 502c, the pixel electrode 518, and the common electrode 522 overlap each other is formed as an L (L), the electric field is formed on the upper part of the subpixel and The lower region may be formed in a similar direction. In addition, when the L shape is formed at an inclination r of 90 ° to 160 °, the field directions of the pixel electrode 518 and the common electrode 522 may be uniformly arranged in the subpixel.

Here, the region having the inclination of the L (L) may correspond to the starting point of the region in which a part of the pixel electrode 518 and the common electrode 522 are divided in the long axis direction. Here, the overlapping region may correspond between the pixel electrode 518 and the dummy metal 502c and between the common electrode 522 and the second gate metal 502b in addition to the above-described region.

The dummy metal 502c may be located in an area that faces the minor axis direction x of the second gate metal 502b on one plane and may have a smaller minor axis direction area than the minor axis area of the second gate metal 502b. (See Figure 15)

As described above, the pixel electrode 518 is formed to be connected to the dummy metal 502c disposed under the second insulating layer 509, and the second gate metal 502b, the dummy metal 502c, and the pixel electrode ( If a portion where the 518 and the common electrode 522 overlap each other is formed as an L (L), the length of the pixel electrode 518 can be extended and inefficient driving between the pixel electrode 518 and the common electrode 522 can be achieved. This area can be reduced.

As described above, each embodiment of the present invention has a structure in which the electrode structure is changed to improve uniformity in the electric field direction, thereby reducing the disclination region and the inefficient driving region, and improving the transmittance and contrast ratio. Has the effect of providing. In addition, there is an effect that can solve the problem of unevenness caused by the panel touch.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention described above may be modified in other specific forms by those skilled in the art to which the present invention pertains without changing its technical spirit or essential features. It will be appreciated that it may be practiced. Therefore, the embodiments described above are to be understood as illustrative and not restrictive in all aspects. In addition, the scope of the present invention is shown by the claims below, rather than the above detailed description. Also, it is to be construed that all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention.

1 is an exploded perspective view of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an exemplary view of an edge type light source.

3 is a plan view of a sub pixel according to the first embodiment of the present invention;

4 is a cross-sectional view of region A1-A1 of FIG. 3;

5 is a cross-sectional view of the region B1-B2.

6 is an exploded view of FIG. 3;

7 is a plan view of a sub pixel according to the second embodiment of the present invention;

FIG. 8 is a cross-sectional view of region A2-A2 in FIG. 7; FIG.

9 is an exploded view of FIG. 7;

10 is a plan view of a sub pixel according to the third embodiment of the present invention;

FIG. 11 is a cross-sectional view of region A3-A3 in FIG. 10; FIG.

12 is an exploded view of FIG. 10;

13 is a plan view of a sub pixel according to the fourth embodiment of the present invention;

FIG. 14 is a cross-sectional view of region A4-A4 in FIG. 13; FIG.

15 is an exploded view of FIG. 13;

<Explanation of symbols on main parts of the drawings>

110, 210, 310, 410, 510: first substrate 202a, 302a, 402a, 502a: first gate metal

202b, 302b, 402b, 502b: second gate metal 202c, 302c, 402c, 502c: dummy metal

203,303,403,503: First insulating film 208,308,408,508: Data wiring

209,309,409,509: Second insulating film 218,318,418,518: Pixel electrode

222,322,422,522: common electrode

Claims (10)

A first substrate; A dummy metal disposed on the first substrate and disposed to face the first gate metal connected to the scan wiring, the second gate metal connected to the common voltage wiring, and the second gate metal so as to form a closed curve open on one plane; A first insulating layer on the first and second gate metals and the dummy metal; An active layer overlapping the first gate metal on the first insulating layer; A data line disposed along the long axis direction of the second gate metal on the first insulating layer, a source in contact with one end of the active layer and connected to the data line, and a contact with the other end of the active layer and separated from the source drain; A second insulating layer covering the data line, the source, and the drain on the first insulating layer; And And a pixel electrode connected to the source or drain on the second insulating layer, the pixel electrode connected to the dummy metal, and a common electrode connected to the second gate metal. A first substrate; A first gate metal on the first substrate and connected to the scan wiring, and a second gate metal connected to the common voltage wiring; A first insulating layer on the first and second gate metals; An active layer overlapping the first gate metal on the first insulating layer; A data line disposed along the long axis direction of the second gate metal on the first insulating layer, a source in contact with one end of the active layer and connected to the data line, and a contact with the other end of the active layer and separated from the source A dummy metal disposed to face the drain and the second gate metal so as to form a closed curve open on one plane; A second insulating layer covering the data line, the source, the drain, and the dummy metal on the first insulating layer; And And a pixel electrode connected to the source or drain on the second insulating layer, the pixel electrode connected to the dummy metal, and a common electrode connected to the second gate metal. The method according to claim 1 or 2, The second gate metal, the dummy metal, the pixel electrode and the common electrode, A portion of the area where these overlap each other is an L-shaped shape having an inclination on one plane. The method of claim 1, The dummy metal is, And the same material and the same process as the first gate metal or the second gate metal. The method of claim 2, The dummy metal is, And the same material and the same process as the source or the drain. The method according to claim 1 or 2, The dummy metal is, The liquid crystal display of claim 1, wherein the liquid crystal display is positioned in a region of the second gate metal opposite to the minor axis of the second gate metal and is narrower than the minor area of the second gate metal. The method according to claim 1 or 2, The dummy metal is, And a major axis and a minor axis area on one plane which are located in an area opposite the major axis and minor axis of the second gate metal and smaller than the major axis and minor axis area of the second gate metal. The method according to claim 1 or 2, The dummy metal is, The liquid crystal display device of claim 1, wherein the liquid crystal display has a long axis direction area that is positioned in a region of the second gate metal opposite to the long axis direction of the second gate metal. The method according to claim 1 or 2, The pixel electrode and the common electrode, And an electrode divided from the short axis direction extends long along the long axis direction. The method according to claim 1 or 2, The pixel electrode and the common electrode, And an electrode divided from the long axis direction extends along the short axis direction.

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