KR20090129161A - Structure of flash translation layer and prefetching method and asynchronous writing method based on the flash translation layer - Google Patents

Abstract

PURPOSE: A flash translation layer structure, pre-carrying method using the same, and asynchronous writing method based on the flash conversion layer structure are provided to predict address data which is frequency updated, thereby minimizing unnecessary repeated writing operation. CONSTITUTION: A flash translation layer structure is composed of the Fine-Grained clustered hash table of 1 step, the Fine-Grained clustered hash table of 2 step, and a Coarse-Grained clustered hash table. Information about successive PBA(Physical Block Address) is stored in the Coarse-grained clustered hash table. The flash translation layer structure comprises a continuity flag. The continuity flag minimizes repeated address translation mechanism according to the address translation request of successive LBA(Local Block Address) based on information about a physical address.

Description

Flash Transform Hierarchy Structure, Prefetch Method Using the Same, and Asynchronous Write Method Based on Flash Transformation Structure

The present invention relates to address translation performance and lifetime management of flash memory, and more particularly, provides continuous address translation performance through continuity flags and prefetching techniques, and flash memory through 2-bit write prediction and asynchronous write techniques. The present invention relates to a flash conversion hierarchy structure that can be efficiently managed, a prefetch method using the same, and an asynchronous write method based on the flash conversion structure.

Recently, with the introduction of large-capacity NAND flash memory every year, it is in the spotlight as a new storage device to replace magnetic disk in the future. The advantage of NAND flash memory is that it can be randomly accessed compared to a normal hard disk, and thus the input / output speed and shock resistance are useful for embedded systems or industrial systems. However, in addition to these advantages, magnetic disks and other physical characteristics are included as follows.

The first NAND flash memory consists of pages (512B, 2KB) and blocks (16KB, 128KB). Pages are the smallest unit of NAND flash memory. Generally, 32 pages constitute one block. Second, each block has a limit on the number of times it is updated, which is called wear. It is about 100,000 times in SLC (Single Level Cell) and about 10,000 times in MLC (Multi Level Cell). Third, the NAND flash memory is divided into three operations of read / write / delete. The read / write operation is in units of pages (512B, 2KB), but the erase operation is in blocks (16KB, 128KB). Fourth block delete is much slower than read / write because it erases 32 pages.

Therefore, the existing hard disk dedicated file system is designed without considering the characteristics of the NAND flash memory. Therefore, the compatibility with the existing file system and the NAND flash memory is performed through a middleware called a FTL (Flash Translation Layer). Should be. The role of FTL is as follows.

First, since in-place update requires erasing before writing, the deletion cost is very high. Therefore, the NAND flash memory performs an out-place update instead of an in-place update. Each time an external update is performed, the logical address of the file system (LBA) and the physical block address (PBA) of the flash memory mapped to each other are updated, so the address translation table function is included. Second, it has the function of leveling the wear of all blocks in order to use NAND flash memory for a long time. Third, since the erase speed is slower than read and write, it includes a garbage collection function that deletes invalid blocks of flash memory in a batch.

Meanwhile, as described above, in order to reduce the size of the address translation table, which is the biggest disadvantage of the page-based address translation scheme, a block-based address translation scheme has recently been applied. For example, an NFTL scheme exists. Here, NFTL is an NTL dedicated FTL designed by M-Systems. That is, as shown in FIG. 1, the value of the Logical Block Address (LBA) is divided by the number of pages per block, and the quotient is used as a VBA (Virtual Block Address), and the remaining value is used as an index. When accessing the address translation table, the VBA value is used to access the entry containing the addresses of the primary block and the replacement block.

First, if the main block PBA exists, the page-by-page access is attempted with the remaining block offset. However, if the data of the PBA corresponding to the main block is not valid, the technique of searching each page sequentially by accessing the address of the replacement block again. This is called NFTL's block address conversion technique. In block-based address translation, the size of the address translation table is small, but there is an overhead of re-scanning the replacement block sequentially if the address retrieval fails in the main block.

Meanwhile, as another example of an address translation method, there is an AFTL method, which is an FTL proposed by the National Taiwan University, and is composed of an address translation table of two units, a coarse-grained hash table and a fine-grained hash table, as shown in FIG. 2. have.

By default, coarse-grained hash tables use block-level address translation techniques like NFTL, and fine-grained hash tables use page-level address translation techniques such as FTL. In case of using the page address conversion method, if the replacement block data is valid, it is assumed that the data can be frequently used in the future, and stored in the fine-grained hash table to convert the address by page.

In the case of the main block, the coarse-grained hash table is used because it is directly found using the offset. Due to the limitation of the size of fine-grained hash tables, a replacement technique between fine-to-coarse is required, and the technique used here uses the technique of applying LRU to move unused slots to a coarse-grained hash table for a certain period of time. .

However, the hash table applied in the above-described NFTL method and AFTL method has a disadvantage in that flexibility is lacked because the address translation speed is always fixed, and the tag and next pointers are additionally required for each node to use memory. There is a problem in that about 200% overhead occurs.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a continuity flag for storing information about consecutive physical addresses, thereby reducing the number of repetitive address translations and thus address translation of a coarse-grained clustered hash table. The present invention provides a preloading method for a flash translation layer that can improve performance.

Another object of the present invention is an asynchronous write method based on a write-through method for a flash translation layer that can minimize unnecessary repetitive write operations that increase the lifespan of a flash memory by predicting address data with frequent updates. In providing.

Flash conversion hierarchy according to an aspect of the present invention for achieving the above object is a flash conversion layer consisting of a first stage fine-grained clustered hash table, a second stage fine-grained clustered hash table and a coarse-grained clustered hash table In the (FTL) structure, the Coarse-grained clustered hash table stores information about consecutive physical block addresses (PBAs) and consecutive LBAs based on the information about the physical addresses. A continuity flag is included to minimize the repetitive address translation mechanism according to the address translation request.

In addition, a preloading method for a flash translation layer according to an aspect of the present invention for achieving the above object comprises the steps of: a) storing a contiguous LBA and its corresponding PBAs in the same bucket as a clustered hash table; b) accepting a read request for an LBA in the bucket; c) performing address translation of consecutive LBAs based on the continuity flag mounted as a coarse-grained clustered hash table; d) pre-loading the entire page of the bucket to which the LBA belongs.

Specifically, step c) may include c-1) searching for the first fine-grained clustered hash table and ending address translation when there is a matching PBA; c-2) searching for the second fine-grained clustered hash table if the search fails in the first fine-grained clustered hash table, and ending address translation when there is a matching PBA; And c-3) searching for matching address translation information in the coarse-grained clustered hash table when the search fails in the second fine-grained clustered hash table.

On the other hand, the asynchronous write method based on a pre-write method for a flash translation layer according to an aspect of the present invention for achieving the above object, a) generating a prediction table in which any information is stored; b) adding a VBA containing a repeatedly stored LBA to the prediction table; c) updating a prediction bit stored in the prediction table in proportion to the number of write requests, each time a write request enters an LBA belonging to the same VBA; d) storing the VBA in a reservation buffer when the prediction bit is updated to a preset value; And e) loading only the latest data loaded into the reservation buffer into the flash memory when the reservation buffer is saturated.

The write-in and asynchronous write method for the flash translation layer according to the present invention has the effect of leading the research in related fields and contributing to the activation of subsequent studies by suggesting practical algorithm implementation and policy for FTL suitable for flash memory. have.

In addition, the present invention can maintain a unique position in the global memory semiconductor field through technology research and development on software related to NAND flash memory, and furthermore, it can be sufficiently applied to future next-generation nonvolatile memory such as nonvolatile random access memory (NVRAM). As a result, the company can achieve global competitiveness by increasing sales and securing proprietary technology.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

First, the address translation table technique disclosed in the present invention uses a clustered hash table that is less memory-intensive than a general hash table and is suitable for large-capacity address translation. Hereinafter, the address translation table scheme is referred to as a clustered flash translation layer (CFTL) method. In the CFTL method according to the present invention, a fine-grained clustered hash table is designed in two stages while using a block and page address translation table technique to reduce miss penalty, thereby improving address translation speed. It also improves continuous address translation performance with Continuity Flag and Prefetch and improves flash memory life and performance through write delay using 2-bit access prediction.

Next, the prefetching procedure for the above-described flash translation layer will be described. FIG. 3 is a diagram illustrating an address translation table technique of a CFTL method applied as a prefetching procedure for a flash translation layer, and FIG. 4 is a flowchart illustrating a prefetching procedure for a flash translation layer using the CFTL method.

As shown, a clustered hash table is a combination of a linear table technique and a hash table, such as a one-step fine-grained clustered hash table that groups similar addresses into the same bucket, and a translation lookaside buffer (TLB). Borrowing a cache, a two-stage fine-grained clustered hash table that minimizes miss penalties and reduces the frequency of access to coarse-grained clustered hash tables with relatively high address translation overhead, and continuous LBA with continuity flags. It consists of coarse-grained clustered hash table that reduces the address translation burden when requesting address of (Logical Block Address).

Based on this configuration, when the requested LBA exists in the fine-grained clustered hash table, address translation is performed by pre-loading all pages of the bucket to which the LBA belongs, thereby performing address translation performance. Let's do it.

Here, the first-level fine-grained clustered hash table is a clustered hash table that uses a combination of a linear table technique and a hash table. The memory usage is less than that of the existing hash table, and similar addresses are grouped in the same bucket. It can be secured.

Therefore, when an address translation request of a specific LBA comes in from the host, the first step is to search the first-level fine-grained clustered hash table, and if a matching PBA is found, the address translation is terminated, and the first-level fine-grained clustered hash table is searched. If it fails, address translation is terminated by searching the second-level fine-grained clustered hash table to find a matching PBA.

On the other hand, if the search fails even in the second-level fine-grained clustered hash table, address matching information is finally found in the coarse-grained clustered hash table. Coarse-grained clustered hash tables, like NFTL, first convert LBAs to VBAs and offsets. Hashing the obtained VBA to find the bucket that stores the address of the PPBA (Primary Physical Block Address) and RPBA (Replacement Physical Block Address). If the page data at the matched PPBA and offset is not valid, the RPBA is sequentially searched to find the corresponding physical address.

In addition, the aforementioned two-stage fine-grained clustered hash table requires movement between Coarse-to-Fine or Fine-to-Coarse, and as a policy for this, promotion and demotion policies are applied. In other words, when moving to coarse-to-fine, if the frequency of access increases a certain number of times due to frequent access to a specific LBA, a promotion policy is first applied to a two-stage fine-grained clustered hash table, or NUR technique is used. This allows a demotion policy to demote from a fine-grained clustered hash table to a coarse-grained clustered hash table if there is no access for some time. On the other hand, after the promotion policy is executed, the access frequency is initialized, and the policy is equally applied to the first-level fine-grained clustered hash table.

Therefore, a two-stage fine-grained clustered hash table can be used to reduce miss penalties, reduce the frequency of access to coarse-grained clustered hash tables, and address translation time because most of the address translation is done in fine-grained clustered hash tables. Can be reduced.

The NUR technique is a method that can identify slots that are not used recently according to bits at predetermined periods in the system by using a bit vector called a modified bit. Therefore, it is applied to the fine-to-coarse replacement technique as shown in Table 1 by determining whether the situation is referenced through the two bits and whether the modification has been made.

Reference bits Fix bit Policy 0 0 Demote to Coarse 0 One Keep state One 0 Keep state One One Keep state

That is, as shown in Table 1, when the NUR reference and modification bits of a specific address are all 0, the address is not used, and it is moved from the fine-grained clustered hash table to the coarse-grained clustered hash table. Delete slots from fine-grained clustered hash tables.

Next, a method of prefetching pages of PBAs indicated by subblocks of a specific bucket of the clustered hash table illustrated in FIG. 4 will be described.

First of all, unlike the commonly used method, that is, address translation and data transfer for each LBA request by FTL, the prefetching technique for successive pages according to the present invention is a bucket in a fine-grained clustered hash table. It is to fetch pages with consecutive LBAs in them.

In other words, the clustered hash table, which is a data structure used in the address translation scheme, stores contiguous LBAs and corresponding PBAs in the same bucket, and selects physical pages of adjacent subblocks when a read request for an LBA of a specific bucket is made. It can be brought in. Thus, not only does it prevent repetitive memory loading and issuance of instructions to the flash memory every hour, but also a plurality of pages are loaded, thereby reducing the speed of a read operation at the next read.

The clustered hash table is an address translation data structure used in CFTL, and is a data structure first used in the virtual memory page technique of Solaris, which is a 64-bit operating system of Sun Microsystems, and consists of a bucket, which is a set of subblocks. Here, the number of subblocks in one bucket is called a subblock factor. Unlike a general hash table, since there are several subblocks in one bucket, the memory usage of a pointer per address is 1 / (subblock factor). It can be reduced by).

Therefore, since data that is used continuously and simultaneously is continuously stored in sub-blocks of one bucket, it is very useful for maintaining locality in the address translation table, and is applied to the address translation data structure in the present invention.

Meanwhile, in the present invention, a continuity flag is added to each subblock of each bucket of the coarse-grained clustered hash table described above. When the VBA and the PBA are contiguous together, the continuity flag is added. The number is written to the value of the continuity flag. This allows for address translation as well as acquiring PBA without having to repeat the address translation mechanism again. As a result, since the fine-grained clustered hash table is composed of LBAs with high access frequency as independent tables, address retrieval time is improved to improve address translation performance, and the PBA data pointed to by the subblocks of the bucket is pre-main memory. Improves address translation performance.

Here, the continuity flag described above, that is, the continuity flag applied to the address translation method when the address of the continuous LBA is requested is a 'C' value stored in the subblocks shown in the coarse-grained clustered hash table of FIG. 3. Along with the contiguous VBA, the physical block is also used to write the number of contiguous blocks in C, the continuity flag in the contiguous case, which enables address translation without repeating the address translation mechanism again. For example, if the VBA is 128, the PPBA is 386, and the continuity flag is 8, the increment value of VBA is 8 or less.

7 is a graph comparing the performance of the CFTL according to the present invention. The CFTL environment was tested using the Linux 2.6.17 MTD (Memory Technology Device). For the performance evaluation, the ratio of slots in the first stage fine-grained clustered hash table and the second stage fine-grained clustered hash table is 1 Assigned to: 4. For example, if the number of Maximum Short Fine-Grained Slots (MSFS) is 1000, this means that the number of Maximum Long Fine-Grained Slots (MLFS) is 4000. For the experiment, the subblock factor of the clustered hash table, that is, the number of subblocks is set to 8, the MSFS is set to 2500, and the MLFS is set to 10,000. 2-bit write prediction scheme The number of slots in the prediction table is set to 1024, 2048, 4096.

Here, we used the Andrew benchmark, which is a well-known way of evaluating storage performance, to measure address translation time and overall performance of the FTL. Andrew benchmarks fall into five stages: 1) directory creation, 2) data copying, 3) recursive file search, 4) file access, and 5) compilation. These tests are useful for verifying read / write performance on storage devices. As shown, averaging 10 values shows that CFTL's address translation speed is about 13% faster than NFTL and about 8% faster than AFTL. In addition, the application of continuity flags and prefetching techniques resulted in more than 17% better performance than NFTL and 11% better than AFTL due to the prediction of consecutive addresses.

Moreover, when comparing the size of the CFTL address translation table, it can be seen that the memory usage of the address translation table is reduced. As shown in Table 2, when comparing the size of the address translation table of NFTL, AFTL, and CFTL with subblock factor of 8, it can be seen that CFTL reduces the address translation table memory usage by up to 43% or more than AFTL. . In addition, setting the CFTL subblock factor to 32 indicates that memory usage can be saved up to 65%.

MFS NFTL AFTL CFTL 500 + 2,000 64.0 KB 201.8 KB 78.1 KB 1,000 + 4,000 64.0 KB 211.5 KB 84.2KB 1,500 + 6,000 64.0 KB 221.3 KB 90.3 KB 2,000 + 8,000 64.0 KB 231.1 KB 96.4 KB 2,500 + 10,000 64.0 KB 240.8 KB 102.5 KB 3,000 + 12,000 64.0 KB 250.6 KB 108.6KB

Meanwhile, in the present invention, when the PBA data is pre-loaded into the main memory to perform address translation, the frequently updated data is first stored using the write buffer instead of directly stored in the flash memory. This is to extend the life of the flash memory and to minimize repetitive write operations. In the present invention, this writing method will be referred to as '2-bit write prediction'.

The 2-bit write prediction classifies four states for prediction. FIG. 5 is a diagram for describing a 2-bit write prediction technique, and FIG. 6 is a diagram for explaining an asynchronous writing method using FIG. 5. This will be described with reference to the following.

First, the VBA including the repeatedly stored LBA is added to the prediction table, and then the prediction bit is updated whenever a write request is made to an LBA belonging to the same VBA. If the prediction bits are 10 or 11, it is determined that the VBA is frequently updated, and the updated page is loaded into the reserved buffer of RAM.

When the prediction bit is changed to 00, 01, only the latest data of the data in the reservation buffer is stored in the flash memory. When the 2-bit write prediction technique is applied, the prediction table is updated in the order in which write requests are received. Represents four states with two bits and stores the VBA (Virtual Block Address), which is determined to be a Predict written state with bits 10 and 11, in the reservation buffer, and then the Predict not written with the reservation buffer full or with prediction bits 00 and 01. In the state, only the latest data in the reservation buffer is merged and loaded into the flash memory. This write delay technique can improve the lifespan of flash memory by reducing the number of writes to flash memory and has a great effect on maintaining the locality of data.

8 to 10 are graphs showing the lifespan of a flash memory according to the 2-bit write prediction technique described above. In the experiments according to the present invention, the focus was on reducing the number of flash memory writes using the 2-bit write prediction technique and the write buffer. Reducing the number of writes has two advantages.

First, it has a reduction in wear, a measure of the lifetime of flash memory, and a second decrease in the number of executions of the block collection technique that executes with writes due to the decrease in the number of writes. Therefore, 2-bit write prediction techniques can improve memory life and performance very efficiently. 8 shows the results of experiments focused on deleting and overwriting existing files. Finally, FIG. 9 shows the results of experiments of repeatedly adding data to an existing file.

In the case of the Andrew benchmark described above, since the file access patterns have various file access patterns, they are not affected by the write applied by the 2-bit write prediction technique. However, in overwrite and append, the number of writes decreases in proportion to the size of the 2-bit write prediction table, and CFTL with 4096 slots in the prediction table reduces the number of writes by up to 60% over NFTL and AFTL. .

FIG. 10 shows the write time of CFTL using the existing NFTL, AFTL, and 2-bit write prediction techniques according to Andrew benchmark, update, and test, respectively. As a result, CFTL reduced write time by more than 10% in the Andrew benchmark and over 30% in the overwrite and append operation benchmarks compared to NFTL and AFTL. The shortened results also demonstrate that it can be used to reduce the overhead of block collection techniques.

Here, looking at the memory usage used in the 2-bit write prediction scheme according to the present invention, when the number of slots in the prediction table is 1024, 2048, 4096, respectively, as shown in Table 3, the size of the table increases to 8KB, 16KB, 32KB. The memory usage used by the write buffer is increasing to 512 KB, 1 MB, and 2 MB, respectively.

Number of slots Memory usage Write buffer size 1024 8 KB 512 KB 2048 16 KB 1 MB 4096 32 KB 2 MB

As a result, through the asynchronous write method using the 2-bit write prediction method according to the present invention, it is proved that the prewrite and asynchronous write methods are 17% faster than the existing NFTL in address translation performance and about 30% improved in the write performance. .

As described above, the present invention can be applied to all fields that require NAND flash memory, it will be possible to commercialize as a core technology that supports the technology of NAND flash of domestic companies. In recent years, growth in NAND flash memory is expected to grow from 130% to 140% in 2008, as demand from major products such as mobile handsets, MP3 devices / personal media players, digital cameras, and USB flash drives is growing significantly. Most suppliers are aggressively pursuing the transfer of node processes while increasing manufacturing output, which is expected to balance supply and demand in 2H08.

In addition, demand for mobile handset manufacturers is expected to grow 10 percent year-over-year to $ 1.23 billion. The next major area of growth will be MP3 / PMP devices, which will grow by 20% to $ 200 million, followed by USB flash drives by 25% annually, to $ 170 million. Digital camera market growth is expected to reach 14% to $ 130 million this year.

Recently, NAND flash memory manufacturers and portable storage device manufacturers, such as Samsung Electronics and Hynix, have been increasing interest in flash memory software to improve the performance of flash memory software and release high quality hardware. It is expected. Therefore, it is determined that the industrial utilization value of the NAND memory management method according to the present invention is extremely high.

1 and 2 are diagrams for explaining a conventional address translation technique.

3 is a diagram illustrating an address translation table scheme of a CFTL method applied as a prefetching procedure for a flash translation layer according to the present invention.

FIG. 4 is a flowchart illustrating a preloading procedure for a flash translation layer using the CFTL method of FIG. 3.

5 is a diagram for describing a 2-bit write prediction technique applied to the present invention.

FIG. 6 is a diagram for describing an asynchronous writing method using FIG. 5.

7 is a graph comparing the performance of the CFTL according to the present invention.

8 to 10 are graphs showing the lifespan of a flash memory according to the 2-bit write prediction technique described above.

Claims (10)

In a flash translation hierarchy (FTL) structure consisting of a first-level fine-grained clustered hash table, a second-level fine-grained clustered hash table, and a coarse-grained clustered hash table, Stores information about consecutive physical block addresses (PBAs) as the coarse-grained clustered hash table, and based on the address translation request of consecutive LBAs based on the information about the physical addresses. A flash translation hierarchy, comprising a continuity flag to minimize repetitive address translation mechanisms. The method of claim 1, The continuity flag is a flash translation layer structure, characterized in that the number of consecutive blocks is written when the VBA (Virtual Block Address) and PBA (Physical Block Address) is continuous. The method according to claim 1 or 2, And the continuity flag is set for each subblock of each bucket of the coarse-grained clustered hash table. The method according to claim 1 or 2, And the flash conversion is NAND flash memory based. In the page prefetch method using the flash conversion hierarchy according to claim 1, a) storing contiguous LBAs and corresponding PBAs in the same bucket as the clustered hash table; b) accepting a read request for an LBA in the bucket; c) performing address conversion of consecutive LBAs based on the continuity flag mounted as the coarse-grained clustered hash table; d) prefetching an entire page of the bucket to which the LBA belongs; and a prefetch method using a flash translation hierarchy. The method of claim 5, wherein step c) c-1) searching for the first fine-grained clustered hash table and ending address translation when there is a matching PBA; c-2) searching for the second fine-grained clustered hash table if the search fails in the first fine-grained clustered hash table, and ending address translation when there is a matching PBA; And c-3) searching for matching address translation information in the coarse-grained clustered hash table when the second stage fine-grained clustered hash table fails to search. Prefetch method used. According to claim 6, wherein step c-3), A) converting an LBA to an offset with a VBA in the coarse-grained clustered hash table; B) hashing the VBA to find a bucket in which the addresses of PPBA and RPBA are stored; And C) sequentially searching the RPBA to find a corresponding physical address when the matched page data at the PPBA and the offset is not valid; In the flash memory write method based on the flash conversion structure, a) generating a prediction table in which any information is stored; b) adding a VBA containing a repeatedly stored LBA to the prediction table; c) updating a prediction bit stored in the prediction table in proportion to the number of write requests, each time a write request enters an LBA belonging to the same VBA; d) storing the VBA in a reservation buffer when the prediction bit is updated to a preset value; And and e) loading only the latest data loaded into the reservation buffer into the flash memory when the reservation buffer is saturated. The method of claim 8, And the prediction bit is a two-bit structure for displaying at least four states. The method of claim 8, And the latest data loaded into the reserved buffer is data obtained by collectively merging the VBA.

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