KR20090123550A - Method of manufacturing a flash memory device - Google Patents

Abstract

PURPOSE: A method for manufacturing a flash memory device is provided to prevent plasma damage about a sidewall of gate lines by covering the sidewall of gate lines with one of an oxide layer, a TEOS layer, and an SiN layer before a reactive ion etching process. CONSTITUTION: An isolation region(315) for isolating the device is formed on a semiconductor substrate(310). Gate lines(340) are formed on the semiconductor substrate with the device isolation region. A spacer insulation layer(350) is deposited on the semiconductor substrate to surround the gate lines. A photoresist film pattern(355) is formed on a spacer insulation layer to expose the region to form a common source between gate lines. A trench(350) is formed by reactive-ion etching the spacer insulation layer and the device isolation region using the photoresist film pattern as a mask. A common source is formed on the semiconductor substrate of the lower part of the trench by performing the ion implantation process in the trench.

Description

Method of manufacturing a flash memory device

The present invention relates to an apparatus for manufacturing a semiconductor device, and more particularly, to a method of manufacturing a flash memory device capable of preventing damage to sidewalls of gate lines by plasma when forming trenches for forming a common source.

In general, as the high integration of semiconductor circuits becomes more competitive, cell size reduction is indispensable, and thus efforts to implement microcircuits continue.

Although there is a method of connecting a contact to each unit cell when forming a source layer in a flash memory device, this method is not suitable for highly integrated devices because a contact margin must be considered. Recently, many common source lines have been applied to realize high integration of flash memory devices.

Self-aligned technologies such as Self Aligned Contact (SAC) and Self-Aligned Shallow Trench Isolation (SA-STI) play a critical role in minimizing the cell size of semiconductor devices. Recessed Common Source (RCS) refers to one of processes for forming a common source line of a flash memory device in a self-aligned source (SAS) manner. That is, RCS is a process of removing the isolation material of the STI and forming a common source through the ion implantation process.

1 shows a layout of a typical flash memory cell. Referring to FIG. 1, a plurality of trench lines 3 corresponding to device isolation regions are formed on a substrate, and the trench lines 3 are parallel to the bit lines BL and 5 of the flash memory cell. . A plurality of gate lines 12 and 14 are formed in a direction perpendicular to the trench line 3, that is, in a direction parallel to the word line WL of the flash memory cell.

Impurity ions are implanted in the direction of the word line WL to form a common source region 20. A drain region is formed in the active region opposite to the common source region based on the gate lines 12 and 14.

FIG. 2A is a cross-sectional view of the layout of FIG. 1 taken along line AA ′, and FIG. 2B is a cross-sectional view of the layout of FIG. 1 taken along line BB ′.

As shown in FIG. 2B, the STI technique is used to define the active region 5 and the device isolation region 3 on the semiconductor substrate. The STI technology is a method of etching a silicon substrate to form a trench and gapfilling a field oxide layer in the trench.

Next, referring to FIG. 2A, gate lines 12 and 14 are formed on a semiconductor substrate in which an active region 5 and a device isolation region 3 are defined, as shown in FIG. 2B. The gate lines 12 and 14 may be formed by stacking a tunnel oxide layer 210, a floating gate pattern 215, an ONO layer (Oxide-Nitride-Oxide film 220), and a control gate pattern 230. .

The common source region 20 is formed by removing a field oxide between the gate lines 12 and 14 to form a trench and implanting an ion into the formed trench. In this case, a photoresist pattern (not shown) is formed on the semiconductor substrate to exclude the common source region so as to form the common source 20, and the device isolation material, that is, a field oxide layer, is formed using the photoresist pattern (not shown) as a mask. The trench is formed by etching a reactive oxide (field oxide).

When reactive ion etching the field oxide layer, side surfaces of the control gate and sidewalls of the ONO layer may be damaged. Such damage may cause a change in the coupling ratio of the flash memory, thereby degrading the reliability of the flash memory device.

An object of the present invention is to provide a method of manufacturing a flash memory device capable of preventing the gate line from being damaged by the plasma by the reactive ion etching during the RCS process.

In accordance with another aspect of the present invention, there is provided a method of manufacturing a flash memory device, the method comprising: forming an isolation region for device isolation on a semiconductor substrate, and forming gate lines on the semiconductor substrate on which the device isolation region is formed; Depositing a spacer insulating film on the semiconductor substrate to surround the gate lines, forming a photoresist pattern on the spacer insulating film to expose a region where a common source is to be formed between the gate lines, and the photoresist film Forming a trench by reactive ion etching the spacer insulating layer and the device isolation region using a pattern as a mask, and forming a common source on the semiconductor substrate under the trench by performing an ion implantation process on the trench do.

The method of manufacturing a flash memory device according to an embodiment of the present invention covers the sidewalls of the gate lines with at least one of an oxide film, a TEOS film, and a SiN film before performing a reactive ion etching process to form a trench for forming a common source. Plasma damage to the side walls of the lines can be prevented, thereby improving the reliability of the flash memory device.

Hereinafter, the technical objects and features of the present invention will be apparent from the description of the accompanying drawings and the embodiments. Looking at the present invention in detail.

3A to 3F are cross-sectional views illustrating a method of manufacturing a flash memory device according to an embodiment of the present invention. 3A to 3F are cross-sectional views taken along the line C-C 'of the layout shown in FIG.

As shown in FIG. 3A, a shallow trench isolation (STI) process is performed on the semiconductor substrate 310 to form a device isolation region 315 for device isolation. That is, a first photoresist pattern (not shown) is formed on the semiconductor substrate 310 to form the device isolation region through a photolithography process.

Subsequently, the semiconductor substrate 310 is etched using the first photoresist pattern (not shown) as a mask to form a trench, and then a field oxide layer is gapfilled with a device isolation material in the trench to form the trench. 315).

Next, as shown in FIG. 3B, gate lines 340 and 345 having a stack structure are formed on the semiconductor substrate 310 on which the device isolation region 315 is formed.

For example, the tunnel oxide layer 320, the floating gate poly 325, the ONO layer (Oxide-Niride-Oxide film) 330, and the control gate poly 335 are sequentially formed on the semiconductor substrate 310.

Subsequently, a photolithography process is performed on the control gate poly 335 to form a second photoresist pattern (not shown). The second photoresist layer pattern (not shown) may be patterned to expose the control gate poly 335 corresponding to the active region of the semiconductor substrate. The control gate poly 335, the ONO layer 330, the floating gate poly 325, and the tunnel oxide layer 320 are sequentially etched using the second photoresist pattern as a mask to form the gate lines ( 340 and 345 may be formed.

The method of forming the gate lines 340 and 345 shown in FIG. 3B is merely one embodiment of the present invention, but is not limited thereto.

Next, as shown in FIG. 3C, a spacer spacer insulating layer 350 is formed on the semiconductor substrate 310 on which the gate lines 340 and 345 are formed. The spacer spacer insulating layer 350 may be formed by performing a spacer process to cover the top and sidewalls of the gate lines 340 and 345.

For example, the spacer spacer insulating layer 350 may be formed through an etch back process after depositing a spacer insulating layer. In this case, the spacer spacer insulating layer 350 may also be formed on the device isolation region between the gate lines 340 and 345.

In this case, at least one of an oxide film, a TEOS, and a SiN film may be deposited on the spacer spacer insulating film 350. In addition, the deposition thickness may be 100 ~ 350 ~, the deposition temperature during the deposition process may be 500 ℃ to 700 ℃.

Next, as shown in FIG. 3D, a third photoresist layer pattern 355 is formed on the spacer insulation layer 350 through a photolithography process. The third photoresist layer pattern 355 exposes the spacer spacer insulation layer 350 on the device isolation region 315-1 between the gate lines 340 and 345.

Next, as shown in FIG. 3E, the spacer spacer insulating layer 350 on the device isolation region 315-1 between the gate lines 340 and 345 using the third photoresist pattern 355 as a mask. ) And the device isolation region 315 beneath it are formed to form a trench 360 by reactive ion etching (RIE).

The spacer spacer insulating layer 350 covering the top and sidewalls of the gate lines 340 and 345 during the reactive ion etching process may remove sidewalls of the gate lines 350 and 345 from plasma damage caused by the reactive ion etching. Protect. That is, the tunnel oxide films 320-1 and 320-2, the floating gate polys 325-1 and 325-2, the ONO films 330-1 and 330-2, and the control gate poly Do not damage the sides of 335-1, 335-2).

Next, as illustrated in FIG. 3F, ions are implanted into the semiconductor substrate 310 on which the trench 360 is formed by using the third photoresist pattern 355 as a mask, and are common to the semiconductor substrate below the trench 360. Source 365 is formed. For example, the common source 365 may be formed in a semiconductor substrate adjacent to the bottom and side surfaces of the trench 360.

Ion implantation to form the common source 365 may be performed as follows. First, ions are first implanted using the third photoresist pattern 355 as a mask in a direction perpendicular to the lower surface of the trench 360. Next, the common source 365 may be formed by implanting ions into the side surface of the trench 360 using a gradient ion implantation method.

 Unlike the conventional method of manufacturing a flash memory device, an oxide film, a TEOS film, and a sidewall of the gate lines 340 and 345 are formed before the reactive ion etching process for forming the trench 360 is performed. Cover with at least one of the SiN films.

Accordingly, the tunnel oxide films 320-1 and 320-2, the floating gate polys 325-1 and 325-2, the ONO films 330-1 and 330-2 by plasma damage due to reactive ion etching. And side surfaces of the control gate pulleys 335-1 and 335-2 are not damaged.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 shows a layout of a typical flash memory cell.

FIG. 2A is a cross-sectional view of the layout of FIG. 1 taken along the line AA ′. FIG.

FIG. 2B is a cross-sectional view of the layout of FIG. 1 taken along the line BB ′. FIG.

3A to 3F are cross-sectional views illustrating a method of manufacturing a flash memory device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

310: semiconductor substrate, 315: device isolation region,

320: tunnel oxide film, 325: floating gate poly,

330: ONO film, 335: control gate pulley,

350: insulating film, 335: photosensitive film pattern,

360: trench, 365: common source.

Claims (5)

Forming an isolation region for device isolation in the semiconductor substrate; Forming gate lines on a semiconductor substrate on which device isolation regions are formed; Depositing a spacer insulating film on the semiconductor substrate to surround the gate lines; Forming a photoresist pattern on the spacer insulating layer to expose a region where a common source is to be formed between the gate lines; Forming a trench by reactive ion etching the spacer insulating layer and the device isolation region using the photoresist pattern as a mask; And And forming a common source in the semiconductor substrate under the trench by performing an ion implantation process on the trench. The method of claim 1, wherein the depositing of the spacer insulating layer comprises: And depositing at least one of an oxide film, a TEOS film, and SiN so as to surround the gate lines. The method of claim 1, The spacer insulating film is a method of manufacturing a flash memory device, characterized in that formed in a thickness of 100 ~ 350Å. The method of claim 1, wherein forming the common source comprises: Implanting ions in a direction perpendicular to a lower surface of the trench using the photoresist pattern as a mask; And And implanting ions into a side surface of the trench by a gradient ion implantation method using the photoresist pattern as a mask. The method of claim 1, And wherein the common source is formed in a semiconductor substrate adjacent to the bottom and side surfaces of the trench.

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