KR20090123510A - Method of operating a non volatile memory device - Google Patents

Abstract

PURPOSE: An operation method of a non-volatile memory device is provided to reduce a program time by integrating a voltage change process of selection bit lines and a pre-charge process of a non-selection bit line. CONSTITUTION: A program instruction is inputted to a non-volatile memory device(S301). A controller pre-charges non-selection bit lines. The controller changes voltage of operation and selection bit lines according to a data state of a second latch(303). The controller applies variable voltage at a power voltage level. The controller applies an odd bit line discharge control signal at a high level. The controller applies an even bit line selection signal, a sensing control signal, and a second data transmission signal at a high level. Flag information for controlling a progress of a program of a multi-level cell is stored in a node. The program is proceeded by applying program voltage to a word line(S305,S307).

Description

Method of operating a non volatile memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the operation of a nonvolatile memory device, and more particularly to a method of operating a nonvolatile memory device that simplifies the method of precharging a bit line voltage during a program operation.

Flash memory, which is a nonvolatile memory, is generally classified into a NAND flash memory and a NOR flash memory. NOR flash memory has a good random access time characteristic because memory cells are independently connected to bit lines and word lines, whereas NAND flash memory has a plurality of memory cells connected in series so that one contact per cell string is provided. Since only requires, it has excellent characteristics in terms of integration degree. Therefore, a NAND structure is mainly used for highly integrated flash memory.

Well known NAND flash memory devices include memory cell arrays, row decoders, and page buffers. The memory cell array includes a plurality of word lines extending along rows and a plurality of bit lines extending along columns and a plurality of cell strings corresponding to the bit lines, respectively.

1 is a flowchart of a program operation of a nonvolatile memory device.

Referring to FIG. 1, the nonvolatile memory device precharges unselected bit lines according to the program command S101 (S103).

When the program command is input, address information to be programmed and data to be programmed are input together. The nonvolatile memory device selects an even bit line or an odd bit line using address information, and selects a word line to execute a program.

At this time, the bit lines are precharged to prevent the memory cells connected to the unselected bit lines from being programmed. To this end, the nonvolatile memory device precharges the voltage VIRPWR to unselected bit lines in the bit line selection circuit connected to the page buffer.

In a nonvolatile memory device, a voltage of a bit line including a memory cell for programming is 0V, and a bit line including a memory cell that should not be programmed is precharged to a power supply voltage level to prevent program.

After precharging the unselected bit lines, the bit line voltage is changed according to the state of data to be programmed in the memory cell connected to the selected bit line (S105). In general, a memory cell having '1' data is in an erased state, and a memory cell having '0' data is programmed.

Therefore, among the memory cells connected to the selected bit lines, the bit line connected to the memory cell to which '1' data is to be input is precharged to the power supply voltage level, and the bit line connected to the memory cell to which the '0' data is to be input is 0V. Make it.

When the bit line voltage change of steps S103 and S105 is completed, a program voltage is applied to the word line to proceed the program (S107 and S109).

In such a program operation, a process of precharging unselected bit lines and a process of changing a voltage of selected bit lines according to a data state of a memory cell are independently performed.

Accordingly, an aspect of the present invention is to provide a method of operating a nonvolatile memory device capable of simultaneously performing precharge of an unselected bit line and changing a selected bit line voltage when a program is executed.

Method of operating a nonvolatile memory device according to a feature of the present invention,

Receiving data to be programmed according to a program command; Changing the voltage of the first bit line selected for programming the data according to the data state to be programmed and simultaneously precharging the unselected second bit line; And proceeding with the data program.

The voltage of the first bit line is precharged to a power supply voltage when the data to be programmed is the first logic level, and becomes 0 V when the data to be programmed is the second logic level.

After changing the voltage of the first bit line, the first bit line voltage is changed according to pre-stored flag information.

The second bit line is precharged by the variable voltage of the page buffer.

Method of operating a nonvolatile memory device according to another aspect of the present invention,

Receiving a program command and address information, and receiving data to be programmed into a page buffer; Changing a first bit line voltage selected according to the address information according to data stored in a page buffer, and simultaneously precharging a second bit line voltage not selected; Changing the voltage of the first bit line according to flag information stored in the page buffer; And performing a program by applying a program voltage to the selected word line.

The voltage of the first bit line is precharged to a power supply voltage when the data to be programmed stored in the page buffer is the first logic level, and becomes 0 V when the data to be programmed is the second logic level. .

Method of operating a nonvolatile memory device according to another aspect of the present invention,

Performing an erase and performing a verification; According to a soft program command, changing the selected first bit line voltage according to the data stored in the page buffer, and simultaneously precharging the unselected second bit line voltage; And performing a soft program.

The first bit lines are all precharged to a power supply voltage level.

As described above, the method of operating the nonvolatile memory device according to the present invention may shorten the program time by integrating the precharging of the unselected bit lines during the program operation and changing the voltage of the selected bit lines. .

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

2A is a block diagram of a nonvolatile memory device.

2A, the flash memory device 200 may include a memory cell array 210, a page buffer unit 220, a Y decoder 230, an X decoder 240, a voltage providing unit 250, and a controller. 260.

The memory cell array 210 includes a plurality of cell strings in which memory cells for data storage are connected in series, and each cell string is connected to a bit line BL. In addition, the gates of the memory cells are connected to the word line WL in a direction orthogonal to the bit line.

The page buffer unit 220 includes a plurality of page buffers PBs connected to bit lines of the memory cell array 210. Each page buffer PB temporarily stores data to be programmed in a selected memory cell. The data is transferred to a memory cell through a bit line, or data stored in the memory cell is read and stored.

The page buffer includes a plurality of latch circuits, and while the program is executed using one latch circuit, data to be cached may be input to the other latch circuit.

The Y decoder 230 provides an input / output path to the page buffer PB of the page buffer unit 220 according to the input address, and the X decoder 240 selects a word line of the memory cell array 210 according to the input address. do.

The voltage providing unit 250 generates an operation voltage to be provided to a word line connected by the X decoder 240 under the control of the controller 260, and the controller 260 outputs a control signal according to an operation command. The voltage providing unit 250 is controlled to provide a pass voltage set according to the data program degree of the memory cell array 210.

2B is a detailed circuit diagram of the page buffer.

Referring to FIG. 2B, the page buffer includes a bit line selection unit 221, a sensing unit 222, a precharge unit 223, a latch unit 224, and a verification unit 228.

The bit line selector 221 selects the even bit line BLe and the odd bit line BLO, and the sensing unit 222 senses the voltage of the bit line connected by the bit line selector 221. The sensing result of the sensing unit 222 is reflected as the sensing node SO.

The precharge unit 223 precharges the sensing node SO, and the latch unit 224 has a plurality of latch circuits connected to the sensing node SO to form a memory cell according to the voltage level of the sensing node SO. The stored data is stored in the latch circuit or the data to be programmed is stored in the latch circuit and then transferred to the sensing node SO.

The latch unit 224 includes first to third latch circuit units 225 to 227. The first latch circuit unit 225 receives data for a cache program or temporarily stores read data and outputs the read data. The second latch circuit unit 226 and the third latch circuit unit 227 perform data programs.

The verification unit 228 is connected between the first and second latch circuit units 225 and 226 to output a verification signal for program verification.

The bit line selector 221 may include first to fourth NMOS transistors N1 to N4, the sensing unit 222 may include a fifth NMOS transistor, and the precharge unit 223 may be a PMOS transistor (P). ).

The first latch circuit unit 225 includes sixth to eighth NMOS transistors N6 to N8, and includes first to second inverters IN1 and IN2. The second latch circuit unit 226 includes ninth to eleventh NMOS transistors N9 to N11 and third and fourth inverters IN3 and IN4.

The third latch circuit unit 227 includes twelfth to fifteenth NMOS transistors N12 to N15 and fifth and sixth inverters IN5 and IN6, and the verification unit includes seventeenth to nineteenth NMOS transistors N17 to N19. It includes.

The first and second NMOS transistors N1 and N2 are connected in series between the even bit line BLe and the odd bit line BLo, and between the first and second NMOS transistors N1 and N2. Variable voltage VIRPWR is connected. The variable voltage VIRPWR provides a power supply voltage Vcc for prohibiting a program or a 0V voltage for discharging during a program operation. The discharge control signals DISCHe and DISCHo are input to the gates of the first and second NMOS transistors N1 and N2, respectively.

The third NMOS transistor N3 is connected between the even bit line BLe and the node K1, and the even bit line select signal BSLe is input to the gate of the third NMOS transistor N3.

The fourth NMOS transistor N4 is connected between the odd bit line BLo and the node K1, and the odd bit line selection signal BSLo is input to the gate of the fourth NMOS transistor N4.

The fifth NMOS transistor N5 is connected between the node K1 and the sensing node SO, and the sensing control signal PBSENSE is input to the gate of the fifth NMOS transistor N5. The fifth NMOS transistor N5 is turned on or off according to the voltage of the bit line to which it is connected and the voltage level of the sensing control signal PBSENSE. As the fifth NMOS transistor N5 is turned on or turned off, the voltage level of the sensing node SO is changed to change data stored in the latch unit 224.

The PMOS transistor P is connected between the power supply voltage and the sensing node SO, and the precharge control signal PRECH_N is input to the gate of the PMOS transistor P.

The sixth NMOS transistor N6 is connected between the sensing node SO and the node QC_N, and the first data transfer signal TRAN is input to the gate of the sixth NMOS transistor N6.

The first and second inverters IN1 and IN2 are connected in a latch circuit form between the node QC and the node QC_N to form the first latch L1.

The seventh NMOS transistor N7 is connected between the node QC and the node K2, and the eighth NMOS transistor N8 is connected between the node QC_N and the node K2. The first reset signal CRST and the first set signal CSET are input to gates of the seventh and eighth NMOS transistors N7 and N8, respectively.

The ninth NMOS transistor N9 is connected between the sensing electrode SO and the node QM_N, and the second data transfer signal TRANM is input to the gate of the ninth NMOS transistor N9. The third and fourth inverters IN3 and IN4 are connected between the node QM and the node QM_N in the form of a latch circuit to form the second latch L2.

The tenth NMOS transistor N10 is connected between the node QM and the node K2, and the eleventh NMOS transistor N11 is connected between the node QM_N and the node K2. The second reset signal MRST and the second set signal MSET are input to the gates of the tenth and eleventh NMOS transistors N10 and N11, respectively.

The twelfth NMOS transistor N12 is connected between the sensing node SO and the node QT, and the thirteenth NMOS transistor N13 is connected between the sensing node SO and the node QT_N. The third data transfer inversion signal TRANT_N and the third data transfer signal TRANT are input to gates of the twelfth and thirteenth NMOS transistors N12 and N13, respectively.

The fifth and sixth inverters IN5 and IN6 are connected between the node QT and the node QT_N in a latch circuit form to form the third latch L3.

The fourteenth NMOS transistor N14 is connected between the node QT and the node K2, and the fifteenth NMOS transistor N15 is connected between the node QT_N and the node K2. The third reset signal TRST and the third set signal TSET are input to gates of the fourteenth and fifteenth NMOS transistors N14 and N15, respectively.

The sixteenth NMOS transistor N16 is connected between the node K2 and the ground node, and the sensing node SO is connected to the gate of the sixteenth NMOS transistor N16.

The seventeenth and eighteenth NMOS transistors N17 and N18 are connected between the node K3 and the verify signal output node nWDo, and the gate of the seventeenth NMOS transistor N17 is connected to the node QC_N. The page buffer check signal PBCHECK is connected to the gate of the NMOS transistor N18.

The nineteenth NMOS transistor N19 is connected between the ground node and the node K3, and the gate of the nineteenth NMOS transistor N19 is connected to the node QM.

3 is a flowchart illustrating a program operation of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 3 and the page buffer circuit of FIGS. 2A and 2B, a program command is first input to a nonvolatile memory device (S301).

The program command includes address information for executing a program and data to be programmed. The controller 260 selects a word line and a bit line by using the address information. The data to be programmed is stored in the second latch L2 of the page buffer.

When the data input to be programmed is completed, the controller 260 precharges the unselected bit lines and simultaneously changes the voltage of the selected bit lines according to the data state of the second latch L2 (303).

If it is assumed that the selected bit line is an even bit line, the controller 260 applies the variable voltage VIRPWR to the power supply voltage Vcc level and controls the odd bit line discharge so that the second NMOS transistor N2 is turned on. The signal DISCHo is applied at a high level.

At the same time, the even bit line selection signal BSLe, the sensing control signal PBSENSE, and the second data transmission signal TRANM are applied at a high level.

By the above operation, the odd bit line BLo becomes precharged by the variable voltage VIRPWR, and the even bit line BLe becomes precharged or becomes 0V according to the state of the node QM_N.

After the bit line voltage setting as described above, the voltage of the even bit line is finely adjusted. The fine adjustment is applied to the sensing control signal PBSENSE, the even bit line selection signal BSLe, and the third data transmission signal TRANT to a high level to adjust the bit line voltage. The reason for the fine adjustment is that, even when the data of the node QM_N is in the '0' state, whether or not the program is determined depends on the state of the node QT_N when the multilevel cell is programmed. The node QT_N may store flag information for controlling program progress of a multi-level cell.

When the bit line voltage setting is completed, the program is applied by applying a program voltage to the word line (S305 and S307).

By the above operation, the voltages of the selected bit line and the non-selected bit line are set at the same time, thereby reducing the program time compared to when operating separately. In addition to program execution, the present invention can also be applied to a soft program that is performed in an erase operation. When proceeding to a soft program, both even and odd bit lines are precharged and can operate.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.

1 is a flowchart of a program operation of a nonvolatile memory device.

2A is a block diagram of a nonvolatile memory device.

2B is a detailed circuit diagram of the page buffer.

3 is a flowchart illustrating a program operation of a nonvolatile memory device according to an embodiment of the present invention.

* Brief description of the main parts of the drawings *

200: nonvolatile memory device 210: memory cell array

220: page buffer unit 230: Y decoder

240: X decoder 250: voltage providing unit

260 control unit

Claims (8)

Receiving data to be programmed according to a program command; Changing the voltage of the first bit line selected for programming the data according to the data state to be programmed and simultaneously precharging the unselected second bit line; And Steps to proceed with data program Method of operating a nonvolatile memory device comprising a. The method of claim 1, The voltage of the first bit line is, When the data to be programmed is at a first logic level, the data is precharged to a power supply voltage. And 0 V when the data to be programmed is at the second logic level. The method of claim 2, After changing the voltage of the first bit line, changing the first bit line voltage according to prestored flag information. The method of claim 1, And the second bit line is precharged by a variable voltage of a page buffer. Receiving a program command and address information, and receiving data to be programmed into a page buffer; Changing a first bit line voltage selected according to the address information according to data stored in a page buffer, and simultaneously precharging a second bit line voltage not selected; Changing the voltage of the first bit line according to flag information stored in the page buffer; And Performing a program by applying a program voltage to a selected word line Method of operating a nonvolatile memory device comprising a. The method of claim 5, The voltage of the first bit line is If the data to be programmed stored in the page buffer is at a first logic level, it is precharged to a power supply voltage. And 0 V when the data to be programmed is at the second logic level. Performing an erase and performing a verification; According to a soft program command, changing the selected first bit line voltage according to the data stored in the page buffer, and simultaneously precharging the unselected second bit line voltage; And Steps to Run a Soft Program Method of operating a nonvolatile memory device comprising a. The method of claim 7, wherein And all of the first bit lines are precharged to a power supply voltage level.

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