KR20090117584A - Apparatus and mathod for encoding low density parity check code - Google Patents

Abstract

PURPOSE: An apparatus and a method for encoding a low density parity check code are provided to generate a low density parity code having a low error by performing encoding of the low density parity code. CONSTITUTION: A parity check matrix generating part(310) generates a parity check matrix including a parity sub matrix. The parity check matrix includes a matrix element which is a message bit and a matrix element which is a parity bit. A puncturing part(320) performs puncturing about at least one matrix element among matrix element of a parity sub matrix. The puncturing part performs puncturing about at least one matrix element among matrix element of a first block matrix according to a puncturing order. The puncturing part punctures the matrix element of the first block matrix based on a matrix size of the first block matrix in a puncturing process. An encoding part(330) encodes an information word inputted from user by using the parity check matrix.

Description

Low density parity check code encoder and its method {APPARATUS AND MATHOD FOR ENCODING LOW DENSITY PARITY CHECK CODE}

The present invention relates to an apparatus and method for encoding a low density parity check code, and more particularly, to an apparatus and method for encoding a low density parity check code having a low error floor.

The present invention is derived from the research conducted as part of the IT growth engine technology development of the Ministry of Knowledge Economy and the Ministry of Information and Telecommunications Research and Development. Transmission technology development].

With the rapid development of mobile communication systems, there is a demand for the development of a technology for transmitting a large amount of data approaching the capacity of a wired network in a wireless network. However, the mobile communication system inevitably generates an error due to noise, interference, fading, and the like depending on the channel conditions at the time of transmitting data. This causes loss of information data.

Various error-control schemes are used to reduce the loss of information data due to errors, and the most commonly used error-correcting code is the most commonly used.

The Low Density Parity Check Code (hereinafter referred to as "LDPC code") is one of the error correction codes that was proposed by Gallagher in 1962. LDPC codes were not used due to the complexity of decoder implementations, but their performance has been proven in the 1990s, and research on these codes has been actively conducted since then.

The LDPC code has a parity where most elements have a zero value and very few elements other than those with a zero value have a non-zero value (eg a value of 1). Coded using a parity check matrix.

The LDPC code can obtain a rate-compatible characteristic according to channel conditions through puncture. Punching is a method of increasing the code rate by not sending some nodes in the data to be sent. At this time, in order to decode the punctured nodes, it is assumed that the decoder knows the positions of the punctured nodes.

1 is a diagram illustrating an example of a recovery tree of a perforated LDPC code according to the prior art.

Perforated nodes may be classified according to the number of iterations of the decoder necessary to recover. For example, the punctured nodes recovered in the k-th decoding process of the decoder are called k-SR recoverable nodes. In general, the smaller the value of k in the k-SR node, the higher the reliability of the restored node. Therefore, when puncturing some nodes, the puncturing proceeds from the order of low k values.

1 shows a recovery tree when the value of k is three. In FIG. 1, a circular symbol means a variable node, and represents a column in a parity check matrix. The square symbol denotes a check node, which represents a row in the parity check matrix. The line connecting each variable node and the check node means an edge, and determines the value (0 or 1) of the matrix element in the parity check matrix. Perforated nodes classified according to the repetition order in which decoding is performed may be collected again among the same k-SR nodes. This is called grouping and can be expressed as G _k by grouping k-SR nodes.

).The parity check matrix (H) can comprise a sub-matrix, the message matrix elements of a message in bits (sub matrix) (H _s) and the parity sub-matrix of the parity bits to a matrix element (H _p) (

).

There parity sub-matrix can have a structure RC E ^2, E ² parity sub-matrix having a RC structure to can be expressed as Equation (1).

은 행렬

에서

=1일 때의 행렬을 의미한다. m은 패리티 검사 행렬(또는 패리티 서브 행렬)의 행의 크기를 의미하는 것으로서, m이 2의 승수 값을 가진다고 가정하면(즉,

),

이 l=d 일 때 행렬 크기가 최소가 되고 그때의 행렬

는

가 된다. here,

Silver matrix

in

It means a matrix when = 1. m is the size of the row of the parity check matrix (or parity sub-matrix), assuming that m has a multiplier of 2 (i.e.

),

The matrix size becomes the minimum when l = d, then

Is

Becomes

Parity sub-matrices with an E ² RC structure are punctured in order from the first column of the matrix. Therefore, the parity sub-matrix having the E ² RC structure has a structure that is convenient for puncturing because the puncturing order is relatively simple.

As mentioned above, in the case where the channel state changes with time, the error correction code system should be able to change the code rate according to channel state information (CSI). To obtain adaptability, several encoders and decoders are required. When the number of encoders and decoders increases, the complexity of the code and the decoding increases.

On the other hand, when the code rate is changed by puncturing, only one coder and one decoder can obtain code rate adaptability. In addition, when using a parity check matrix including a parity sub-matrix having an E ² RC structure, the complexity of puncturing is reduced and performance superior to other punctured LDPC codes can be obtained.

However, when using a parity check matrix including a parity sub-matrix with an E ² RC structure, a relatively large error floor occurs at the reference code rate, so that an error occurs even when the signal to noise ratio (SNR) increases. Probability is not greatly reduced and Bit Error Rate (BER) performance is degraded.

It is an object of the present invention to modify the E ² RC structure to encode a low density parity code with low error floor.

In order to achieve the object of the present invention as described above, the present invention provides a parity check matrix generating unit for generating a parity check matrix including a parity sub matrix having parity bits as matrix elements, and the parity sub-matrix of the parity sub-matrix. And a puncturing unit for puncturing at least one matrix element among matrix elements, and an encoding unit for encoding an information code input from a user using the parity check matrix on which the puncturing is performed. Provides an apparatus for encoding a low density parity check code including a plurality of first block matrices having an E ² RC (Efficiently Encodable Rate compatible) structure.

According to one aspect of the invention, generating a parity check matrix including a parity sub-matrix having a parity bit as a matrix element, performing a puncture on at least one matrix element of the matrix elements of the parity sub-matrix, And encoding an information word input from a user using the parity check matrix on which the puncturing has been performed, wherein the parity sub-matrix comprises a plurality of first block matrices having an E ² RC structure. An encoding method of is provided.

According to the present invention, a low density parity code having a low error floor can be generated by encoding a low density parity code using a parity check matrix including a parity submatrix having a modified E ² RC structure.

Hereinafter, an apparatus and method for encoding a low density parity check code according to the present invention will be described in detail with reference to the accompanying drawings.

2 illustrates a parity sub-matrix according to an embodiment of the present invention. Hereinafter, a parity submatrix according to an embodiment of the present invention will be described in detail with reference to FIG. 2.

In encoding the punctured LDPC code, the puncture is performed on the parity sub-matrix (H _p ) having a certain structure. The code rate of the LDPC code may be changed according to the number of matrix elements (or variable nodes) on which the puncturing is performed. The code rate according to the number of matrix elements (or variable nodes) for which puncturing is performed may be expressed as in Equation 2 below.

Where R is the code rate of the punctured LDPC code, n is the length of the LDPC code, k is the length of the information code, and n _p is the length of the punctured code.

As can be seen from Equation 2, the apparatus and method for encoding a low density parity check code according to an embodiment of the present invention can change the code rate by adjusting the number of matrix elements to be punctured.

In the conventional E ² RC LDPC code, encoding of the LDPC code is performed using a parity check matrix including a parity sub-matrix composed of one matrix having an E ² RC structure. As the length of the LDCP code increases, the maximum check node order in the parity sub-matrix increases. This increase in the maximum check node order causes the distribution of the order of the check nodes in the parity sub-matrix to be more distributed. Many cycles with ACE (Approximate cycle EMD) have been created. That is, the number of small stopping sets becomes large, and as a result, the LDPC code has a high error floor. For LDPC codes with high error floors, the error probability does not decrease significantly even if the signal-to-noise ratio is increased, resulting in low bit error rate (BER) and frame error rate (FER) performance.

An apparatus and method for encoding a low density parity check code according to an embodiment of the present invention changes the structure of a parity submatrix having an E ² RC structure, thereby reducing the maximum check node order in the parity submatrix and reducing the total check node. By agglomerating the order distribution, the problem of LDPC codes with high error floors can be solved without deteriorating existing performance.

As shown in FIG. 2, the parity sub-matrix H _p may include a plurality of block matrices. In this case, the parity sub-matrix H _p may include a plurality of first block matrices having an E ² RC structure.

내지

행렬은 E²RC 구조를 가지는 제1 블록 행렬을 각각 의미한다. E²RC 구조의 제1 블록 행렬은 재귀적인 형태를 가지는데, 상기

내지

행렬을 일반화하여 표현하면 하기 수학식 3과 같다.

To

The matrix means a first block matrix each having an E ² RC structure. The first block matrix of the E ² RC structure is recursive.

To

The generalization of the matrix is expressed as Equation 3 below.

는

의 크기를 갖는 단위 행렬,

는

의 크기를 갖는 영행렬을 각각 의미한다. 또한,

은 1 에서

사이의 값을 갖는 자연수이고, j는 1 에서

(

, m은 패리티 검사 행렬의 크기를 의미함)의 값을 갖는 복수개의 E²RC 구조를 가지는 블록 행렬의 순서를 각각 의미하고, b와

는

의 관계를 가진다.

이

값을 갖는 경우,

가 된다.Where b is the size of a block matrix having an E ² RC structure,

Is

An identity matrix with the size of,

Is

Each means a matrix having a size of. Also,

Is from 1

Is a natural number with a value between and j is from 1

(

, m denotes the size of the parity check matrix), and b and b denote a sequence of block matrices having a plurality of E ² RC structures.

Is

Has a relationship with

this

Has a value,

Becomes

As shown in FIG. 2, the parity sub-matrix H _p may be represented as a row and a column in block units corresponding to the matrix size of the first block matrix. The one block matrices may be located on the diagonal axis of the block unit of the parity sub-matrix H _p . This is due to the matrix characteristics of the E ² RC structure.

Also, the parity sub-matrix H _p may include a plurality of zero matrixes O _b and a plurality of second block matrices C _b .

Most elements have a zero value, and very few elements other than zero have a non-zero value (for example, a value of 1). In order to satisfy the property, most of the parity sub-matrix consists of zero matrix O _b , where the matrix element has a value of zero.

The second block matrix C _b is a block matrix added to improve the performance of LDPC code encoding, which can be expressed as Equation 4 below.

That is, the second block matrix C _b is a sub-matrix added to adjust the order of the variable nodes in the parity sub-matrix H _p to "2". When the order of the variable nodes in the parity sub-matrix H _p is 2, that is, when the second block matrix C _b is added, the encoding performance of the LDPC code is increased.

According to an embodiment of the present invention, the column of the rightmost block unit of the parity sub-matrix H _p may not include the second block matrix. If the rightmost block unit column of the parity submatrix H _p does not contain the second block matrix C _b , the order of the variable nodes of the rightmost column of the parity submatrix is 1, in which case The LDPC code will have better performance. This is due to the characteristics of the E ² RC structure.

As described above, the present invention configures the parity sub-matrix used for encoding the LDPC code to include a small first block matrix having a plurality of E ² RC structures, whereby the maximum parity sub-order of the parity sub-matrix is a parity sub-matrix. It is determined by the matrix size (b) of the first block matrix, not the matrix size (m) of. In other words, when the LDPC code is encoded using a first block matrix having a small matrix size (that is, a small b value), the order distribution of the check nodes of the parity check matrix is aggregated and the maximum check node orders are small. You lose. Accordingly, the maximum check node order of the parity submatrix can solve the problem of the high error floor mentioned above with a fixed value irrespective of the length of the LDPC code.

When encoding LDPC codes are performed by using the parity sub-matrix shown in FIG.

는 검사 노드의 차수 분포에 관한 다항식, i는 검사 노드에 연결된 에지의 개수, 는 i개의 에지와 연결된 검사 노드의 수 대 전체 에지의 수의 비율을 각각 의미하는데, 이 경우

는 하기 수학식 6에 따라서 결정될 수 있다. here,

Is the polynomial of the order distribution of the check nodes, i is the number of edges connected to the check node, Denotes the ratio of the number of inspection nodes connected to the i edges to the total number of edges, respectively.

May be determined according to Equation 6 below.

에 의해 결정된다. 따라서,

값을 작게 하는 경우, 즉 제1 블록 행렬의 크기를 작게 하는 경우, 패리티 검사 행렬의 검사노드의 차수 분포가 응집되고, 최대 검사 노드 차수의 크기가 줄어들어, 낮은 오류 마루를 갖는 LDPC 코드를 부호화 할 수 있게 된다. As can be seen from Equation 6, when the LDPC code is encoded using the parity sub-matrix H _p shown in FIG. 2, the maximum detection node order of the parity sub-matrix H _p is the matrix size. irrespective of m

Determined by therefore,

When the value is reduced, that is, when the size of the first block matrix is reduced, the order distribution of the check nodes of the parity check matrix is aggregated and the size of the maximum check node order is reduced, so that LDPC codes having a low error floor can be encoded. It becomes possible.

As an example, when the length of the information word is 1024 and the length of the LDPC code is 2048, LDPC encoding is performed using a parity sub-matrix including a first block matrix and a second block matrix having a matrix size of 16 × 16. When comparing the conventional E ² RC LDPC code and the E ² RC LDPC code according to an example of the present invention, the order distribution of the variable nodes is the same as 0.00015 + 0.30765 x + 0.27287 x ² + 0.41933 x ⁶ The order distribution of the nodes is 0.441899x ⁵ + 0.521797x ⁶ + 0.017854x ⁷ + 0.012052x ⁸ + 0.002976x ⁹ + 0.001637x ¹⁰ + 0.001785x ¹¹ (traditional E ² RC LDPC code) and 0.400833x ⁵ + 0.596786x ⁶ + 0.002381x ⁷ (E ² RC LDPC code according to an example of the present invention), each having a different form. That is, the E ² RC LDPC code according to an example of the present invention has a higher order distribution of test nodes than the conventional E ² RC LDPC code, and accordingly, the E ² RC LDPC code according to an example of the present invention is a conventional E We can see that we have better performance (lower error floor) than ² RC LDPC codes.

3 is a block diagram illustrating a structure of an encoding apparatus of a low density parity check code according to an embodiment of the present invention.

The low density parity check code encoding apparatus 300 according to an embodiment of the present invention includes a parity check matrix generator 310, a puncturing unit 320, and an encoding unit 330. Hereinafter, a low density parity check code encoding apparatus according to an embodiment of the present invention will be described in detail with reference to FIG. 3.

The parity check matrix generator 310 generates a parity check matrix including a parity sub matrix having parity bits as matrix elements.

The parity check matrix is a matrix representing a parity check of a linear code. The parity check matrix includes a matrix element that is a message bit and a matrix element that is a parity bit. The parity sub-matrix means a sub matrix of a parity check matrix composed of matrix elements that are parity bits.

According to an embodiment of the present invention, the parity sub-matrix may include a plurality of first block matrices having an E ² RC structure.

In the conventional E ² RC LDPC code, an LDPC code is encoded using a parity sub-matrix as one matrix having an E ² RC structure. However, the low density parity code encoding apparatus according to an embodiment of the present invention The LDPC code is encoded using a parity sub-matrix including a plurality of first block matrices having an E ² RC structure. In this case, each of the first block matrices may have the same matrix size.

According to an embodiment of the present invention, the number of rows of the parity sub-matrix and the number of rows of the first block matrix may have an exponential power of two.

) 패리티 서브 행렬의 설계가 간단해진다. This is due to the structure of a matrix having an E ² RC structure, where the number of rows of the first block matrix is represented by an exponential power of two (for example,

Parity submatrix is simplified.

According to an embodiment of the present invention, a plurality of first block matrices having an E ² RC structure may be located on a diagonal axis in blocks of the parity sub-matrix. This is due to the matrix characteristics of the E ² RC structure.

According to an embodiment of the present invention, the parity sub-matrix may include at least one second block matrix for adjusting the order of the variable nodes in the parity sub-matrix. As an example, for a matrix with an E ² RC structure, the order of the variable nodes may have a value of 2, in which case the second block matrix may include one matrix element having a value of 1, and the rest The matrix element may have a value of zero.

According to an embodiment of the present invention, the first block matrix and the second block matrix have the same matrix size, and the columns of each block unit except the column of the rightmost block unit in the parity sub-matrix are a plurality of first block matrices. One second block matrix of one of the first block matrix and at least one second block matrix. As an example, as in the structure of the parity sub-matrix H _p shown in FIG. 2, the plurality of first block matrices are located on a diagonal axis of a block unit of the parity sub-matrix, and the at least one second block matrices are first It may be located below the block matrix. According to an example of the present invention, the first block matrix may be expressed as Equation 3, and the second block matrix may be expressed as Equation 4. In this case, the variable node in the parity sub-matrix The order may be determined to be 2 except for the rightmost column of the parity submatrix (the variable node order of the rightmost column is 1).

According to an embodiment of the present invention, the order distribution of the check nodes in the parity sub-matrix may be determined based on the matrix size of the first block matrix. That is, in the encoding apparatus of the low density parity check code according to the embodiment of the present invention, the order distribution of the check nodes in the parity sub-matrix is determined according to the matrix size of the first block matrix rather than the matrix size of the parity sub-matrix. Accordingly, even when the size of the LDPC code is large, when encoding is performed using the first block matrix having the small matrix size, the LDPC code having the low error floor can be encoded. According to an example of the present invention, the order distribution of the check nodes in the parity sub-matrix may be determined according to Equations 5 and 6 above.

The puncturing unit 320 punctures at least one matrix element among the matrix elements of the parity submatrix.

Punching means that some bits (nodes) are not sent in the data to be transmitted in order to adjust a code rate in coding of a code. In order to decode the punctured code, it is necessary to assume that the decoder knows the location of some punctured bits (nodes).

According to one embodiment of the present invention, the puncturing unit 320 is for each of the plurality of first block matrices, among the matrix elements of the first block matrix according to the puncturing order determined based on the matrix size of the first block matrix. Perforation may be performed on at least one matrix element.

That is, when the puncturing unit 320 performs puncturing on the matrix elements of the parity sub-matrix, the puncturing unit 320 punctures the matrix elements of each first block matrix based on the matrix size of the first block matrix.

In this case, the order of puncturing in the first block matrix may be determined based on the size of the first block matrix, where the order of puncturing is k, except for matrix elements having zero values of each blocked first block matrix. In the SR node, the puncturing may proceed from the order of low k values. If the order of nodes to be punctured is defined as the index of the node to be punctured, the index of the node to be punctured may be determined according to Equation 7 below.

를, q는

를 각각 의미한다. 이 경우, j는

의 범위를 갖는다. Here, j is the order of puncturing, p _j is the order of the nodes where the puncture is performed (edge, check node, variable node in the graph, j j puncture is from the left p _j For the first node), r is

Where q is

Means each. In this case, j is

Has a range of.

As can be seen from Equation 7, the order of puncturing in each first block matrix is determined according to the value of b, which is the matrix size of the first block matrix.

The encoder 330 encodes the information word input from the user by using the parity check matrix on which the puncturing has been performed.

According to an example of the present invention, each of the first block matrices includes at least one non-puncture node, in which case, the maximum number of punctured nodes is m-m _b , and the maximum code rate of the LDPC code is It can be expressed as 8

,

,

의 관계가 각각 성립한다. Where k is the length of the information word, n is the length of the LDPC code, and m (= nk) is the number of check nodes.

,

,

Each relationship is established.

4 is a diagram illustrating a step-by-step method for encoding a low density parity check code according to an embodiment of the present invention. Hereinafter, a process performed at each step will be described in detail with reference to FIG. 4.

In step S410, a parity check matrix including a parity sub-matrix having parity bits as matrix elements is generated.

According to an embodiment of the present invention, the parity sub-matrix may include a plurality of first block matrices having an E ² RC structure.

In the conventional E ² RC LDPC code, an LDPC code is encoded using a parity sub-matrix as one matrix having an E ² RC structure. However, the low density parity code encoding apparatus according to an embodiment of the present invention The LDPC code is encoded using a parity sub-matrix including a plurality of first block matrices having an E ² RC structure. In this case, each of the first block matrices may have the same matrix size.

According to an embodiment of the present invention, the number of rows of the parity sub-matrix and the number of rows of the first block matrix may have an exponential power of two. This is to simplify the design of the parity sub-matrix.

According to an embodiment of the present invention, a plurality of first block matrices having an E ² RC structure may be located on a diagonal axis of a block unit of the parity sub-matrix.

According to an embodiment of the present invention, the parity sub-matrix may include at least one second block matrix for adjusting the order of the variable nodes in the parity sub-matrix. As an example, the second block matrix may include one matrix element having a value of 1, and the remaining matrix elements may have a value of zero.

According to an embodiment of the present invention, the first block matrix and the second block matrix have the same matrix size, and the columns of each block unit except the column of the rightmost block unit in the parity sub-matrix are a plurality of first block matrices. One second block matrix of one of the first block matrix and at least one second block matrix.

According to an embodiment of the present invention, the order distribution of the check nodes in the parity sub-matrix may be determined based on the matrix size of the first block matrix. That is, even when the size of the LDPC code is large, when encoding is performed using the first block matrix having a small matrix size, the LDPC code having a low error floor can be encoded.

 In operation S420, puncturing is performed on at least one matrix element among the matrix elements of the parity sub-matrix generated in operation S410. In order to decode the punctured code, it is necessary to assume that the decoder knows the location of some punctured bits (nodes).

According to an embodiment of the present invention, in step S420, for each of the plurality of first block matrices, at least one of matrix elements of the first block matrix according to the puncturing order determined based on the matrix size of the first block matrix. Perforation may be performed on the matrix elements of.

In operation S430, the information word input from the user is encoded by using the parity check matrix on which the puncturing is performed.

The embodiments of the method of encoding the low density parity check code according to the present invention have been described so far, and the configuration of the antenna radiation performance measuring system described above with reference to FIG. 3 is also applicable to the present embodiment. Therefore, more detailed description will be omitted.

In addition, the method of encoding the low density parity check code according to the present invention may be implemented in the form of program instructions that can be executed by various computer means and recorded on a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. Program instructions recorded on the media may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well-known and available to those having skill in the computer software arts. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tape, optical media such as CD-ROMs, DVDs, and magnetic disks, such as floppy disks. Examples of program instructions such as magneto-optical, ROM, RAM, flash memory, etc. may be executed by a computer using an interpreter as well as machine code such as produced by a compiler. Contains high-level language codes. The hardware device described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

As described above, the present invention has been described by way of limited embodiments and drawings, but the present invention is not limited to the above embodiments, and those skilled in the art to which the present invention pertains various modifications and variations from such descriptions. This is possible. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined by the claims below and equivalents thereof.

1 is a diagram illustrating an example of a recovery tree of a perforated LDPC code according to the prior art.

2 illustrates a parity sub-matrix according to an embodiment of the present invention.

3 is a block diagram illustrating a structure of an encoding apparatus of a low density parity check code according to an embodiment of the present invention.

4 is a diagram illustrating a step-by-step method for encoding a low density parity check code according to an embodiment of the present invention.

Claims (10)

A parity check matrix generator for generating a parity check matrix including a parity sub matrix having parity bits as matrix elements; A puncturing unit for puncturing at least one of the matrix elements of the parity sub-matrix; And An encoder that encodes an information code input from a user by using the parity check matrix on which the puncturing has been performed Including And the parity sub-matrix comprises a plurality of first block matrices having an E ² RC (Efficiently Encodable Rate compatible) structure. The method of claim 1, And the number of rows of the parity sub-matrix and the number of rows of the first block matrix are exponential powers of two. The method of claim 1, And the plurality of first block matrices are located on a diagonal line in block units of the parity sub-matrix. The method of claim 1, And the parity sub-matrix comprises at least one second block matrix for adjusting the order of variable nodes in the parity sub-matrix. The method of claim 4, wherein The first block matrix and the second block matrix have the same matrix size, The column of each block unit except the rightmost block unit in the parity sub-matrix is a first block matrix of one of the plurality of first block matrices and a second block matrix of one of the at least one second block matrix. And a low density parity check code encoding apparatus. The method of claim 1, And an order distribution of check nodes in the parity sub-matrix is determined based on a matrix size of the first block matrix. The method of claim 1, The puncturing unit performs puncturing on at least one matrix element among the matrix elements of the first block matrix in a puncturing order determined based on the matrix size of the first block matrix for each of the plurality of first block matrices. And a low density parity check code encoding apparatus. Generating a parity check matrix comprising a parity sub-matrix having parity bits as matrix elements; Puncturing at least one of the matrix elements of the parity sub-matrix; And Encoding an information word input from a user using the parity check matrix on which the puncturing has been performed Including And the parity sub-matrix comprises a plurality of first block matrices having an E ² RC structure. The method of claim 8, And the plurality of first block matrices are located on a diagonal axis of a block unit of the parity sub-matrix. The method of claim 8, And an order distribution of check nodes in the parity sub-matrix is determined based on a matrix size of the first block matrix.

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