KR20090115615A - Memory test system having fail judgment apparatus and method for judging fail of devices in memory test system - Google Patents

Abstract

PURPOSE: A memory test system including a defect determination apparatus and a defect determination method of the device in the memory test system are provided to progress a test at high speed by confirming the defect of each memory device without using the defect memory. CONSTITUTION: A test board(210) generates test signal. An input-output sharing device(220) outputs test data and inputs memory devices for testing the test signal. A defect determination device(400) determines whether to be defect of the memory device. The defect determination device includes a plurality of registers. A plurality of registers stores and classifies a defect determination result by each memory device.

Description

Memory test system including failure determination device and method for determining device failure in memory test system {Memory test system having fail judgment apparatus and method for judging fail of devices in memory test system}

The present invention relates to a memory test system including a failure determining device and a method for determining a device failure in a memory test system, and more particularly, in a memory test system in which test signals are applied to a plurality of memory devices using a shared pin. The present invention relates to a memory test system including a failure determination device capable of quickly checking whether a plurality of memory devices are broken, and a memory device failure determination method in a memory test system.

In general, memory products have a large amount of defects at the beginning of production and stabilize after a certain period of time, but suddenly increase as the product reaches the end of its life. Therefore, the high reliability that occurs early in the memory component must be effectively eliminated when the system is configured with memory to increase the initial reliability of the system.

In recent years, the capacity and performance of memory have increased greatly, but the process for testing memory has become more complicated and difficult. Therefore, the cost of testing memory accounts for a large percentage of the total memory production cost. Therefore, the importance of test methods and equipment for accurately determining whether a memory is defective at an early time is increasing.

The test of the memory can be classified into a wafer test performed in a wafer state and a package test performed in a package state after the assembly process. The wafer test is further divided into a pre-laser test before the laser repair process and an electronic die sorting (EDS) test after the laser repair.

The die, which has been determined to pass the EDS test, is assembled into a packaged memory through an assembly process. The packaged memory is again subjected to a series of package tests. That is, first, a DC test is performed to determine whether there is an abnormality in the assembly process, a burn-in test is performed, and a high temperature package test and a low temperature package test are performed. Recently, burn-in tests and DC tests have been performed on wafers for efficiency.

In order to detect and eliminate the initial defect of the memory, a current and voltage are applied to a memory device (DUT, Device Under Test) such as a die or a semiconductor on a wafer to test the normality of the device (DC TEST), or the inherent function of the memory device A system that tests this (Write / Read's AC TEST) is also known as a memory tester. In such a memory test system, a failure determination device may be used to determine whether a device under test has failed.

1 and 2, a failure determination apparatus and a failure determination method of a memory test system will be described. FIG. 1 is a schematic block diagram of an apparatus for determining a failure of a memory test system according to the prior art, and FIG. 2 is a flowchart illustrating a method for determining a failure of a memory device according to the prior art.

The memory tester system 50 shown in FIG. 1 includes a test board 10, a shared pin 20, a failure determining device 30, and a memory device 40 to be tested.

The test board 10 generates various test signals for testing the memory device 40. The shared pin 20 applies a test signal to the memory device 40 and performs a function of outputting test data. A plurality of memory devices to be tested, that is, the first to fourth devices DUT1 to DUT4, are commonly connected to the shared pin 20.

The failure determining apparatus 30 includes a counter 31, a memory address generator 33, and a failure memory 35. The counter 31 determines whether a failure occurs from the test data output through the sharing pin 20 and counts a failure determination result. The memory address generator 33 divides an area of the fault memory 35 to correspond to the plurality of devices DUT1 to DUT4, and test data for each device is stored in a corresponding area of the fail memory 35. By reading whether a failure determination result exists in the test data stored in the failure memory 35, it is possible to know which device among the plurality of devices DUT1 to DUT4 has a failure.

Referring to FIG. 2, a method of determining a failure of a memory device according to the related art will be described. First, a plurality of memory devices are connected to a shared pin (S201). Next, the timing is set in preparation for applying the test signal (S202), and the process of setting the fault memory (S203) is performed. Then, a test signal is applied to the plurality of devices through the sharing pin (S204), and a process of outputting test data performed on the plurality of devices is performed (S205). Next, the address of the faulty memory is selected (S206), and the output test data is stored in a predetermined area of the faulty memory (S207). Then, the entire fault memory is read (S208), and as a result of the fault determination, it is determined whether the fault bit exists in the predetermined area (S209). As a result of the determination, if the fault bit exists in the predetermined region, it is confirmed that a fault has occurred in a device corresponding to the region (S210). It can be confirmed that there is no (S211).

As discussed above, the counter 31 only counts the number of failures that occurred in multiple memory devices, so that the counter 31 does not know which memory device has failed. Therefore, in order to confirm in which memory device a failure has occurred, it is only possible to confirm which memory device has a failure by reading and confirming the entire failure memory 35 so that it is simply necessary to confirm whether or not the memory device has failed. There was also a problem that takes considerable time.

In addition, due to the process of setting the fault memory and the process of selecting the address of the fault memory in order to use the fault memory 35, a lot of time is required, resulting in a long test time.

The present invention is to overcome the above-mentioned conventional problems, the problem to be solved by the present invention is to determine whether the failure of each memory device without using the faulty memory to determine whether the fault can determine the device to proceed at high speed The present invention provides a memory test system and a method for determining a failure of a memory device in a memory test system.

According to an exemplary embodiment of the present invention, a memory test system including a failure determining apparatus, the test board generating a test signal; An input / output shareer for inputting the test signal to a plurality of memory devices and outputting test data; And a failure determining device that determines whether the plurality of memory devices have failed, and the failure determining device includes a plurality of registers that divide and store a failure determination result for each memory device. This is provided.

The plurality of memory devices are commonly connected to the input / output sharer.

The fault determination device may include a fault counter that determines a fault from the test data output from the input / output router and counts a fault determination result; And a selector configured to select any one of the plurality of registers and to connect the failure counter and a register.

The apparatus for determining whether the failure further includes an address generator for controlling the selector to select a register corresponding to each of the memory devices.

The test board includes an algorithm pattern generator, and the memory test system is a semiconductor test system.

According to another embodiment of the present invention, there is provided a method of inputting a test signal to a plurality of memory devices; Outputting test data performed on the plurality of memory devices; Counting a failure determination result by determining whether the failure is performed from the test data; Storing the failure determination result in a plurality of registers; And reading the plurality of registers to determine whether each memory device has failed.

The storing of the failure determination result in a plurality of registers may include selecting a register corresponding to each of the memory devices; And storing a failure determination result for each memory device in a corresponding register.

The applying of test signals to the plurality of memory devices may include connecting the plurality of memory devices to an input / output router for inputting the test signals and outputting test data; And applying a test signal to the plurality of memory devices through the input / output router.

As in the present invention, if the fault data is counted among the test data output from each memory device using the selector and the register, the fault data is counted and stored in a register corresponding to each memory device. Can be determined.

As a result, it is possible to confirm whether or not each memory device has failed without using a faulty memory, so that the test can be performed at high speed, thereby improving test efficiency.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

3 is a schematic configuration diagram of a memory test system including a failure determination apparatus according to the present invention, and FIG. 4 is a schematic configuration diagram of a failure determination apparatus according to an embodiment of the present invention.

Referring to FIG. 3, the memory test system includes a control computer 100, a main test device 200, a performance measurement device 300, a failure determination device 400, and a memory loading device 500, and a memory test. The device under test (DUT) 600 loaded by the memory loading apparatus 500 is disposed in the system.

The control computer 100 may be configured as a workstation or a personal computer capable of controlling and monitoring the overall operation of the memory test system.

The main test apparatus 200 includes a plurality of test boards, and the plurality of test boards generate various test signals for performing a memory test.

The memory loading apparatus 500 transfers and loads the memory device under test to the performance measurement apparatus 300, and unloads the memory device on which the test is completed. The memory loading apparatus 500 loads the wafer into the performance measurement apparatus 300 when the test is performed in the wafer state, and loads the semiconductor package into the performance measurement apparatus 300 when the test is performed in the semiconductor package state.

The performance measuring apparatus 300 performs a function of testing a memory device loaded by the memory loading apparatus 500, and includes a test head, a probe card, a probe, and the like.

The apparatus 400 for determining whether or not a failure performs a function of determining and confirming a failure of the device under test.

Referring to FIG. 4, the memory test system includes a test board 210, an input / output sharer 220, a plurality of memory devices, that is, first to fourth devices DUT 1 to DUT 4 610, 620, 630, and 640. It consists of the device under test 600 and the failure determination device 400 configured as.

The failure determining device 400 includes a failure counter 410, a selector 420, a register 430, and an address generator 440, and the register 430 includes a plurality of registers, namely, first through fourth. It consists of registers 431, 432, 433, 434.

The failure counter 410 determines whether a failure occurs from the test data output from the input / output sharer 220 and counts a failure determination result. The selector 420 selects one of a plurality of registers to connect the failure counter 410 and the register 430. The register 430 is composed of a plurality of registers, and a failure determination result for each memory device is stored in a corresponding register. The address generator 440 controls the selector 420 to select a register corresponding to each memory device.

Referring to the configuration of the memory test system shown in FIG. 4, the test board 210 of the main test apparatus 200 is connected to the input / output sharer 220, and the input / output sharer 220 is connected to the device under test 600. . The device under test includes a plurality of devices, that is, first to fourth devices (DUT 1 to DUT 4) 610, 620, 630, and 640, and each device is commonly connected to the input / output sharer 220.

The input / output sharer 220 is connected to the failure counter 410 of the failure determination device 400. An output terminal of the fault counter 410 and an address generator 440 are connected to an input terminal of the selector 420, and a register 430 is connected to an output terminal of the selector 420.

Looking at the failure determination operation in the memory test system having the above configuration, the test signal generated by the test board 210 is the first to the first to the second of the test target device 600 through the input / output sharer 220, that is, the shared pin 4 devices (DUT 1 to DUT 4) 610, 620, 630, and 640.

Test data performed on the first to fourth devices (DUT 1 to DUT 4) 610, 620, 630, and 640 are sequentially output through the input / output sharer 220. The test data output through the input / output sharer 220 is applied to the failure counter 410, and the failure counter 410 determines whether a failure is made from the test data, and counts the failure determination result. The failure determination result counted by the failure counter 410 is stored in the register 430 corresponding to each device via the selection unit 420. In this case, the address generator 440 controls the selector 420 to select a register corresponding to each device by the address bit. As a result, each register is stored in a failure determination result generated in each device, and it is possible to know in which device a failure has occurred by reading only the register.

If a failure occurs in the first device 610 and the third device 630, the failure counter 410 counts the failure determination results for the first device 610 and the third device 630. The failure determination result for the first device 610 is stored in the first register 431, which is a register corresponding to the first device 610, and the failure determination result for the third device 630 is determined by the third device ( And a third register 433 which is a register corresponding to 630. Therefore, when the entire register 430 is read, a failure determination result stored in each of the first register 431 and the third register 433 is detected, so that a failure occurs in the first device 610 and the third device 630. You can see that it has occurred.

5 is a flowchart illustrating a method of determining a failure of a memory device using a memory test system including a failure determining apparatus according to the present invention.

Referring to FIG. 5, first, a plurality of memory devices are commonly connected to an input / output router such as a shared pin (S501).

Next, the timing is set in preparation for applying the test signal (S502), and the test signal is applied to the plurality of memory devices through the shared pin (S503).

Then, a process of outputting test data performed on the plurality of memory devices is performed (S504).

A process of counting a failure determination result is performed by determining whether a failure is generated from the output test data (S505). Next, a register corresponding to each memory device is selected (S506), and a process of storing a failure determination result for each memory device in the corresponding register is performed (S507).

Thereafter, each register is read (S508), and a process of determining whether or not a fault bit exists in each register as a result of the reading is performed (S509).

As a result of the determination, if the fault bit is present in any register, it is confirmed that a fault has occurred in the memory device corresponding to the register (S510). If the fault bit is not present in any register, the memory corresponding to the register is found. In the device, it can be confirmed that there is no failure (S511).

As described above, by using the method of determining whether a memory device is faulty according to the present invention, it is possible to omit a process of setting a fault memory and a process of selecting an address of a fault memory, which are necessary in the related art. In this case, it is possible to quickly check whether or not the memory device is broken.

6 is a schematic structural diagram of an apparatus for determining a failure according to another embodiment of the present invention.

Referring to FIG. 6, the memory test system includes an algorithmic pattern generator (ALPG) 215, an input / output sharer 220, a plurality of memory devices, that is, first to fourth devices DUT 1 to DUT 4. The test target device 600 and the failure determination device 450 are configured of a (610, 620, 630, 640).

The failure determination device 450 includes a failure counter 460, a selector 470, a register 480, an address generator 490, and a failure memory 495, and the register 480 includes a plurality of registers. And first to fourth registers 481, 482, 483, and 484.

The present embodiment uses the signal generated from the algorithm pattern generator 215 as a test signal, and additionally includes a fault memory 495 in order to determine exactly which cells fail in the memory device.

What has been described above is only an exemplary embodiment of a memory test system including a failure determining apparatus and a memory device in the memory test system according to the present invention, the present invention is not limited to the above-described embodiment, As claimed in the following claims, any person of ordinary skill in the art without departing from the gist of the present invention will have the technical spirit of the present invention to the extent that various modifications can be made. .

1 is a schematic configuration diagram of an apparatus for determining a failure of a memory test system according to the related art.

2 is a flowchart illustrating a method for determining whether a device has failed in accordance with the prior art.

3 is a schematic configuration diagram of a memory test system including a failure determination apparatus according to the present invention.

4 is a schematic structural diagram of a failure determination apparatus according to an embodiment of the present invention.

5 is a flowchart illustrating a method for determining whether a device has failed using a memory test system including a device for determining whether a failure occurs according to the present invention.

6 is a schematic structural diagram of an apparatus for determining a failure according to another embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

100: control computer

200: main test device

300: performance measurement device

400: failure determination device

410: fault counter

420: selection unit

430: register

440: address generator

500: memory loading device

600: memory device

Claims (8)

In a memory test system including a failure determination device, A test board generating a test signal; An input / output shareer for inputting the test signal to a plurality of memory devices to be tested and outputting test data; And A failure determining device determining whether the plurality of memory devices have failed, The apparatus for determining whether a failure includes a plurality of registers for dividing and storing a failure determination result for each memory device. The method of claim 1, And the plurality of memory devices are commonly connected to the input / output router. The method according to claim 1 or 2, The failure determination device, A failure counter that determines whether a failure occurs from the test data output from the input / output router and counts a failure determination result; And And a selector configured to select any one of the plurality of registers and to connect the failure counter and a register. The method of claim 3, The failure determination device, And an address generator for controlling the selector to select a register corresponding to each of the memory devices. The method according to claim 1 or 2, And the test board comprises an algorithmic pattern generator. In the memory test system, a method of determining whether a memory device has failed, Inputting a test signal into a plurality of memory devices; Outputting test data performed on the plurality of memory devices; Counting a failure determination result by determining whether the failure is performed from the test data; Storing the failure determination result in a plurality of registers; And And determining whether each memory device has failed by reading the plurality of registers. The method of claim 6, Storing the failure determination result in a plurality of registers, Selecting a register corresponding to each of the memory devices; And And storing a failure determination result for each of the memory devices in a corresponding register. The method of claim 6, Applying a test signal to the plurality of memory devices, Connecting a plurality of memory devices to a common input / output router for inputting the test signal and outputting test data; And And applying a test signal to the plurality of memory devices through the input / output router.

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