KR20090115472A - Dynamic current-mode logic circuit - Google Patents

Abstract

PURPOSE: A dynamic current-mode logic circuit is provided to reduce current of a short circuit in static mode at high speed by using a logic gate with a new structure. CONSTITUTION: In a dynamic current-mode logic circuit, an MOS current-mode logic block(DLT) includes differential input terminals and differential output terminals. The MOS current-mode logic block performs an evaluation operation of the differential input signals in an evaluation step. Precharge circuit(Q2,Q3,Q4) precharge voltage levels of differential output terminals to the voltage level of the electric power supply in a precharge step. The precharge circuit connects a virtual ground node and a ground node within an activation range during of an pulse signal. A first switch circuit separates a current output terminal and a virtual ground node of the MOS current-mode logic block in the precharge step.

Description

Dynamic current-mode logic circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a dynamic current-mode logic circuit, that is, self-timed current mode logic (STCML), which can reduce dynamic power consumption and static power consumption in high-speed operation.

As the demand for portable devices has exploded, current-mode logic (CML) has emerged as a new family of logic that can replace commonly used CMOS logic gates. .

Bipolar transistors were initially applied to the CML, but their use has recently been extended to MOS gates (or CMOS circuits) requiring high-speed operation.

The first form of CML using MOS transistors is MOS CML (MCML).

1 illustrates a structure of a logic gate implemented with MOS current-mode logic (MCML) according to the prior art.

Referring to FIG. 1, a logic gate implemented with an MCML, such as an inverter / buffer, represents each logic level (eg, 1 or 0) with each voltage generated at each load resistor R1 and R2, and each transistor. Since (Q1, Q2, and Q3) are operated in the linear region, the operation speed is high.

In the high frequency region, MCML consumes less power and operates at a higher speed. However, MCML requires a constant current source Q1 that operates in response to a bias voltage Vref, resulting in high static power consumption and complicated design.

That is, the MCML consumes a lot of static power by using the constant current source Q1, and the layout area is increased due to the respective pull-up resistors R1 and R2 used at the output stage. Therefore, MCML is difficult to apply to digital logic gate design.

Dynamic CML (DyCML) is a logic style that solves the problems of MCML to apply CML technology to digital logic gate design.

FIG. 2 shows a basic structure of self-timed dynamic current-mode logic (DyCML) according to the prior art, and FIG. 3 shows a circuit diagram of the self-timing buffer shown in FIG.

2 and 3, the self-timed DyCML is stored in the differential logic tree 10, the precharge circuits Q2, Q3, and Q4, the virtual ground circuits Q1 and C1, and the differential logic tree 10. Latch circuits Q5 and Q6 for latching each of the logic values evaluated by this, and a self-timing buffer 12.

The precharge circuits Q2, Q3, and Q4 of the self-timed DyCML adjust the voltage levels (OUT and / OUT) of the output terminals during the precharge period and the period in which the first clock signal GCLK is at the low level. Charge (or precharge) to the level (Vdd) and discharge the voltage of the capacitor (C1). During the precharge period, the differential logic tree 10 and the virtual ground node, for example, the EOE node, are separated by the transistor Q1.

During the valuation period, that is, during the period when the first clock signal GCLK is at the high level, the transistors Q3 and Q4 are turned off and the transistor Q1 is turned on so that the differential logic tree 10 is turned on. An evaluation operation is performed according to the input signals.

The transistors Q5 and Q6 are latches that hold the voltage level (OUT, high level) of the first output terminal and the voltage level (/ OUT, eg, low level) of the second output terminal after the evaluating operation is performed. It works.

The self-timing buffer 12 is a clock signal inputted to the gate of the next stage DyCML (that is, the transistor Q1 and a clock signal outputted from the self-timing buffer 12 so that the DyCML can perform the self-timing operation smoothly. Except for having the same structure as the DyCML shown in Figure 2) to generate the necessary second clock signal (CLK1). The second clock signal CLK1 is supplied to the gate of the transistor Q1 of the next stage DyCML.

The DyCML shown in FIG. 2 removes the constant current source Q1 and the traditional resistors R1 and R2 used in the MCML shown in FIG. 1 and replaces the virtual ground C1 and active device resistors Q3-Q6. It can reduce power consumption and DyCML layout area, so it can be easily applied to digital systems.

However, as the size of the transistor Q1 acting as a switch of the virtual ground C1 is considerably larger than the size of the transistor Q2, the transistors Q1 and Q2 are alternately turned off in the precharge period and the evaluation period. In the precharge period, that is, the period in which the first clock signal GCLK is at a low level, a large leakage current occurs.

Also present between each of the PMOS transistors Q11 and Q13 in the self-timing buffer 12 and the respective control signals GCLK, / GCLK, and EOE that control the gates of the respective NOS transistors Q12 and Q14. Due to the signal race, there is a section in which two transistors (Q11 and Q12, or Q13 and Q14) are turned on at the same time, so that a large amount of short-circuit current occurs. have.

Accordingly, the technical problem to be achieved by the present invention is to provide a logic gate having a new structure that can reduce the dynamic power consumption and static power consumption in high-speed operation, in order to overcome the disadvantages of the dynamic current-mode logic.

A dynamic current-mode logic circuit for achieving the above technical problem includes a MOS current-mode logic block, a precharge circuit, and a first switch circuit.

The MOS current-mode logic block includes differential input terminals and differential output terminals, and performs an evaluating operation on differential input signals inputted through the differential input terminals in an evaluating step.

The precharge circuit precharges the voltage levels of the differential output terminals to the voltage level of the power supply in the precharge step, and connects the virtual ground node and the ground node only during the activation period of the pulse signal generated when the precharge step is started. .

The first switch circuit separates the current output terminal of the MOS current-mode logic block and the virtual ground node in the precharge step, and the current output terminal and the current of the MOS current-mode logic block in the evaluating step. Connect the virtual ground node.

The dynamic current-mode logic circuit further includes a pulse generator for generating the pulse signal in response to a first clock signal and a delayed first clock signal in the precharge step. The pulse generator is a NOR gate.

The dynamic current-mode logic circuit may include a second switch circuit that separates the virtual ground node and the first node in the precharge step and connects the virtual ground node and the first node in the evaluating step, and the precharge. And a third switch circuit connecting the first node and the ground node in the step and separating the first node and the ground node in the evaluating step.

The dynamic current-mode logic circuit is connected between the power supply and the ground terminal through a fourth switch gated in response to the signal of the first node and is configured to invert the first clock signal and a first inverter. A second inverter connected between the power supply and the ground terminal through a fifth switch gated in response to a clock signal and inverting an output signal of the first inverter to generate a second clock signal; and the first clock signal And a pulse generator configured to generate the pulse signal in response to an output signal of the first inverter.

The pulse generator generates the pulse signal that is activated only during a period corresponding to the inverting delay time of the first inverter in response to the first clock signal and the output signal of the first inverter being deactivated.

The dynamic current-mode logic circuit according to the embodiment of the present invention has an effect of significantly reducing the leakage current generated during the static mode operation and the short circuit current generated during the dynamic mode operation in a high speed operation.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

4 illustrates a structure of self-timed current-mode logic (STCML) according to an embodiment of the present invention, FIG. 5 illustrates a circuit diagram of a self-timing buffer of STCML illustrated in FIG. 4, and FIG. 6 is illustrated in FIG. 4. An operation timing diagram of the illustrated STCML is illustrated, and FIG. 7 illustrates voltage waveforms of internal nodes of the STCML illustrated in FIG. 4.

STCML according to an embodiment of the present invention invented to overcome the shortcomings of DyCML may be referred to as STCML family, STCML gate, or STCML circuit. STCML according to an embodiment of the present invention may be used as an optical communication transceiver or an adder of a CPU. STCML is an example of a dynamic current-mode logic circuit.

Referring to FIG. 4, the STCML includes a differential logic tree (DLT) for logic evaluation, precharge circuits (Q2, Q3, and Q4), virtual ground circuits (Q1 and C1), and self- improvement for performance. A timing buffer STB, switch circuits Q10 and Q11, pulse generator G1, and latches Q5 and Q6.

The differential logic tree (DLT), which may also be referred to as a MOS current-mode logic block or MOS current-mode logic circuit, corresponds to the differential output signals OUT corresponding to the difference between the differential input signals Input + and Input- in the evaluation phase. And / OUT).

For example, in the evaluation step, the differential logic tree DLT outputs a first output signal OUT having a first level to the first output terminal according to the difference between the differential input signals Input + and Input− and outputs the first output signal. The second output signal / OUT having a level lower than the level (or higher than the first level) may be output to the second output terminal. For example, the differential logic tree DLT may be implemented as a differential amplifier, an inverter, a buffer, or the like.

The self-timing buffer (STB) performs the function of generating the required clock signal at the next STCML stage. That is, since the main function of the self-timing buffer (STB) is to quickly transfer the completion signal CLK1 as the clock signal of the next stage STCML, it is important to speed up the rise time of the completion signal CLK1. Do.

For example, the self-timing buffer STB is connected between the power supply and the ground terminal via a switch Q14 that is turned on / off in response to the input signal EOE of the self-timing buffer STB as shown in FIG. 5. The power supply and the ground terminal through first inverters Q15 and Q16 for inverting the first clock signal GCLK and a switch Q19 that is turned on / off in response to the inverted first clock signal / GCLK. And second inverters Q17 and Q18 connected to each other to invert the output signal / EOE of the first inverters Q15 and Q16 to generate the second clock signal CLK1.

Referring to FIG. 5, the self-timing buffer STB includes transistors Q16 and Q18 for blocking leakage current and short circuit current. That is, transistor Q16 is connected between transistor Q14 and transistor Q15 and transistor Q18 is connected between transistor Q17 and transistor Q19.

The transistor Q10 used as the switch circuit separates the virtual ground node and the input node of the self-timing buffer STB in the precharge stage and the input node of the virtual ground node and the self-timing buffer STB in the evaluating stage. Performs the function of connecting.

In addition, the transistor Q11 used as the switch circuit performs a function of preventing floating of an input node of the self-timing buffer STB by the transistor Q10. That is, the transistor Q11 connects the input node of the self-timing buffer STB and the ground node in the precharge stage and separates the input node and the ground node of the self-timing buffer STB in the evaluating stage. do.

4 to 7, immediately after the precharge stage starts, that is, immediately after the first clock signal GCLK transitions from the high level to the low level, the transistors Q3 and Q4 are connected to the voltage level of the first output terminal. The voltage level (/ OUT) of (OUT) and the second output terminal starts precharging to the voltage level (Vdd) of the power supply, that is, the high level.

The voltage EOE of the input node of the self timing buffer STB transitions to the low level, that is, the ground voltage level by the transistor Q11. The voltage / EOE of the first inverter is precharged or charged to the voltage level Vdd of the power supply by the transistor Q15 of the self timing buffer STB.

Accordingly, the pulse generator G1 generates a pulse signal DP having a very short pulse width immediately after the precharge step is started. The pulse width of the pulse signal DP may be determined according to the turn-on time of the transistor Q11 and the turn-on time of the transistor Q15. The pulse generator G1 may be implemented with a NOR gate.

Transistor Q2, which performs the function of the switch circuit in response to the pulse signal DP, discharges the voltage of the capacitor C1 connected to the virtual ground node (or used as the virtual ground node) to ground. Thus, the pulse signal DP functions as a virtual ground discharge pulse. The discharge of the voltage of the capacitor C1 is only performed for a very short time in the initial stage of the precharge stage by the activated (eg, having a high level) pulse signal DP.

In the precharge step, the transistors Q1 and Q2 remain off at the same time while the pulse signal DP is inactive, for example, at a low level.

When the transistors Q1 and Q2 remain off at the same time in the precharge step, the transistor Q1 having a width larger than the width of the transistor Q2 (eg, the ratio of the width of the channel to the length of the channel) is removed. Many leakage currents introduced through the transistor Q2, which maintains the off state, flow into the capacitor C1 which is not discharged to ground but is used as a virtual ground node.

Therefore, since the source voltage of the transistor Q1 increases due to leakage current flowing in time, the voltage difference Vgs between the gate and the source of the transistor Q1 becomes negative. Thus, the leakage current of transistor Q1 is significantly reduced.

During the precharge step, i.e., while the first clock signal GCLK maintains the low level, the voltage level OUT of the first output terminal and the voltage of the second output terminal are caused by the transistors Q3 and Q4. The level / OUT is precharged or charged to the voltage level Vdd of the power supply.

During the evaluation phase, that is, while the first clock signal GCLK maintains the high level, the evaluation of the differential input signals Input + and Input− is performed by the differential logic tree DLT. For example, when the first clock signal GCLK transitions from a low level to a high level, the voltage level OUT of the first output terminal transitions from a high level to a low level after an evaluation period by the differential logic tree DLT. After the self-timing period passes, the first clock signal CLK1 transitions from the low level to the high level.

For example, when the first input signal Input + is at the high level, the voltage level OUT of the first output terminal transitions to the low level by the differential logic tree DLT, and at the same time, the input signal of the self-timing buffer STB As the EOE rises to the high level, the level / EOE of the output voltage of the first inverter transitions to the low level.

Accordingly, the evolution completion signal, that is, the second clock signal CLK1, transitions to the high level by the transistor Q17 of the self-timing buffer STB.

The second clock signal CLK1 is input to the gate of the transistor Q1 of the next stage STCML. For example, when the semiconductor device includes K-STCML stages connected in series, the structure and operation of each of the K-STCML stages are substantially the same as the structure and operation of the STCML shown in FIGS. 4 and 5. .

However, only the clock signal input to the gate of the transistor Q1 of each of the K-STCML stages and the clock signal output from the self-timing buffer STB are different.

For example, the first clock signal GCLK is input to the gate of the transistor Q1 of the first STCML stage, and the clock signal CLK1 output from the self-timing buffer STB of the first STCML stage is the second STCML stage. The clock signal inputted to the gate of the transistor (Q1) of the transistor, the clock signal output from the self-timing buffer (STB) of the second STCML stage is input to the gate of the transistor (Q1) of the third STCML stage, (K-1) The clock signal output from the self-timing buffer STB of the STCML stage is input to the gate of the transistor Q1 of the K-th STCML stage.

Referring to FIG. 7, PEV represents the voltage level of the current output terminal of the differential logic tree DLT when the first clock signal GCLK is at the low level, and EOE represents the voltage of the input terminal of the self-timing buffer STB. OUT represents the voltage at the first output terminal of the differential logic tree DLT.

8 shows simulation results for power, time delay, and energy-delay product (EDP) of a NAND gate. The simulation shown in FIG. 8 was carried out at temperature conditions of supply voltage (Vdd) 1.8V, loading capacitance 50fF, and 25 ° C.

As a result of comparing the dynamic power consumption, the STCML according to the embodiment of the present invention has a 27% improvement over DyCML and 5% compared to the most widely used differential cascode voltage switched logic (DCVS) for implementing a logic gate. It can be seen that the effect of the improvement.

As a result of the comparison in terms of EDP, it can be seen that the STCML according to the embodiment of the present invention has an improvement effect of 14% compared to DyCML and an improvement effect of 19 compared to DCVS.

9 shows simulation results for leakage power consumption of a NAND gate. 9, it can be seen that the leakage current of the STCML according to the embodiment of the present invention is considerably smaller than the leakage current of the DyCML and the leakage current of the DCVS. In the power saving mode, that is, the idle mode, the leakage current of the STCML according to the embodiment of the present invention can be seen that significantly lower than the leakage current of the DyCML.

In the case of DyCML, only one relatively large transistor Q1 of the transistors Q1 and Q2 shown in FIG. 2 is turned off in the power saving mode, whereas in the case of STCML according to an embodiment of the present invention, This is because the transistors Q1 and Q2 shown in FIG. 4 are turned off, so that the leakage current is significantly reduced due to the stacking effect and the body effect.

STCML according to an embodiment of the present invention consumes less leakage current as much as 1/26 as compared to DyCML, and consumes twice as much leakage current as DCVS.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

The detailed description of each drawing is provided in order to provide a thorough understanding of the drawings cited in the detailed description of the invention.

1 illustrates a structure of a logic gate implemented with MOS current-mode logic (MCML) according to the prior art.

2 illustrates a basic structure of self-timed dynamic current-mode logic (DyCML) according to the prior art.

3 shows a circuit diagram of the self-timing buffer shown in FIG. 2.

4 illustrates a structure of self-timed current-mode logic (STCML) according to an embodiment of the present invention.

FIG. 5 shows a circuit diagram of the self-timing buffer of STCML shown in FIG. 4.

FIG. 6 illustrates an operation timing diagram of the STCML shown in FIG. 4.

FIG. 7 shows voltage waveforms of internal nodes of the STCML shown in FIG. 4.

8 shows simulation results for power, time delay, and EDP of a NAND gate.

9 shows simulation results for leakage power consumption of a NAND gate.

Claims (6)

A MOS current-mode logic block comprising differential input terminals and differential output terminals, the MOS current-mode logic block performing an evaluation operation on differential input signals inputted through the differential input terminals in an evaluating step; A precharge circuit for precharging the voltage levels of the differential output terminals to a voltage level of a power supply in a precharge step, and connecting a virtual ground node and a ground node only during an activation period of a pulse signal generated when the precharge step is started; And Separating the current output terminal of the MOS current-mode logic block and the virtual ground node in the precharge step, and connecting the current output terminal of the MOS current-mode logic block and the virtual ground node in the evaluation step. A dynamic current-mode logic circuit comprising a first switch circuit for. The logic circuit of claim 1, wherein the dynamic current-mode logic circuit comprises: And in the precharge step, a pulse generator for generating the pulse signal in response to a first clock signal and a delayed first clock signal. 3. The dynamic current-mode logic circuit of claim 2 wherein the pulse generator is a NOR gate. The logic circuit of claim 1, wherein the dynamic current-mode logic circuit comprises: A second switch circuit separating the virtual ground node and the first node in the precharge step and connecting the virtual ground node and the first node in the evaluating step; And And a third switch circuit connecting the first node and the ground node in the precharge step and separating the first node and the ground node in the evaluating step. The logic circuit of claim 4 wherein the dynamic current-mode logic circuit comprises: A first inverter connected between the power supply and the ground terminal through a fourth switch gated in response to a signal of the first node and inverting a first clock signal; A second inverter connected between the power supply and the ground terminal through a fifth switch gated in response to an inverted first clock signal and inverting an output signal of the first inverter to generate a second clock signal; And And a pulse generator configured to generate the pulse signal in response to the first clock signal and an output signal of the first inverter. The pulse generator of claim 5, wherein the pulse generator generates the pulse signal that is activated only during a period corresponding to an inverting delay time of the first inverter in response to the first clock signal and the output signal of the first inverter being deactivated. Dynamic current-mode logic circuit.

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