KR20090114989A - Duty circle correct circuit and delay locked loop circuit thereof - Google Patents

Abstract

PURPOSE: A duty cycle correction circuit and a delay locked loop circuit are provided to correct a duty ratio by performing the feedback operation for changing the driving power of a circuit for driving a clock outputted from a duty cycle correction circuit. CONSTITUTION: A phase mixing unit(322) detects the phase difference between a positive clock and a negative clock and mixes the phase of the positive and negative clocks by reflecting the weight corresponding to the detection result. A duty ratio detector(326) detects the duty ratio of the clock outputted from the phase mixing unit and generates the control code corresponding to the detection result. A clock inversion driver(324) inverts and drives the clock outputted from the phase mixing unit with the pull-up driving power and the pull-down driving power.

Description

DUTY CIRCLE CORRECT CIRCUIT AND DELAY LOCKED LOOP CIRCUIT THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to a delay locked loop circuit (DLL) having a duty cycle correction circuit (DCC) of a semiconductor device. The present invention relates to a delay locked loop (DLL) having a duty cycle correction circuit (DCC) capable of performing a more accurate duty correction operation compared to the duty cycle correction circuit (DCC).

Synchronous semiconductor memory devices such as DDR SDRAM (Double Data Rate Synchronous DRAM) transfer data with external devices using an internal clock synchronized with an external clock input from an external device such as a memory controller (CTRL).

This is because, in order to stably transfer data between the memory and the memory controller, the time synchronization between the external clock and the data output from the memory is very important.

At this time, the data output from the memory is output in synchronization with the internal clock. When the internal clock is initially applied to the memory, the internal clock is applied in synchronization with the external clock, but is delayed through each component in the memory and output to the outside of the memory. If it does, it is output out of sync with external clock.

Therefore, for stable transmission of data output from the memory, the delayed internal clock is accurately positioned at the edge or center of the external clock applied by the memory controller while passing through each component in the memory transmitting the data. To do this, the time the data is on the bus must be compensated back to the internal clock so that the internal and external clocks are synchronized.

Clock synchronizing circuits that perform this role include a phase locked loop (PLL) circuit and a delay locked loop (DLL) circuit.

Of these, when the frequency of the external clock and the internal clock are different, the frequency-locking function should be used. Therefore, a phase locked loop (PLL) is used. However, when the frequency of the external clock is the same as the frequency of the internal clock, a delayed fixed loop (DLL) circuit that can be implemented in a relatively small area is mainly used compared to the phase locked loop (PLL).

That is, in the case of the semiconductor memory device, since the frequency used is the same, a delay locked loop (DLL) circuit is mainly used as the clock synchronization circuit.

In particular, the semiconductor memory device includes a register for storing a fixed delay value, and when the power is turned off, the fixed delay value is stored in the register, and when the power is applied again, the internal clock is fixed by loading the fixed delay value stored in the register. In this case, the clock synchronization operation can be performed when the phase difference between the internal clock and the external clock is relatively small during the initial operation of the semiconductor memory device, and the delay value of the register according to the phase difference between the internal clock and the external clock even after the initial operation. The most widely used register controlled delayed loop circuit is to adjust the fluctuation width to reduce the time it takes for the internal and external clocks to synchronize.

1 is a block diagram showing a general register controlled delay locked loop (DLL) circuit.

Referring to FIG. 1, a general register controlled delay locked loop (DLL) circuit includes a phase comparator 100R and 100F and a control clock for comparing phases of a source clock REFCLK and a feedback clock fbclkr and fbclkf. The comparison result of the control pulse generator 110 and the phase comparator 100R, 100F for generating the plurality of control pulses PULSE2, PULSE3, and PULSE6 sequentially activated in response to the delay shifting update period in response to CONTCLK). mode control units 160R and 160F for generating mode control signals FM_END, lock_state, FM_END_F, and lock_statef corresponding to fine, coarse, FM_pdout, finef, coarsef, and FM_pdoutf, and mode control signals FM_END, lock_state, FM_END_F, In the normal mode and the coarse mode, the first delay shift control signals frclk_sl, frclk_sr, srclk_sl, srclk_sr, ffclk_sl, ffclk_sr, sfclk_sl, and sfclk_sl in response to lock_statef) Generate In the high fast mode, the delay shift control units 130R and 130F for generating the second delay shift control signals fastr_sl and fastf_sl for controlling the delay shifting operation, and the first delay shift control signal in the normal mode In response to frclk_sl, frclk_sr, srclk_sl, srclk_sr, ffclk_sl, ffclk_sr, sfclk_sl, and sfclk_sr), the phase shift of the internal clocks (clkin1, clkin2) is delayed in units of delay units. Delay shifts the phases of clkin1 and clkin2 in units smaller than the delay unit.In fast mode, the phases of the internal clocks clkin1 and clkin2 are delayed in response to the second delay shift control signals fastr_sl and fastf_sl. Includes a unit-receives the phase delay unit 140R, 140F for shift-shifting the unit, and the output clocks (ifbclkr, ifbclkf) of the duty compensation unit 120 The delay replication model units 150R and 150F for outputting the feedback clocks fbclkr and fbclkf reflecting the actual delay conditions of the internal clock path, and the source clocks REFCLK whose phases are synchronized with each other by buffering the external clock CLK. And a clock buffer 180B for generating the control clock CONTCLK and the internal clocks clkin1 and clkin2, a power down of the inverted signal ckeb_com of the clock enable signal and a mode register set (MRS). A power for generating a clock buffer enable signal CLKBUF_ENb for controlling the operation of the clock buffer unit 180B in response to a signal including mode information and a signal containing precharge information. Operation of the delay locked loop (DLL) circuit in response to the down mode controller 180A and the delay locked loop (DLL) reset signal (dll_resetb) and the delay locked loop (DLL) deactivation signal (dis_dll) input from the outside of the semiconductor memory device. Reset to control Invert the phase of the delay locked loop (DLL) control unit 190 for generating a signal and one of the output clocks (mixout_r, mixout_f) of the phase delay units 140R and 140F (mixout_r or mixout_f). Mainly by outputting with mixout_f-, a rising inside clock (rising_clk) having a rising edge corresponding to the rising edge of the inner clocks (clkin1, clkin2) and a falling inside having a rising edge corresponding to the falling edge of the inner clocks (clkin1, clkin2). Pre-duty compensator 119 for outputting a clock falling_clk and a duty-corrector 120 for correcting the duty ratio of the output clocks (rising_clk, falling_clk) of pre-duty compensator 119 in the locked state. ) And a delay locked loop (DLL) driver 170 for outputting the delay locked loop output clocks (irclkdll and ifclkdll) driving the output clocks (ifbclkr and ifbclkf) of the duty compensation unit 120 to the output driver of the semiconductor memory device. ).

The operation thereof will be described based on the configuration of the general register control type delay locked loop (DLL) circuit described above.

First, the above-described register controlled delay locked loop (DLL) circuit is a delay locked loop (DLL) circuit operating in a dual-loop (Dual-Loop) method, wherein the dual loop method is a delay locked loop (DLL) circuit driver ( Two clocks with opposite phases are used before performing the duty ratio correction operation so that the duty ratio of the delay locked loop output clocks (irclkdll and ifclkdll) outputted through 170) is 50 to 50. By performing the delay locked loop operation, if the locked state through the delay locked loop operation means a method of performing the duty ratio correction operation.

That is, the rising edge corresponding to the rising edge corresponding to the rising edge of the rising edge of the internal clocks clkin1 and clkin2 and the rising edge corresponding to the falling edges of the internal clocks clkin1 and clkin2 are determined. A method of performing a delay locked loop operation using a falling inner clock (falling_clk).

In contrast to the dual loop method, there is a single loop method, in which the single loop method corresponds to the rising edge or the falling edge of the inner clock (clkin1, clkin2) before performing the duty compensation operation. The delay locked loop operation is performed using only one clock, and when the locked state is reached through the delay locked loop operation, the duty ratio correction operation is performed.

Specifically, among the components of the delay locked loop (DLL) circuit, the mode control units 160R and 160F, the phase comparators 100R and 100F, the delay shift control units 130R and 130F, the phase delay units 140R and 140F, and the delays. The replica model units 150R and 150F adjust the phases of the blocks 100R, 160R, 130R, 140R, and 150R and the falling internal clocks (falling_clk) for adjusting the phases of the rising internal clocks (rising_clk) having the same circuit configuration. It is divided into blocks for adjustment (100F, 160F, 130F, 140F, 150F).

Here, the blocks 100R, 160R, 130R, 140R, and 150R for adjusting the phase of the rising inner clock (rising_clk) may have a rising edge of the rising inner clock (rising_clk) and a rising edge of the source clock (REFCLK) even before the locked state. Adjust the phase of the rising internal clock (rising_clk) to be synchronized, and adjust the phase of the rising internal clock (rising_clk) so that the rising edge of the rising clock (REFCLK) and the rising edge of the source clock (REFCLK) are synchronized even after the locked state. The reason for this is to make the locking state before the locking state and to compensate for the fluctuation in the phase of the rising clock (rising_clk) after the locking state due to the fluctuation of the power supply voltage or noise applied from the outside of the semiconductor memory device.

In addition, the blocks 100F, 160F, 130F, 140F, and 150F for adjusting the phase of the falling inner clock (falling_clk) have a rising edge of the falling inner clock (falling_clk) and a rising edge of the source clock (REFCLK) before the locked state. Adjusts the phase of the falling internal clock (falling_clk) to be synchronized, but only some (130F, 140F) operate after the locked state and do not operate the remaining (100F, 160F, 150F) after locking, to create a locked state before the locked state. After the locked state, since the duty is corrected by the duty compensator 120 at the same time as the locked state, the phase of the falling inner clock falling_clk is changed by the output of the delay locked loop (DLL) driver 170. Does not affect.

For reference, in a general dual loop register-controlled delay locked loop (DLL) circuit, the locked state includes both the rising edge of the source clock (REFCLK) and the rising internal clock (rising_clk) and the rising edge of the falling internal clock (falling_clk). It means a synchronized state-within a certain margin of error.

FIG. 2 is a circuit diagram showing in detail the configuration of a duty compensator according to the prior art among the components of the general register controlled delay locked loop (DLL) circuit shown in FIG.

Referring to FIG. 2, the duty cycle corrector 120 according to the related art detects a phase difference between the positive clock rising_clk and the negative clock falling_clk, and reflects the weight corresponding to the detection result. A phase mixing unit 122 for mixing the phases of the overclocking_clk and a clock inversion driving unit 124 for semi-driving the clocks ifbclkr and ifbclkf output from the phase mixing unit 122 are provided.

Here, the phase mixing unit 122 detects the phase difference between the positive clock rising_clk and the falling clock falling_clk, and outputs the weight selection signal 1232 for outputting the weight selection signal wr_sel, and the weight selection signal wr_sel. In response to the mixing control unit 1224 for generating mixing control signals CTRL1, CTRL1b, CTRL2, CTRL2b, CTRL3, CTRL3b for controlling the mixing ratio of the positive clock rising_clk and the subclock falling_clk. The positive clock (rising_clk) and the negative clock (falling_clk) applied to (IN_ND1, IN_ND2) are applied to the same output terminal (OUT_ND) with varying driving forces in response to the mixed control signals CTRL1, CTRL1b, CTRL2, CTRL2b, CTRL3, and CTRL3b, respectively. A clock mixing unit 1226 for mixing the positive clock rising_clk and the sub-clock falling_clk by inversion driving is provided. In addition, the duty cycle correction enable signal generator 1228 for generating the duty cycle correction enable signal DCC_ENb in response to the signals lock_state and lock_statef indicating that the positive clock rising_clk and the sub-clock falling_clk are locked. It is further provided.

For reference, the duty cycle correction enable signal DCC_ENb is applied to the mixed controller 1224 together with the clock buffer enable signal CLKBUF_ENb to generate the mixed control signals CTRL1, CTRL1b, CTRL2, CTRL2b, CTRL3, and CTRL3b. Affects behavior

In addition, the clock mixing unit 1226 shown in FIG. 2 is a portion corresponding to the positive clock rising_clk, and a portion corresponding to the negative clock falling_clk is not shown. The reason is that the part corresponding to the subclock (falling_clk) and the part corresponding to the positive clock (rising_clk) are almost the same, except that the clocks inputted through different input terminals IN_ND1 and IN_ND2 are opposite to each other. to be.

That is, the clock mixing unit 1226 corresponding to the positive clock rising_clk shown in FIG. 2 is applied with the positive clock rising_clk to the first input terminal IN_ND1 and the falling clock falling_clk to the second input terminal IN_ND2. Is applied, but the clock mixing unit 1226 corresponding to the sub-clock falling_clk not shown in FIG. 2 is supplied with the positive clock rising_clk to the second input terminal IN_ND2 and the sub-clock to the first input terminal IN_ND1. Only falling_clk is applied, the rest of the configuration is exactly the same.

Therefore, the components of the duty cycle correction circuit DCC according to the related art, which will be described later, will be described only for a portion corresponding to the positive clock rising_clk in the same manner as the phase mixing unit 122. In other words, the part corresponding to the sub-clock (falling_clk) is also the same as the part corresponding to the positive clock (rising_clk) and the input / output signal names are different, the configuration and operation is almost the same.

The clock inversion driver 124 is an inverter composed of one PMOS transistor P1 and one NMOS transistor N1. The clock inversion driver 124 inverts and drives the clock loaded on the output node OUT_ND of the phase mixer 122. It serves as a correction clock (ifbclkr).

That is, when the duty ratio is corrected in the phase mixing unit 122, the mixing control signals CTRL1, CTRL1b, CTRL2, CTRL2b, CTRL3, and CTRL3b are turned on / off as shown in the drawing. Off) Phase mixing is performed by inverting the positive clock (rising_clk) and the negative clock (falling_clk) with different driving forces using a plurality of controlled inverters (INV1, INV2, INV3, INV4, INV5, and INV6). The phase of the clock loaded on the output node OUT_ND of the negative part 122 is in a state opposite to that of the positive clock rising_clk and the negative clock falling_clk, and the clock inversion driver 124 may use the phase mixing part Inverting the clock loaded on the output node OUT_ND of 122).

On the other hand, the configuration of the clock inversion driver 124 again, as described above, having a structure of a general inverter that performs the inversion driving operation using one PMOS transistor P1 and one NMOS transistor N1. Able to know.

That is, in the period in which the clock loaded on the output node OUT_ND of the phase mixing unit 122 is activated with logic 'high', the inverter is inverted and driven by the NMOS transistor N1 included in the clock inversion driver 124. The correction clock ifbclkr is output as a section in which logic 'low' is inactivated, and the clock loaded on the output node OUT_ND of the phase mixing unit 122 is clocked in a section in which logic 'low' is inactive. Inverted and driven by the PMOS transistor P1 included in the inversion driver 124, the duty correction clock ifbclkr is output as a section in which logic 'high' is activated.

At this time, assuming that the duty ratio of the clock loaded on the output node OUT_ND is correctly adjusted to 50 to 50 by the duty ratio correction operation of the phase mixer 122, the duty ratio of the duty correction clock ifbclkr is 50 to 50. In order to maintain the state correctly adjusted, the driving force of the PMOS transistor P1 and the NMOS transistor N1 included in the clock inversion driver 124 must be completely the same.

However, it is only theoretically possible to implement the driving force of the PMOS transistor P1 and the NMOS transistor N1 provided in the clock inversion driver 124 to be completely the same, and the duty cycle correction circuit produced through the actual process process may be implemented. In (DCC), the driving force of the PMOS transistor P1 and the NMOS transistor N1 provided in the clock inversion driver 124 due to various problems-usually PVT (process, voltage, temperature) variation is completely equal. impossible.

As described above, since the driving force of the PMOS transistor P1 and the NMOS transistor N1 included in the clock inversion driver 124 cannot be completely equal, the output node OUT_ND is caused by the duty ratio correction operation of the phase mixing unit 122. Even if the duty ratio of the clock is accurately set to 50 to 50, the duty ratio of the duty correction clock (ifbclkr) output through the clock inversion driver 124 may not be maintained at 50 to 50.

The internal circuit of a semiconductor device such as a data output driver using the duty correction clock (ifbclkr) may not operate normally due to a problem that the duty ratio of the duty correction clock (ifbclkr) does not maintain 50 to 50 accurately. Problems may occur that do not operate properly.

The shorter one period tCK of the operation clock of the semiconductor device is, the greater the influence is, which may prevent the semiconductor device from operating normally.

The present invention is proposed to solve the above problems in the prior art, the duty cycle correction circuit using a control code whose value is changed according to the duty ratio of the clock output from the duty cycle correction circuit (DCC) A duty cycle correction circuit (DCC) capable of performing a more precise duty correction operation than a conventional duty cycle correction circuit (DCC) through a feedback operation that varies a driving force of a circuit for driving a clock output from the (DCC). The purpose is to provide.

According to an aspect of the present invention for achieving the above object to be solved, to detect the phase difference between the positive clock and the negative clock, and to mix the phase of the positive and negative clock by reflecting the weight corresponding to the detection result Phase mixing means; Duty ratio detection means for detecting a duty ratio of the clock output from the phase mixing means and generating a control code corresponding to the detection result; And a clock inversion driving means for inverting the clock output from the phase mixing means with a pull-up driving force and a pull-down driving force that change in response to the control code, respectively.

According to another aspect of the present invention for achieving the above object, the first and second internal clocks corresponding to the first and second clock edges of the source clock is delayed to achieve delay lock. A delay high integer stage for outputting as 2 delay locked clocks; Phase mixing means for detecting a phase difference between the first and second delay locked clocks and mixing phases of the first and second delay locked clocks by reflecting a weight corresponding to the detection result; Duty ratio detection means for detecting a duty ratio of the clock output from the phase mixing means and generating a control code corresponding to the detection result; And a clock inversion driving means for inverting the clock output from the phase mixing means with a pull-up driving force and a pull-down driving force that change in response to the control code, and outputting the clock as a delay locked loop clock. DLL).

According to the present invention, the driving force of the circuit for driving the clock output from the duty cycle correction circuit (DCC) using a control code whose value changes according to the duty ratio of the clock output from the duty cycle correction circuit (DCC) is determined. By performing a variable feedback operation, a more accurate duty correction operation can be performed.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be configured in various different forms, only this embodiment is intended to complete the disclosure of the present invention and to those skilled in the art the scope of the present invention It is provided to inform you completely.

3 is a circuit diagram showing in detail the configuration of a duty compensator according to an embodiment of the present invention among the components of the general register controlled delay locked loop (DLL) circuit shown in FIG.

Referring to FIG. 3, the duty compensator 320 according to an embodiment of the present invention detects a phase difference between the positive clock rising_clk and the negative clock falling_clk, and reflects the weight corresponding to the detection result to the positive clock. Detects the duty ratio of the phase mixing unit 322 for mixing the phase of the rising_clk and the sub-clocking_clk, and the clock ifbclkr output from the phase mixing unit 322, and the control code corresponding to the detection result. The duty ratio detector 326 for generating (N <1: n>, P <1: n>) and the control code (N <1: n>, P <1: n>), respectively, change in response to And a clock inversion driver 324 for inverting the clock ifbclkr output from the phase mixing unit 322 by the pull-up driving force and the pull-down driving force.

Here, the phase mixing unit 322 detects a phase difference between the positive clock rising_clk and the subclock falling_clk and outputs a weight selection signal wr_sel and a weight selection signal wr_sel. In response to the mixing control unit 3224, which generates mixing control signals CTRL1, CTRL1b, CTRL2, CTRL2b, CTRL3, CTRL3b for controlling the mixing ratio of the forward clock rising_clk and the subclock falling_clk. The positive clock (rising_clk) and the negative clock (falling_clk) applied to (IN_ND1, IN_ND2) are applied to the same output terminal (OUT_ND) with varying driving forces in response to the mixed control signals CTRL1, CTRL1b, CTRL2, CTRL2b, CTRL3, and CTRL3b, respectively. By inversion driving, a clock mixing section 3326 for mixing the positive clock rising_clk and the sub-clock falling_clk is provided. In addition, the duty cycle correction enable signal generator 3328 generates the duty cycle correction enable signal DCC_ENb in response to the signals lock_state and lock_statef indicating that the clock clock rising_clk and the clock fall_clk are locked. It is further provided.

For reference, the duty cycle correction enable signal DCC_ENb is applied to the mixing control unit 3224 together with the clock buffer enable signal CLKBUF_ENb to generate the mixed control signals CTRL1, CTRL1b, CTRL2, CTRL2b, CTRL3, and CTRL3b. Affects behavior

In addition, the clock mixing unit 3326 illustrated in FIG. 2 is a portion corresponding to the positive clock rising_clk, and a portion corresponding to the subclock falling_clk is not shown. The reason is that the part corresponding to the subclock (falling_clk) and the part corresponding to the positive clock (rising_clk) are almost the same, except that the clocks inputted through different input terminals IN_ND1 and IN_ND2 are opposite to each other. to be.

That is, the clock mixing unit 3326 corresponding to the positive clock rising_clk illustrated in FIG. 2 is supplied with the positive clock rising_clk to the first input terminal IN_ND1 and the falling clock falling_clk to the second input terminal IN_ND2. Is applied, but the clock mixing unit 3326 corresponding to the sub-clock falling_clk not shown in FIG. 2 is supplied with the positive clock rising_clk to the second input terminal IN_ND2 and the sub-clock to the first input terminal IN_ND1. Only falling_clk is applied, the rest of the configuration is exactly the same.

Therefore, the components of the duty cycle correction circuit DCC according to the related art, which will be described later, will be described only for the portion corresponding to the positive clock rising_clk in the same manner as the phase mixing unit 322. In other words, the part corresponding to the sub-clock (falling_clk) is also the same as the part corresponding to the positive clock (rising_clk) and the input / output signal names are different, the configuration and operation is almost the same.

The duty ratio detector 326 detects the enable signal for generating the detection enable signals H_EN and L_EN whose logic levels change in response to the duty ratio of the clock ifbclkr output from the phase mixer 322. The signal generator 3262 and the control code shifting unit 3264 for shifting the values of the control codes N <1: n> and P <1: n> in response to the detection enable signals H_EN and L_EN. And a control code initialization unit 3266 for initializing the values of the control codes N <1: n> and P <1: n> in response to the clock buffer enable signal CLKBUF_ENb.

In addition, the clock inversion driving unit 324 is a phase mixing unit with a driving force that changes in response to the predetermined first code P <1: n> of the control codes N <1: n> and P <1: n>. A predetermined second of the pull-up reversal driver 3324 and the control codes N <1: n> and P <1: n> for pull-up reversal driving of the inactivation section of the clock ifbclkr outputted at 322; And a pull-down inversion driver 3244 for pull-down inversion driving of the activation section of the clock ifbclkr output from the phase mixing unit 322 with a driving force that changes in response to the code N <1: n>.

Here, the pull-up inversion driver 3322 may include a plurality of switch PMOS transistors drain-connected at a source voltage VDD terminal connected in source in response to a clock ifbclkr output from the phase mixing unit 322 applied to the gate. Responding to the plurality of driving PMOS transistors PDR <1: n> for adjusting the amount of current flowing to the source terminal of PSW <1: n> and the first code P <1: n> applied to the gate And a plurality of switch PMOS transistors PSW <1: n> for controlling the amount of current flowing from the drain terminal of each of the source-connected driving PMOS transistors PDR <1: n> to the drain-connected duty compensation clock ifbclkr terminal. ). In addition, in response to the clock ifbclkr output from the phase mixing unit 322 applied to the gate, the current flows from the source connected power supply voltage VDD to the source terminal of the drain-connected default switch PMOS transistor PSW <0>. Drain at the drain terminal of the default driving PMOS transistor PDR <0> for adjusting the amount of current and source-connected default driving PMOS transistor PDR <0> in response to the potential level of the ground voltage VSS applied to the gate. A default switch PMOS transistor PSW <0> is further provided for controlling the amount of current flowing to the connected duty correction clock ifbclkr stage.

In addition, the pull-down inversion driver 3244 may include source terminals of the plurality of switch NMOS transistors NSW <1: n> connected in drain in response to a clock ifbclkr output from the phase mixing unit 322 applied to the gate. In response to the plurality of driving NMOS transistors NDR <1: n> for adjusting the amount of current flowing to the source-connected ground voltage VSS terminal and a second code N <1: n> applied to the gate, A plurality of switch NMOS transistors NSW <1: n> for controlling the amount of current flowing to the drain of each of the driving NMOS transistors NDR <1: n> connected to a source at the drain-connected duty correction clock ifbclkr stage are connected. Equipped. In addition, the ground voltage VSS terminal connected to the source terminal of the plurality of default switch NMOS transistors NSW <0> drain-connected in response to the clock ifbclkr output from the phase mixer 322 applied to the gate. A source driving NMOS transistor NDR <0> for regulating the amount of current flowing to the source, and a source connected at the duty-corrected clock ifbclkr stage connected in response to the potential level of the power supply voltage VDD applied to the gate. A default switch NMOS transistor NSW <0> is further provided for adjusting the amount of current flowing to the drain of the default driving NMOS transistor NDR <0>.

Referring to the operation of the duty compensator 320 according to the embodiment of the present invention based on the above configuration as follows.

For reference, the operation of the phase mixing means 322 having the above-described configuration will not be described here because it is described in the known art.

First, the detection enable generator 3326 of the components of the duty ratio detector 326 may have a length in which a clock ifbclkr output from the phase mixer 322 is activated with logic 'high'. Predetermined length-the length that can be detected by comparing the length, which can be different depending on the performance of the phase detection circuit-The detection enable signal when longer than The first signal H_EN of (H_EN, L_EN) is activated with logic 'High', and the second signal L_EN is inactivated with logic 'Low' and output.

In addition, among the components of the duty ratio detector 326, the detection enable generator 3326 has a length in which a clock ifbclkr output from the phase mixer 322 is deactivated to a logic 'low'. Predetermined length rather than the length of the section that is activated by logic 'high'-Means a detectable length by comparing the length, and may have different values depending on the performance of the phase detection circuit-Detects enable signal when longer than The first signal H_EN of (H_EN, L_EN) is deactivated to logic 'low', and the second signal L_EN is activated to output logic 'high'.

In addition, among the components of the duty ratio detector 326, the detection enable generator 3262 may include a length of a section in which the clock ifbclkr output from the phase mixer 322 is activated with logic 'high'. The difference in the length of the section which is deactivated by logic 'Low' is the predetermined length-the length that can be detected by comparing the lengths, which can have different values depending on the performance of the phase detection circuit-in the shorter time, the detection enable signal The first signal H_EN of (H_EN, L_EN) is deactivated to logic 'low' and the second signal L_EN is deactivated to logic 'low' and output.

In addition, the control code shifting unit 3264 among the components of the duty ratio detector 326 activates the first signal H_EN of the detection enable signals H_EN and L_EN to a logic 'high', Shifting update period when the signal L_EN is inactive as logic 'low'-Operation period of the duty cycle correction circuit (DCC)-Control code (N <1: n>, P <1: n>) ) Shifts the values of logic '0' to logic '1' in a predetermined order. That is, the values of the control codes N <1: n> and P <1: n> are increased.

In addition, among the components of the duty ratio detector 326, the control code shifting unit 3264 deactivates the first signal H_EN of the detection enable signals H_EN and L_EN by a logic 'low', and the second signal. Shifting update period when the signal L_EN is logic 'High' active state-Operation cycle of the duty cycle correction circuit (DCC)-Control code (N <1: n>, P <1: n>) Shifting the values of logic '1' to logic '0' in a predetermined order. That is, the control codes N <1: n> and P <1: n> are reduced.

The control code shifting unit 3264 among the components of the duty ratio detection unit 326 deactivates the first signal H_EN of the detection enable signals H_EN and L_EN by a logic 'low', and the second signal. Shifting update period when the signal L_EN is inactive as logic 'low'-Operation period of the duty cycle correction circuit (DCC)-Control code (N <1: n>, P <1: n>) Does not shift). That is, it does nothing.

Specifically, referring to the operation of the control code shifting unit 3264 among the components of the duty ratio detection unit 326 by way of example, the initial value of the first control code P <1: n> is logic '1'. When the initial value of the second control code N <1: n> is logic '0', the first signal H_EN of the detection enable signals H_EN and L_EN is set to logic 'High'. When the activation and the second signal L_EN are deactivated and input to the logic 'low', the first code N <of the second control code N <1: n> having the value of logic '0' is input. 1>) to the nth code N <n> in order to shift the logic to '1'.

Similarly, when the initial value of the first control code P <1: n> is logic '1' and the initial value of the second control code N <1: n> is logic '0', detection is performed. When the first signal H_EN of the enable signals H_EN and L_EN is deactivated to logic 'low' and the second signal L_EN is activated to be logic 'high' and is input, the value of logic '1' The first code P <1> of the first control code P <1: n> to the nth code P <n> is shifted to logic '0' in order.

Further, the first to fifth codes P <1: 5> of the first control code P <1: n> are logic '0', and the first to the first control code P <1: n> are logical. When the sixth to nth codes P <6: n> are logic '1' and all the code values of the second control code N <1: n> are logic '0', the detection enable signal ( When the first signal H_EN of H_EN and L_EN is activated as logic 'high' and the second signal L_EN is deactivated and input as logic 'low', the logic signal has a value of '0'. After shifting the logic '1' from the fifth code P <5> of the first control code P <1: n> to the first code P <1> in order, the logic '0' The first code N <1> of the second control code N <1: n> having the value is shifted to logic '1' in order from the nth code N <n>.

Similarly, all code values of the first control code P <1: n> are logic '1', and the first to fifth codes N <1: 5 of the second control code N <1: n>. > Is a logic '1' and the detection enable signal (A) is set in a state where the sixth to nth codes P <6: n> of the second control code N <1: n> are logic '0'. When the first signal H_EN of H_EN and L_EN is deactivated to logic 'low' and the second signal L_EN is activated to be logic 'high' and is input, it has a value of logic '1'. The value of logic '1' after the shifting to the logic '0' from the fifth code N <5> of the second control code N <1: n> to the first code N <1> in order The first code P <1> of the first control code P <1: n> to n-th code P <n> is shifted to logic '1' in order.

Among the components of the clock inversion driving unit 324, the pull-up inversion driving unit 3322 is relatively smaller than the value of the logic '1' in the first control code P <1: n>. In many cases, a pull-up reversal operation of the inactivation section of the clock ifbclkr output from the phase mixing unit 322 with a relatively strong driving force performs an operation of increasing the activation section of the duty correction clock ifbclkr.

Also, among the components of the clock inversion driver 324, the pull-up inversion driver 3324 is relatively smaller than the value of logic '0' in the first control code P <1: n>. In many cases, a pull-up reversal operation of the inactivation section of the clock ifbclkr output from the phase mixer 322 with a relatively weak driving force reduces the activation section of the duty compensation clock ifbclkr.

Among the components of the clock inversion driving unit 324, the pull-down inversion driving unit 3244 has a value of logic '1' in the second control code N <1: n> relatively than a value of logic '0'. In many cases, a pull-down reversal operation of the activation section of the clock ifbclkr output from the phase mixing unit 322 with a relatively strong driving force increases the inactivation section of the duty correction clock ifbclkr.

Also, among the components of the clock inversion driver 324, the pull-down inversion driver 3244 is relatively smaller than the value of logic '1' in the second control code N <1: n>. In many cases, a pull-down reversal operation of an activation section of the clock ifbclkr output from the phase mixing unit 322 with a relatively weak driving force reduces an inactivation section of the duty compensation clock ifbclkr.

FIG. 4 is a timing diagram showing an operation waveform of the duty compensator according to the embodiment of the present invention shown in FIG.

Referring to FIG. 4, the operation waveforms of the duty compensator according to the embodiment of the present invention are <when the activation period of the initial compensation clock (ifbclkr) is longer than the inactivation period> and <the initial duty compensation clock (ifbclkr). If the inactivation interval of is longer than the activation interval, it may be divided into>.

First, if <the activation period of the duty correction clock (ifbclkr) is longer than the inactivation period at first>, the detection enable signal is detected in the first operation (1) in which the activation interval of the duty correction clock (ifbclkr) is longer than the inactivation period. The first signal H_EN of (H_EN, L_EN) is activated with logic 'High', the second signal L_EN is deactivated with logic 'Low' and accordingly the initial value is logic '0'. It can be seen that the first code N <1> of the second control code N <1: n> is shifted to logic '1'.

Thus, even if the first code N <1> of the second control code N <1: n> is changed from logic '0' to logic '1', the activation interval of the duty compensation clock ifbclkr is inactive. Even in the second longer operation (②), the first signal H_EN of the detection enable signals H_EN and L_EN is activated as logic 'high', and the second signal L_EN is logic 'low'. In this case, it can be seen that the second code N <2> of the second control code N <1: n> whose initial value was logic '0' is shifted to logic '1'.

The deactivation interval of the duty compensation clock (ifbclkr) is activated by changing the second code (N <2>) of the second control code (N <1: n>) from logic '0' to logic '1'. In the third operation ③ longer than the interval, the second signal L_EN of the detection enable signals H_EN and L_EN is activated with logic 'high', and the first signal H_EN is logic 'low' ( Low) is deactivated, and accordingly the second code N <2> of the second control code N <1: n>, which has been shifted to logic '1' in the second operation, is shifted back to logic '0'. Able to know.

In addition, during the first operation (①), the second operation (②), and the third operation (③) of <if the activation period of the duty correction clock (ifbclkr) is longer than the inactivation period>, the first control code ( It can be seen that P <1: n> keeps the initial logic '1'.

If the inactivation interval of the duty correction clock (ifbclkr is longer than the activation interval), the detection enable signal is detected in the first operation (4) in which the inactivation interval of the duty correction clock (ifbclkr) is longer than the activation interval. The second signal L_EN of (H_EN, L_EN) is activated with logic 'High', the first signal H_EN is deactivated with logic 'Low', and accordingly the initial value is logic '1'. It can be seen that the first code P <1> of the first control code P <1: n> is shifted to logic '0'.

Thus, even if the first code P <1> of the first control code P <1: n> is changed from logic '1' to logic '0', the inactivation interval of the duty compensation clock ifbclkr is activated. Even in the longer second operation (5), the second signal L_EN of the detection enable signals H_EN and L_EN is activated as logic 'high', and the first signal H_EN is logic 'low'. In this case, it can be seen that the second code P <2> of the first control code P <1: n> whose initial value was logic '1' is shifted to logic '0'.

The activation period of the duty compensation clock ifbclkr is deactivated by changing the second code P <2> of the first control code P <1: n> from logic '1' to logic '0'. In the third operation (6) longer than the interval, the first signal H_EN of the detection enable signals H_EN and L_EN is activated as logic 'high' and the second signal L_EN is logic 'low' ( Low) is deactivated, and accordingly, the second code P <2> of the first control code P <1: n>, which has been shifted to logic '0' in the second operation (⑤), returns to logic '1'. It can be seen that it is shifted.

In addition, during the first operation (④), the second operation (⑤) and the third operation (⑥) of <if the inactivation interval of the duty correction clock (ifbclkr) is longer than the activation interval> the second control code ( It can be seen that N <1: n> keeps the initial logic '0'.

As described above, when the embodiment of the present invention is applied, the duty correction clock (ifbclkr) is used by using a control code whose value changes according to the duty ratio of the duty correction clock (ifbclkr) output from the duty cycle correction circuit (DCC). The duty cycle of the duty correction clock (ifbclkr) can be tuned more precisely by performing a feedback operation to change the driving force of the circuit for driving the N-axis.

As a result, a more precise duty correction operation may be performed than the duty cycle correction circuit DCC according to the related art.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill.

For example, in the above-described embodiment, the configuration and operation of the duty cycle correction circuit DCC have been described with respect to the positive clock rising_clk. In the present invention, the duty cycle correction based on the negative clock falling_clk instead of the rising clock rising_clk. The configuration and operation of the circuit DCC are defined, or the configuration and operation of the duty cycle correction circuit DCC are defined based on the positive clock rising_clk and the falling clock falling_clk, respectively.

In addition, the logic gate and the transistor illustrated in the above embodiment should be implemented in different positions and types depending on the polarity of the input signal.

1 is a block diagram showing a general register controlled delay locked loop (DLL) circuit.

FIG. 2 is a circuit diagram showing in detail the configuration of a duty compensator according to the prior art among the components of the general register controlled delay locked loop (DLL) circuit shown in FIG.

3 is a circuit diagram showing in detail the configuration of a duty compensator according to an embodiment of the present invention among the components of the general register controlled delay locked loop (DLL) circuit shown in FIG.

FIG. 4 is a timing diagram showing an operating waveform of the duty compensator according to the embodiment of the present invention shown in FIG.

* Explanation of symbols for main parts of the drawings

120, 320: Duty complementary part 122, 322: Phase mixing part

124, 324: clock inversion driver 326: duty ratio detector

3262: detection enable signal generator 3264: control code shifting unit

Claims (25)

Phase mixing means for detecting a phase difference between the positive clock and the negative clock and mixing phases of the positive and negative clocks by reflecting a weight corresponding to the detection result; Duty ratio detection means for detecting a duty ratio of the clock output from the phase mixing means and generating a control code corresponding to the detection result; And Clock inversion driving means for inverting the clock output from the phase mixing means with a pull-up driving force and a pull-down driving force that change in response to the control code; Duty cycle correction circuit (DCC) having a. The method of claim 1, The phase mixing means, A phase detector for detecting a phase difference between the positive clock and the subclock to output a weight selection signal; A mixing control unit generating a mixing control signal for controlling a mixing ratio of the positive clock and the sub-clock in response to the weight selection signal; And And a clock mixing section for mixing the positive and negative clocks by inverting the positive and negative clocks applied to different input terminals to the same output terminal, respectively, in response to the mixed control signal. Correction circuit (DCC). The method of claim 1, The duty ratio detecting means, A detection enable signal generation unit for generating a detection enable signal whose logic level changes in response to the duty ratio of the clock output from the phase mixing means; And And a control code shifting unit for shifting the value of the control code in response to a detection enable signal. The method of claim 3, The detection enable signal generator, The duty cycle of activating the first signal of the detection enable signal and deactivating the second signal when the length of the activating section of the clock output from the phase mixing means is longer than the length of the inactivating section. Cycle Compensation Circuit (DCC). The method of claim 3, The detection enable signal generator, The duty cycle characterized in that the first signal of the detection enable signal is inactivated, the second signal is activated and outputted when the length of the inactivation section of the clock output from the phase mixing means is longer than the length of the activation section. Cycle Compensation Circuit (DCC). The method of claim 3, The detection enable signal generator, And a duty cycle correction circuit for deactivating and outputting the first and second signals of the detection enable signal when the difference between the length of the activation section and the inactivation section of the clock output from the phase mixing means is shorter than a predetermined length. (DCC). The method of claim 3, The control code shifting unit, The duty of shifting the values of logic '0' in the control code to logic '1' in a predetermined order every shifting update period when the first signal of the detection enable signal is activated and the second signal is inactive. Cycle Compensation Circuit (DCC). The method of claim 7, wherein The control code shifting unit, The duty of shifting the values of logic '1' in the control code to logic '0' in a predetermined order every shifting update period when the first signal of the detection enable signal is inactive and the second signal is in an active state. Cycle Compensation Circuit (DCC). The method of claim 3, The control code shifting unit, And the control code is not shifted every shifting update period when the first and second signals of the detection enable signal are in an inactive state. The method of claim 1, The clock inverting means, A pull-up reversal driver configured to pull-up reversal of an inactive section of a clock output from the phase mixing means with a driving force that changes in response to a predetermined first code among the control codes; And A duty cycle correction circuit (DCC) comprising a pull-down inversion driver for pull-down inversion driving of the clock output from the phase mixing means with a driving force that changes in response to a predetermined second code among the control codes (DCC) ). The method of claim 10, The pull up reversal drive unit, When the value of logic '0' in the first code is greater than the value of logic '1', the clock output is activated by pull-up reversal operation of the inactivation section of the clock output from the phase mixing means with a relatively strong driving force. Duty cycle correction circuit (DCC), characterized in that to increase the interval. The method of claim 10, The pull up reversal drive unit, When the value of logic '1' in the first code is greater than the value of logic '0', the clock output is activated by pull-up reversal of the inactivation period of the clock output from the phase mixing means with relatively weak driving force. Duty cycle correction circuit (DCC), characterized in that to reduce the interval. The method of claim 10, The pull down inversion driving unit, When the value of logic '1' in the second code is larger than the value of logic '0', the clock output is inactivated by pull-down inverting the activation period of the clock output from the phase mixing means with a relatively strong driving force. Duty cycle correction circuit (DCC), characterized in that to increase the interval. The method of claim 10, The pull down inversion driving unit, If the value of logic '0' in the second code is greater than the value of logic '1', the inactivation period of the clock output by pull-down inverting the activation section of the clock output from the phase mixing means with a relatively weak driving force. Duty cycle correction circuit (DCC), characterized in that to reduce the. Delay lock means for delaying the first and second internal clocks corresponding to the first and second clock edges of the source clock and outputting the first and second delay lock clocks to achieve delay lock; Phase mixing means for detecting a phase difference between the first and second delay locked clocks and mixing phases of the first and second delay locked clocks by reflecting a weight corresponding to the detection result; Duty ratio detection means for detecting a duty ratio of the clock output from the phase mixing means and generating a control code corresponding to the detection result; And Clock inversion driving means for inverting the clock output from the phase mixing means with a pull-up driving force and a pull-down driving force that change in response to the control code to output as a delay locked loop clock; Delay fixed loop circuit (DLL) having a. The method of claim 15, The phase mixing means, A phase detector for detecting a phase difference between the first delay locked clock and the second delay locked clock and outputting a weight selection signal; A mixing controller configured to generate a mixing control signal for controlling a mixing ratio of the first delay locked clock and the second delay locked clock in response to the weight selection signal; And A clock mixing section for mixing the first and second delay locked clocks by inverting the first and second delay locked clocks applied to different input terminals to the same output terminal with varying driving forces in response to the mixed control signal, respectively; Delay fixed loop circuit (DLL) characterized in that it comprises. The method of claim 15, The duty ratio detecting means, A detection enable signal generation unit for generating a detection enable signal whose logic level changes in response to the duty ratio of the clock output from the phase mixing means; And And a control code shifting unit for shifting a value of the control code in response to a detection enable signal. The method of claim 17, The detection enable signal generator, When the length of the activation section of the clock output from the phase mixing means is longer than the length of the inactivation section longer than the predetermined length by activating the first signal of the detection enable signal, deactivated and outputs the second signal, When the length of the inactivation section of the clock output from the phase mixing means is longer than the length of the activation section more than a predetermined length, the first signal of the detection enable signal is inactivated, the second signal is activated and outputted, A delay locked loop circuit configured to deactivate and output the first and second signals of the detection enable signal when the difference between the length of the activation section and the inactivation section of the clock output from the phase mixing means is shorter than a predetermined length; (DLL). The method of claim 17, The control code shifting unit, When the first signal of the detection enable signal is activated and the second signal is inactive, shifting values of logic '0' in the control code to logic '1' in a predetermined order every shifting update period. When the first signal of the detection enable signal is inactive and the second signal is in an active state, shifting values of logic '1' in the control code to logic '0' in a predetermined order every shifting update period. And the control code is not shifted every shifting update period when the first and second signals of the detection enable signal are in an inactive state. The method of claim 15, The clock inverting means, A pull-up reversal driver configured to pull-up reversal of the inactivation section of the clock output from the phase mixing means with a driving force that changes in response to a predetermined first code among the control codes; And A delay locked loop circuit comprising a pull-down inversion driver for pull-down inversion driving of the clock outputted from the phase mixing means with a driving force that changes in response to a predetermined second code among the control codes (DLL) ). The method of claim 20, The pull up reversal drive unit, When the value of logic '0' in the first code is more than the value of logic '1', the delay locked loop clock is driven by inverting the inactive section of the clock output from the phase mixing means with a relatively strong driving force. Delayed fixed loop circuit (DLL), characterized in that to increase the activation interval of the. The method of claim 20, The pull up reversal drive unit, If the value of logic '1' in the first code is more than the value of logic '0', the delay locked loop clock is driven by inverting the inactive section of the clock output from the phase mixing means with a relatively weak driving force. Delayed fixed loop circuit (DLL), characterized in that to reduce the activation interval of the. The method of claim 20, The pull down inversion driving unit, If the value of logic '1' in the second code is more than the value of logic '0', the delay locked loop clock is driven by pull-down reversal of the activation period of the clock output from the phase mixing means with a relatively strong driving force. Delayed fixed loop circuit (DLL), characterized in that to increase the deactivation interval of the. The method of claim 20, The pull down inversion driving unit, If the value of logic '0' in the second code is more than the value of logic '1', the delay locked loop clock is pulled inverted by activating the activation section of the clock output from the phase mixing means with a relatively weak driving force. Delay fixed loop circuit (DLL), characterized in that to reduce the inactivation period. The method of claim 15, The delay fixing means, A first phase comparator for comparing phases of the source clock and the first feedback clock; A second phase comparator for comparing phases of the source clock and the second feedback clock; A first clock delay unit for delaying the first internal clock for a time corresponding to a comparison result of the first phase comparison unit and outputting the first internal clock as the first delay locked clock; A second clock delay unit for delaying the second internal clock by the time corresponding to the comparison result of the second phase comparison unit and outputting the second delay clock as the second delay locked clock; A first delay replication model unit for outputting the first delay clock as the first feedback clock by reflecting an actual delay condition of the first internal clock path; And And a second delayed replication model unit for outputting the second delayed clock as the second feedback clock to reflect the actual delay condition of the second internal clock path.

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