KR20090114958A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided to prevent an area of a semiconductor memory device from increasing by sharing a voltage terminal driving circuit and a voltage detection circuit. CONSTITUTION: A discharge pulse generator(350) generates a discharge pulse determining an activation section in response to an active signal and an auto refresh signal corresponding to banks. A discharge common voltage detector(300) detects the voltage level of the internal voltage terminal based on a first target level in response to the discharge pulse. A discharge common driver(310) discharges and drives the internal voltage terminal in response to the output signal of the discharge common voltage detector.

Description

Semiconductor memory device {SEMICONDUCTOR MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to a semiconductor memory device having a charge driving circuit for charge driving an internal voltage and a discharge drive circuit for discharging an internal voltage.

As the continuous scaling down of the line width and the cell size constituting the semiconductor memory chip proceeds, the voltage reduction of the power supply voltage is accelerated, and accordingly, a design technique for satisfying the performance required in a low voltage environment is required.

Currently, most semiconductor memory chips are provided with an internal voltage generator circuit for generating an internal voltage by receiving a power supply voltage VDD from the outside to supply a voltage necessary for the operation of the chip internal circuit.

In particular, in the case of a memory device using a bit line sensing amplifier such as DRAM, a core voltage VCORE is used as a voltage for sensing cell data.

When the word line selected by the row address is activated, data of a plurality of memory cells connected to the word line is transferred to the bit line, and the bit line sense amplifier senses and amplifies the voltage difference between the pair of bit lines.

Thousands of these bitline sense amplifiers typically operate at one time, which causes a large amount of current from the core voltage (VCORE) stage that is used to drive the pull-up power line (usually RTO) of the bitline sense amplifier. It is consumed at once.

However, it is difficult to amplify the data of many cells at once in a short time by using the core voltage VCORE in the trend that the operating voltage decreases.

In order to solve this problem, the RTO power line of the bit line sense amplifier may be operated at a level higher than the core voltage (VCORE) for a predetermined period of time during the operation of the bit line sense amplifier immediately after the charge sharing between the memory cell and the bit line. The bit-line sense amplifier overdriving method (typically driven by the supply voltage (VDD)) is adopted.

In this way, when the external power supply voltage VDD is used as the overdriving voltage, since a voltage input from the outside is sufficient, the data of a large number of cells can be amplified stably in a short time by using a sufficient amount of current.

However, since the level is very high relative to the target level of the core voltage, it takes relatively long time to return to the target level of the core voltage. That is, even after the overdriving operation period, there is a problem that the core voltage does not return to the target level immediately.

Therefore, after the overdriving operation period, the level of the core voltage VCORE stage is rapidly increased by rapidly discharging the level of the core voltage VCORE stage which is a high level due to the overdriving operation. The discharge driving method to achieve the target level has been adopted.

1 is a block diagram showing the configuration of a semiconductor memory device employing a discharge driving method according to the prior art.

Referring to FIG. 1, a semiconductor memory device employing a discharge driving method according to the related art includes a plurality of banks BANK1, BANK2, BANK3, and BANK4 for performing a predetermined operation by receiving a core voltage VCORE. Multiple overdriving for controlling the overdriving operation of each bank BANK1, BANK2, BANK3, BANK4 in response to the active signals ACT1, ACT2, ACT3, ACT4 corresponding to the banks BANK1, BANK2, BANK3, BANK4. It is allocated for each of the banks BANK1, BANK2, BANK3, and BANK4 to generate the overdriving pulse generator 190 for generating pulses OVER_PUL1, OVER_PUL2, OVER_PUL3, and OVER_PUL4, and a plurality of overdriving pulses OVER_PUL1, OVER_PUL2, and OVER_PUL3, When one of the pulses OVER_PUL1 or OVER_PUL2 or OVER_PUL3 or OVER_PUL4 is activated, a plurality of discharge voltage detectors 100A and 100B for detecting the level of the core voltage VCORE stage based on the first target level. , 100C, 100D, and each bank (BANK1, BA) NK2, BANK3, and BANK4 are allocated to the core voltages VCORE in response to the respective discharge control signals DISCH_CON1, DISCH_CON2, DISCH_CON3, and DISCH_CON4, which are output from the respective discharge voltage detection units 100A, 100B, 100C, and 100D. A plurality of discharge driving units 110A, 110B, 110C, and 110D for discharging the stages are allocated to each of the banks BANK1, BANK2, BANK3, and BANK4, and correspond to a plurality of banks BANK1, BANK2, BANK3, and BANK4. When one of the active signals ACT1, ACT2, ACT3, and ACT4 is activated, the plurality of charging voltage detection units 130A for detecting the level of the core voltage VCORE terminal based on the second target level 130B, 130C, and 130D and the respective banks BANK1, BANK2, BANK3, and BANK4, and are each charged control signal CH_CON1 and CH_CON2 that are output from the respective charge voltage detectors 130A, 130B, 130C, and 130D. A plurality of charge driving units 140A and 140 for charge driving the core voltage VCORE stage in response to CH_CON3 and CH_CON4 B, 140C, 140D).

In addition, the semiconductor memory device adopting the discharge driving method according to the related art activates or deactivates each of the active signals ACT1, ACT2, ACT3, and ACT4 in response to the operation of each of the banks BANK1, BANK2, BANK3, and BANK4. The reference voltage VREF corresponding to the first target level is supplied to the active signal generator 180 and the plurality of discharge voltage detectors 100A, 100B, 100C, and 100D for generation, and the plurality of charge voltage detectors A reference voltage generator 120 is further provided to supply the reference voltage VREF corresponding to the second target level to the 130A, 130B, 130C, and 130D.

In this case, the reference voltage VREF corresponding to the first target level output from the reference voltage generator 120 and the reference voltage VREF corresponding to the second target level are illustrated as being equal to each other. It means that the level and the second target level may be the same or different. For example, when the first target level and the second target level are different from each other, the plurality of discharge voltage detectors 100A, 100B, 100C, and 100D control the plurality of discharge drivers 110A, 110B, 110C, and 110D. The voltage level of the reference voltage VREF corresponding to the first target level used controls the plurality of charge driving units 140A, 140B, 140C, and 140D in the plurality of charging voltage detection units 130A, 130B, 130C, and 130D. The level becomes higher than the voltage level of the reference voltage VREF corresponding to the second target level to be used. That is, the reference voltage generator 120 uses one reference voltage commonly used by the plurality of discharge voltage detectors 100A, 100B, 100C, and 100D and the plurality of charge voltage detectors 130A, 130B, 130C, and 130D. Only VREF may be generated, and a plurality of discharge voltage detectors 100A, 100B, 100C, and 100D and a plurality of charge voltage detectors 130A and 130B may be generated by generating a plurality of reference voltages VREF having different levels. , 130C and 130D may use different reference voltages VREF.

Here, the plurality of banks BANK1, BANK2, BANK3, and BANK4 may include a bit line sense amplifier 160A for sensing and amplifying data carried on the bit line, and a power line RTO of the bit line sense amplifier 160A. Is provided with a power supply line driver 170A for driving the core voltage VCORE or the overdriving voltage VDD.

FIG. 2A is a circuit diagram illustrating in detail a plurality of discharge voltage detectors and a plurality of discharge drivers among components of a semiconductor memory device employing the discharge drive method illustrated in FIG. 1.

Referring to FIG. 2A, each of the discharge voltage detectors 100A, 100B, 100C, and 100D among the components of the semiconductor memory device adopting the discharge driving method distributes the level of the core voltage VCORE at a predetermined ratio. Comparing the voltage distribution units 102A, 102B, 102C, and 102D for generating the voltage DIV_VOL with the level of the reference voltage VREF and the division voltage DIV_VOL corresponding to the first target level, but corresponding one-to-one. And a plurality of voltage comparing units 104A, 104B, 104C, and 104D whose operations are controlled on / off in response to a plurality of overdriving pulses OVER_PUL1, OVER_PUL2, OVER_PUL3, and OVER_PUL4 inputted at respective biases.

Here, the voltage dividers 102A, 102B, 102C, and 102D have a first resistor R1 and a second resistor R2 connected in series between the core voltage VCORE terminal and the ground voltage VSS terminal. The division voltage DIV_VOL is output from the connection node DIN of the first resistor R1 and the second resistor R2.

In addition, the plurality of discharge drivers 110A, 110B, 110C, and 110D are each discharge control signals DISCH_CON1 output from the plurality of voltage comparators 104A, 104B, 104C, and 104D received one-to-one through respective gates. And a plurality of NMOS transistors DN1, DN2, DN3, and DN4 for controlling the connection of the drain-source connected core voltage VCORE terminal and the ground voltage VSS terminal in response to DISCH_CON2, DISCH_CON3, and DISCH_CON4. .

FIG. 2B is a detailed view of a plurality of charge voltage detectors and a plurality of charge drivers of components of the semiconductor memory device employing the discharge driving method illustrated in FIG. 1.

Referring to FIG. 2B, each of the charging voltage detection units 130A, 130B, 130C, and 130D of the components of the semiconductor memory device employing the discharge driving method distributes the level of the core voltage VCORE at a predetermined ratio. Compare the voltage distribution units 132A, 132B, 132C, and 132D for generating the voltage DIV_VOL with the level of the reference voltage VREF and the divided voltage DIV_VOL corresponding to the second target level, but corresponding one-to-one. And a plurality of voltage comparison units 134A, 134B, 134C, and 134D whose operations are controlled on / off in response to a plurality of active signals ACT1, ACT2, ACT3, and ACT4 inputted at respective biases.

Here, the voltage distribution units 132A, 132B, 132C, and 132D include a first resistor R1 and a second resistor R2 connected in series between the core voltage VCORE terminal and the ground voltage VSS terminal. The division voltage DIV_VOL is output from the connection node DIN of the first resistor R1 and the second resistor R2.

In addition, the plurality of charge driving units 140A, 140B, 140C, and 140D are each of the charge control signals CH_CON1 output from the plurality of voltage comparators 134A, 134B, 134C, and 134D received one-to-one through respective gates. And a plurality of PMOS transistors DP1, DP2, DP3, DP4 for controlling the connection of the source-drain connected power supply voltage VDD stage and the core voltage VCORE stage in response to CH_CON2, CH_CON3, CH_CON4. .

The operation of the semiconductor memory device employing the discharge driving method according to the prior art based on the above-described configuration is as follows.

First, in a section in which any one of the banks BANK1, BANK2, BANK3, and BANK4 is activated to activate at least one of the plurality of active signals ACT1, ACT2, ACT3, and ACT4, the plurality of charges At least one of the charge voltage detectors 130A, 130B, 130C, or 130D among the charge voltage detectors 130A, 130B, 130C, and 130D operates to detect the level of the core voltage VCORE stage based on the second target level. do.

In this case, when the level of the core voltage VCORE is detected to be lower than the second target level in the detection result of the at least one charging voltage detector 130A or 130B or 130C or 130D, at least one charge driver Increase the level of core voltage (VCORE) level by controlling (140A or 140B or 140C or 140D) to pull up operation.

On the contrary, when the level of the core voltage VCORE level is detected to be higher than the second target level in the detection result of the at least one charging voltage detector 130A or 130B or 130C or 130D, the natural discharge or the plurality of discharges. Due to the operation of the driving units 110A, 110B, 110C, and 110D, the plurality of charge driving units 140A, 140B, 140C, and 140D are pulled up until the level of the core voltage VCORE is lower than the second target level. Control not to.

In addition to the operations of the plurality of charge voltage detectors 130A, 130B, 130C, and 130D, the overdriving pulse generator 190 may include an active signal ACT1 or ACT2 or ACT3 or ACT4, at least one of which is activated. In response, at least one of the overdriving pulses OVER_PUL1 or OVER_PUL2 or OVER_PUL3 or OVER_PUL4 is activated, and accordingly, at least one of the at least one overdriving pulses OVER_PUL1 or OVER_PUL2 or OVER_PUL3 or OVER_PUL4 received. The bank BANK1 or BANK2 or BANK3 or BANK4 performs an overdriving operation. In this manner, as the overdriving operation is performed, the level of the core voltage VCORE stage rapidly rises toward the level of the power supply voltage VDD. As a result, the level of the core voltage VCORE stage increases not only the first target level. It becomes higher than 2nd target level.

In this case, at least one of the overdriving pulses OVER_PUL1 or OVER_PUL2 or OVER_PUL3 or OVER_PUL4 activated in the plurality of discharge voltage detection units 100A, 100B, 100C, and 100D may be input.

However, when at least one discharge voltage detector 100A or 100B or 100C or 100D operates in response to the input at least one overdriving pulse OVER_PUL1 or OVER_PUL2 or OVER_PUL3 or OVER_PUL4, at least one of the at least one The overdriving operation being performed in the bank BANK1 or BANK2 or BANK3 or BANK4 overlaps with the operation. That is, in at least one bank BANK1 or BANK2 or BANK3 or BANK4, the level of the core voltage VOCRE is increased by overdriving operation, but at least one discharge voltage detector 100A or 100B or 100C or 100D), the at least one discharge driver 110A or 110B or 110C or 110D is operated to lower the level of the core voltage VCORE stage, and thus the overdriving operation cannot be performed normally.

Accordingly, the plurality of discharge voltage detectors 100A, 100B, 100C, and 100D operate in response to a pulse which is delayed for a predetermined time by receiving at least one activated overdriving pulse OVER_PUL1 or OVER_PUL2 or OVER_PUL3 or OVER_PUL4. At least one discharge driver 110A or 110B from the time point at which the overdriving operation is performed in the at least one bank BANK1 or BANK2 or BANK3 or BANK4 activated and the plurality of discharge drivers 110A, 110B, 110C, and 110D. or 110C or 110D) is controlled so that the time of operation is different.

That is, when a plurality of overdriving pulses OVER_PUL1, OVER_PUL2, OVER_PUL3, and OVER_PUL4 are inputted, the plurality of pulse delay units 106A, 106B, 106C, and 106D delays them by a predetermined time, thereby delaying the plurality of delay pulses DOVER_PUL1 and DOVER_PUL2. , DOVER_PUL3, DOVER_PUL4) are output and at least one of the plurality of delay pulses (DOVER_PUL1, DOVER_PUL2, DOVER_PUL3, DOVER_PUL4) is activated in response to the detection of the discharge for multiple discharge pulses (DOVER_PUL1 or DOVER_PUL2 or DOVER_PUL3 or DOVER_PUL4). At least one of the discharge voltage detection units 100A or 100B or 100C or 100D among the 100A, 100B, 100C, and 100D is operated to detect the level of the core voltage VCORE stage based on the first target level.

In this way, at least one discharge voltage detector 100A or 100B or 100C or 100D operates to detect the level of the core voltage VCORE terminal based on the first target level. Since the overdriving operation has already been performed in BANK1 or BANK2 or BANK3 or BANK4), the level of the core voltage VCORE stage will be rapidly higher than the first target level. Therefore, the at least one discharge voltage detection unit 100A or 100B or 100C or 100D in operation controls the at least one discharge driver 110A or 110B or 110C or 110D to operate at the level of the core voltage VCORE. Lower it.

Of course, since the power supply voltage VDD is an externally input voltage, when the overdriving operation is performed at a level lower than the target level of the predetermined power supply voltage VDD, a plurality of discharge voltage detectors 100A, 100B, 100C, and 100D are used. By appropriately controlling the operation of each discharge driver 110A, 110B, 110C, 110D, the level of the core voltage VCORE stage is prevented from dropping too much.

As described above, the plurality of charge driving units 140A, 140B, 140C, and 140D and the plurality of discharge driving units 110A, 110B, 110C, and 110D correspond to one-to-one charging voltage detection units 130A, 130B, 130C, 130D) and a plurality of discharge voltage detectors 100A, 100B, 100C, and 100D control their operations on and off, and a plurality of charge voltage detectors 130A, 130B, 130C, and 130D. The plurality of discharge voltage detectors 100A, 100B, 100C, and 100D control the operation according to the level change of the core voltage VCORE stage, thereby controlling the core voltage VCORE stage to always maintain a stable target level. Do it.

Therefore, the aforementioned plurality of charge drivers 140A, 140B, 140C, and 140D, a plurality of discharge drivers 110A, 110B, 110C, and 110D, a plurality of charge voltage detectors 130A, 130B, 130C, and 130D, and a plurality of charge drivers As illustrated in FIG. 1, the discharge voltage detectors 100A, 100B, 100C, and 100D correspond to the banks BANK1, BANK2, BANK3, and BANK4 in one-to-one correspondence.

However, a plurality of charge drivers 140A, 140B, 140C, 140D, a plurality of discharge drivers 110A, 110B, 110C, 110D, and a plurality of charge voltage detectors 130A, 130B, 130C, 130D and a plurality of rooms The dedicated voltage detectors 100A, 100B, 100C, and 100D, and the banks BANK1, BANK2, BANK3, and BANK4 are all connected to one core voltage VCORE terminal as shown in FIG.

That is, the plurality of charge drivers 140A, 140B, 140C, 140D, the plurality of discharge drivers 110A, 110B, 110C, 110D, the plurality of charge voltage detectors 130A, 130B, 130C, 130D, and the plurality of discharges The voltage detectors 100A, 100B, 100C, and 100D are connected to core voltages VCORE that are relatively close to the banks BANK1, BANK2, BANK3, and BANK4 corresponding to one-to-one, respectively.

For example, among the banks BANK1, BANK2, BANK3, and BANK4 of the core voltage VORE terminal area connecting all of the banks BANK1, BANK2, BANK3, and BANK4, the banks BANK1 are relatively close to the first bank BANK1. The first charge driver 140A, the first discharge driver 110A, the first charge voltage detector 130A and the first discharge voltage detector 100A are connected to a region near the core voltage VCORE, and thus the first bank. When BANK1 operates, the operation is determined accordingly.

However, in the above configuration, although the core voltage VCORE is connected to all the banks BANK1, BANK2, BANK3, and BANK4 simultaneously, the banks BANK1, BANK2, BANK3, and BANK4 are connected. In the case of an auto REFresh (AREF) operation that must be operated at the same time, a plurality of charge voltage detectors 130A, 130B, 130C, and 130D and a plurality of discharge voltage detectors 100A, 100B, 100C, and 100D are used. All of them operate at the same time, causing a problem of detecting the same core voltage VCORE.

This causes a problem that a current is consumed which does not actually need to be used.

In addition, the plurality of charging voltage detection units 130A, 130B, 130C, and 130D each include a comparator for comparing whether the level of the core voltage VCORE stage is lower than the second target level. A resistor is also included to distribute the level of the core voltage VCORE to increase efficiency.

Similarly, the plurality of discharge voltage detection units 100A, 100B, 100C, and 100D each include a comparator for comparing whether the core voltage VCORE stage has a level higher than the first target level. A resistor is also included to distribute the level of the core voltage VCORE to increase.

In this case, each of the comparator and the resistor element occupies a relatively large area in the semiconductor memory device. Therefore, each of the charge voltage detectors 130A, 130B, 130C, and 130D including the comparator and the resistance element and the discharge voltage detectors 100A, 100B, 100C, and 100D, respectively, have a relative area of the semiconductor memory device. In this case, a problem arises in that the total area of the semiconductor memory device is increased.

The present invention has been proposed to solve the above problems of the prior art, and provides a charge driving circuit and a discharge driving circuit which occupy a relatively small area without a change in driving force in a semiconductor memory device having a plurality of banks. There is this.

According to an aspect of the present invention for solving the above problems, a plurality of banks; Discharge pulse generation means for generating a discharge pulse in which an activation period is determined in response to an active signal and an auto refresh signal corresponding to the plurality of banks; Discharge common voltage detecting means for detecting a voltage level of an internal voltage terminal based on a first target level in response to the discharge pulse; And discharge common driving means for discharging the internal voltage terminal in response to an output signal of the discharge common voltage detecting means.

In addition, according to another aspect of the present invention for solving the above problems, the bit line sensing amplifier for sensing and amplifying data carried on the bit line, and the power line of the bit line sensing amplifier is applied through the core voltage terminal A plurality of banks each having a power line driver for driving at a core voltage or an overdriving voltage; Overdriving pulse generating means for generating a plurality of overdriving pulses for controlling the overdriving operation of each bank in response to an active signal corresponding to each bank; Discharge pulse generation means for generating a discharge pulse in which an activation period is determined in response to the plurality of overdriving pulses and the auto refresh signal; Discharge common voltage detection means for detecting the level of the core voltage terminal based on a first target level in response to the discharge pulse; And discharge common driving means for discharging the core voltage terminal in response to an output signal of the discharge common voltage detecting means.

According to the present invention, a plurality of banks share the voltage detection circuit for detecting the level of the internal voltage terminal and the voltage terminal driving circuit for driving the internal voltage terminal, thereby preventing the area of the semiconductor memory device from increasing. There is.

In addition, even in an auto refresh (AREF) operation in which a plurality of banks are activated at the same time, the current is prevented from being wasted by not detecting the level of the internal voltage terminal in duplicate.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be configured in various different forms, only this embodiment is intended to complete the disclosure of the present invention and to those skilled in the art the scope of the present invention It is provided to inform you completely.

Example 1

3 is a block diagram showing the configuration of a semiconductor memory device employing a discharge driving method according to a first embodiment of the present invention.

Referring to FIG. 3, the semiconductor memory device adopting the discharge driving method according to the first embodiment of the present invention may include bit line sensing amplifiers 360A, 360B, 360C, and 360D for sensing and amplifying data carried on the bit lines. Power line driver for driving the power line RTO of the bit line detection amplifiers 360A, 360B, 360C, and 360D to the core voltage VCORE or the overdriving voltage VDD applied through the core voltage VCORE. A plurality of banks BANK1, BANK2, BANK3, BANK4 having 370A, 370B, 370C, and 370D, respectively, and active signals ACT1, ACT2, ACT3, corresponding to the banks BANK1, BANK2, BANK3, BANK4, respectively. An overdriving pulse generator 390 for generating a plurality of overdriving pulses OVER_PUL1, OVER_PUL2, OVER_PUL3, and OVER_PUL4 for controlling the overdriving operation of each bank BANK1, BANK2, BANK3, and BANK4 in response to ACT4); , Multiple overdriving pulses (OVER_PUL1, OVER_PUL2, OVER_PUL3, OVER_PUL4) A discharge pulse generator 350 for generating a discharge pulse DISCHARGE_PUL in which an activation period is determined in response to the auto refresh signal AREF_SIG, and a core voltage (C) based on the first target level in response to the discharge pulse DISCHARGE_PUL. Discharging the core voltage (VCORE) terminal in response to the discharge common voltage detector 300 for detecting the level of the VCORE stage and the discharge control signal DISCH_CON output from the discharge common voltage detector 300. And a common driver 310 for discharge.

In addition, a plurality of charging voltage detection units 330A, 330B, 330C, for detecting the level of the core voltage VCORE stage based on the second target level in response to each of the active signals ACT1, ACT2, ACT3, and ACT4. 330D) and charge control signals CON_CH1, CON_CH2, CON_CH3, and CON_CH4 that are allocated to each of the banks BANK1, BANK2, BANK3, and BANK4, and are output from the respective charge voltage detectors 330A, 330B, 330C, and 330D. A plurality of charge driving units 340A, 340B, 340C, and 340D are further provided to charge-drive the core voltage VCORE stage in response to the respective active signals ACT1, ACT2, ACT3, and ACT4.

In addition, the active signal generator 380 for generating or activating each of the active signals ACT1, ACT2, ACT3, and ACT4 in response to the operation of each of the banks BANK1, BANK2, BANK3, and BANK4, and for discharging. The reference voltage VREF corresponding to the first target level is supplied to the common voltage detector 300, and the reference voltages VREF corresponding to the second target level are supplied to the plurality of charging voltage detectors 330A, 330B, 330C, and 330D. It is further provided with a reference voltage generator 320 for supplying.

In this case, the reference voltage VREF corresponding to the first target level output from the reference voltage generator 320 and the reference voltage VREF corresponding to the second target level are shown to be the same. It means that the level and the second target level may be the same or different. For example, when the first target level and the second target level are different from each other, the reference voltage VREF corresponding to the first target level used to control the discharge common driver 310 in the discharge common voltage detector 300. Reference voltage VREF corresponding to a second target level used to control the plurality of charging driving units 340A, 340B, 340C, and 340D in the plurality of charging voltage detection units 330A, 330B, 330C, and 330D. Can be higher than the voltage level. That is, the reference voltage generator 320 may generate only one reference voltage VREF commonly used by the discharge common voltage detector 300 and the plurality of charge voltage detectors 330A, 330B, 330C, and 330D. And generate a plurality of reference voltages VREF having different levels so that the discharge common voltage detector 300 and the charge voltage detectors 330A, 330B, 330C, and 330D are different from each other. You can also use

FIG. 4 is a circuit diagram illustrating in detail a common voltage detecting unit for discharging and a common driving unit for discharging among components of a semiconductor memory device employing the discharge driving method according to the first embodiment of the present invention illustrated in FIG. 3.

Referring to FIG. 4, the common voltage detector 300 for discharging the components of the semiconductor memory device adopting the discharge driving method according to the first embodiment of the present invention distributes the level of the core voltage VCORE stage at a predetermined ratio. The voltage divider 302 for generating the divided voltage DIV_VOL is compared with the level of the reference voltage VREF and the divided voltage DIV_VOL corresponding to the first target level, but the bias pulse discharge pulse DISCHARGE_PUL is input. And a voltage comparing section 304 whose operation is controlled ON / OFF.

The voltage divider 302 of the components of the discharge common voltage detector 300 includes the first resistor R1 and the second low connected in series between the core voltage VCORE terminal and the ground voltage VSS terminal. And a division voltage DIV_VOL is output from the connection node DIN of the first resistor R1 and the second resistor R2.

Among the components of the discharge common voltage detector 300, the voltage comparator 304 includes a driving node ZN connected to a drain-source connected to the driving node ZN corresponding to the level of the divided voltage DIV_VOL applied through the gate. The first NMOS transistor N1 for controlling the magnitude of the current flowing between the COMNs and the drain-source connected output node corresponding to the level of the reference voltage VERF corresponding to the first target level applied through the gate. The second NMOS transistor N2 for controlling the magnitude of the current flowing between the OUTN and the common node COMN, between the power supply voltage VDD terminal, the driving node ZN, the power supply voltage VDD terminal, and the output node OUTN. First and second PMOS transistors P1 and P2 connected to each other in the form of a current mirror to control the current flowing through the driving node ZN and the output node OUTN to be the same, and applied through a gate. In response to the received discharge pulse (DISCHARGE_PUL) And a third NMOS transistor N3 for controlling the magnitude of the current flowing between the drain-source connected common node COMN and the ground voltage VSS terminal.

The common driver 310 for discharge among the components of the semiconductor memory device adopting the discharge driving method according to the first embodiment of the present invention is connected to the discharge control signal DISCH_CON output from the discharge common voltage detector 300. In response, a discharge driver 314 for discharge driving the core voltage VCORE stage with a predetermined driving force is provided.

At this time, the discharge driver 314, NMOS for controlling the magnitude of the current flowing between the drain-source connected core voltage (VCORE) terminal and the ground voltage (VSS) terminal in response to the discharge control signal (DISCH_CON) applied to the gate The transistor DN is provided.

FIG. 5 is a circuit diagram illustrating in detail a discharge pulse generator among components of a semiconductor memory device employing the discharge driving method according to the first embodiment of the present invention shown in FIG. 3.

Referring to FIG. 5, the discharge pulse generator 350 among the components of the semiconductor memory device adopting the discharge driving method according to the first embodiment of the present invention may include a plurality of over driver pulses OVER_PUL1, OVER_PUL2, OVER_PUL3, and OVER_PUL4. In response to the pulse section determining section 352 for determining the pulse section of the enable pulse ENABLE_PUL, a delay section 354 for delaying the enable pulse ENABLE_PUL by a predetermined time t0, and a delay section. The pulse section variation unit 356 for generating a plurality of section variation pulses (VA_DENABLE_PUL1, VA_DENABLE_PUL2, VA_DENABLE_PUL3, VA_DENABLE_PUL4) by varying the pulse section length of the pulse (DENABLE_PUL) output from the step 354 by a predetermined number of times. In response to the refresh signal AREF_SIG, the pulse section with the longest pulse section (VA_DENABLE_PUL4) and the pulse section in the plurality of section change pulses (VA_DENABLE_PUL1, VA_DENABLE_PUL2, VA_DENABLE_PUL3, VA_DENABLE_PUL4) And a discharge pulse output section 358 for outputting either one of the pulse as the discharge pulse (DISCHARGE_PUL) of the relatively short pulse (VA_DENABLE_PUL1).

Here, the pulse section determining unit 352 receives all of the plurality of over driver pulses OVER_PUL1, OVER_PUL2, OVER_PUL3, and OVER_PUL4, and outputs the signals of the NOA gate NOR and the NOA gate NOR for negative logic sum and output. An inverter INV for inverting and outputting as an enable pulse ENABLE_PUL is provided.

In addition, the pulse section changing section 356 is connected in series to sequentially vary the pulse section length of the pulse DENABLE_PUL output from the delay section 354 by a predetermined time, respectively, and a plurality of section varying pulses VA_DENABLE_PUL1 and VA_DENABLE_PUL2. And a plurality of section length varying units 356A, 356B, 356C, and 356D for outputting VA_DENABLE_PUL3 and VA_DENABLE_PUL4.

Here, each of the section length changing units 356A, 356B, 356C, and 356D is a time when the pulses (DENABLE_PUL, VA_DENABLE_PUL1, VA_DENABLE_PUL1, VA3DEN) applied to the respective input terminals PUL_IN_ND1, PUL_IN_ND2, PUL_IN_ND4 are scheduled. A number of delay elements DELAY1, DELAY2, DELAY3, and DELAY4, and pulses DENABLE_PUL, VA_DENABLE_PUL1, VA_DENABLE_PUL2, and VA_DENABLE respectively applied to the respective input terminals PUL_IN_ND1, PUL_IN_ND2, PUL_IN_ND4 Inverts the output pulses of a number of NOR gates (NOR1, NOR2, NOR3, NOR4), and each of the NORG gates (NOR1, NOR2, NOR3, NOR4) for negative logical sum of pulses output from DELAY1, DELAY2, DELAY3, and DELAY4 And a plurality of inverters (INV1, INV2, INV3, INV4) for outputting as a plurality of section variable pulses (VA_DENABLE_PUL1, VA_DENABLE_PUL2, VA_DENABLE_PUL3, VA_DENABLE_PUL4).

The discharge pulse output unit 358 discharges the pulse VA_DENABLE_PUL4 having the longest pulse period among the plurality of section variation pulses VA_DENABLE_PUL1, VA_DENABLE_PUL2, VA_DENABLE_PUL3, and VA_DENABLE_PUL4 in response to the auto refresh signal AREF_SIG. The pulse section of the first pulse switch 358A for switching the output as (DISCHARGE_PUL) and the plurality of section change pulses VA_DENABLE_PUL1, VA_DENABLE_PUL2, VA_DENABLE_PUL3, VA_DENABLE_PUL4 are relatively shortest in response to the auto refresh signal AREF_SIG. A second pulse switch 358B is provided for switching the output of the pulse VA_DENABLE_PUL1 as the discharge pulse DISCHARGE_PUL.

The operation of the semiconductor memory device adopting the discharge driving method according to the first embodiment of the present invention will be described below based on the above-described configuration.

First, as described in the related art, any one bank among the plurality of banks BANK1, BANK2, BANK3, and BANK4 is activated to at least one pulse OVER_PUL1 among the plurality of over driver pulses OVER_PUL1, OVER_PUL2, OVER_PUL3, and OVER_PUL4. or OVER_PUL2 or OVER_PUL3 or OVER_PUL4) is activated, at least one of the plurality of charging voltage detection unit (330A, 330B, 330C, 330D) of the charging voltage detection unit (330A or 330B or 330C or 330D) is operated The level of the voltage VCORE terminal is detected based on the second target level.

In this case, when the level of the core voltage VCORE is detected to be lower than the second target level in the detection result of the at least one charging voltage detector 330A or 330B or 330C or 330D, at least one charge driver 340A, 340B, 340C, and 340D operate to pull up to increase the level of the core voltage VCORE stage.

On the contrary, when the level of the core voltage VCORE is detected to be higher than the second target level in the detection result of the at least one charging voltage detector 330A or 330B or 330C or 330D, the common discharge or discharge is common. Due to the operation of the driving unit 310, the plurality of charging driving units 340A, 340B, 340C, and 340D do not pull up until the level of the core voltage VCORE becomes lower than the second target level.

In addition to the operations of the plurality of charging voltage detectors 330A, 330B, 330C, and 330D, the overdriving pulse generator 390 may include at least one of the over driver pulses OVER_PUL1 or OVER_PUL2 or OVER_PUL3 or OVER_PUL4 that are activated. At least one over-driving pulse (OVER_PUL1 or OVER_PUL2 or OVER_PUL3 or OVER_PUL4) is activated, and accordingly, at least one of the activated over-driving pulses (OVER_PUL1 or OVER_PUL2 or OVER_PUL3 or OVER_PUL4) is received. At least one bank BANK1 or BANK2 or BANK3 or BANK4 performs an overdriving operation. In this manner, as the overdriving operation is performed, the level of the core voltage VCORE stage rapidly rises toward the level of the power supply voltage VDD. As a result, the level of the core voltage VCORE stage increases not only the first target level. It becomes higher than 2nd target level.

In addition, unlike the conventional art, the discharge common voltage detector 300 operates only in an activation section of the discharge pulse DISCHARGE_PUL.

At this time, the plurality of discharge voltage detectors 100A, 100B, 100C, and 100D according to the prior art delay the overdriving pulse OVER_PUL1 or OVER_PUL2 or OVER_PUL3 or OVER_PUL4 by a predetermined time period (DOVER_PUL1 or DOVER_PUL2 or DOVER_PUL3 or DOVER_PUL4). In response to the operation, the time point at which the activation period of the discharge pulse DISCHARGE_PUL starts is controlled to be the same as the time point at which the overdriving pulse OVER_PUL1 or OVER_PUL2 or OVER_PUL3 or OVER_PUL4 is delayed by a predetermined time.

That is, as in the prior art, the timing at which the overdriving operation is performed and the timing at which the discharge common voltage detector 300 operates are controlled to be different from each other.

Specifically, when a plurality of over-driving pulses OVER_PUL1, OVER_PUL2, OVER_PUL3, and OVER_PUL4 are input to the discharge pulse generator 350, the pulse section determiner 352 generates the enable pulse ENABLE_PUL in response thereto. The delay unit 354 delays the enable pulse ENABLE_PUL by a predetermined time t0 and outputs it as a delayed enable pulse DENABLE_PUL.

In this way, the enable section of the discharge pulse (DISCHARGE_PUL) is started from the start point of the activation section of the overdriving pulse OVER_PUL1 or OVER_PUL2 or OVER_PUL3 or OVER_PUL4 by delaying the enable pulse ENABLE_PUL by a predetermined time t0. The point in time is controlled to be later.

In addition, in the drawing, the pulse section determiner 352 of the components of the discharge pulse generator 350 generates the enable pulse ENABLE_PUL first, and then the delay unit 354 generates the enable pulse ENABLE_PUL. The delayed enable pulse DENABLE_PUL is output by delaying the predetermined time t0. This portion may be changed.

That is, the delay unit 354 delays the plurality of overdriving pulses OVER_PUL1, OVER_PUL2, OVER_PUL3, and OVER_PUL4 by a predetermined time t0, and then the pulse section determiner 352 performs the enable pulse DENABLE_PUL. Even if the operation to generate the result is the same.

For reference, the enable pulse ENABLE_PUL generated by the pulse interval determiner 352 among the components of the discharge pulse generator 350 may be any one of a plurality of overdrive pulses OVER_PUL1, OVER_PUL2, OVER_PUL3, and OVER_PUL4. The signal is deactivated when the overdrive pulses OVER_PUL1, OVER_PUL2, OVER_PUL3, and OVER_PUL4 are all deactivated, and the plurality of overdrive pulses OVER_PUL1, OVER_PUL2, OVER_PUL3 and OVER_PUL4 are deactivated. The enable pulse (ENABLE_PUL) is the same activation interval as each of the overdriving pulses (OVER_PUL1, OVER_PUL2, OVER_PUL3, OVER_PUL4), regardless of whether one pulse is active or all pulses. Becomes a signal having

That is, when at least one of the plurality of overdriving pulses OVER_PUL1, OVER_PUL2, OVER_PUL3, and OVER_PUL4 has an activation section, an enable pulse ENABLE_PUL having the same activation section is generated.

As such, when the enable pulse DENABLE_PUL delayed by a predetermined time t0 from the time of activation of the plurality of overdriving pulses OVER_PUL1, OVER_PUL2, OVER_PUL3, and OVER_PUL4 is activated, the components of the discharge pulse generator 350 in response thereto are activated. The pulse section variation unit 356 operates to be activated at the same time as the activation time of the delayed enable pulse DENABLE_PUL, but the variance pulses VA_DENABLE_PUL1, VA_DENABLE_PUL2, VA_DENABLE_PUL3, and VA_DENABLE_PUL4 having different lengths of activation sections are operated. Will be created.

At this time, the length of the activation section of each of the section fluctuation pulses VA_DENABLE_PUL1, VA_DENABLE_PUL2, VA_DENABLE_PUL3, and VA_DENABLE_PUL4 depends on the delay amount of the plurality of delay elements DELAY1, DELAY2, DELAY3, and DELAY4 provided in the pulse section variation unit 356. Is determined.

For example, if each of the delay devices DELAY1, DELAY2, DELAY3, and DELAY4 has a delay amount of 't1', and the activation interval length of the delayed enable pulse DENABLE_PUL is 't0', The first section variable pulse (VA_DENABLE_PUL1) among the section variable pulses (VA_DENABLE_PUL1, VA_DENABLE_PUL2, VA_DENABLE_PUL3, VA_DENABLE_PUL4) has the length of the activation section as '(2 * t0)-t1', and the second section variable pulse (VA_DEN) Is. '(4 * t0)-(3 * t1)' length of the activation interval, and the third interval change pulse (VA_DENABLE_PUL3). '(8 * t0)-(7 * t1)' has the length of activation section, and the fourth section variation pulse (VA_DENABLE_PUL4) is. It has an activation interval length of '(16 * t0)-(15 * t1)'.

At this time, since there is a relationship of 't1 ≤ t0', the first section variable pulse VA_DENABLE_PUL1 has a relatively shortest activation section length, and the fourth section variable pulse VA_DENABLE_PUL4 has a relatively long activation section length. Will have

In this way, when a plurality of interval variation pulses VA_DENABLE_PUL1, VA_DENABLE_PUL2, VA_DENABLE_PUL3, and VA_DENABLE_PUL4 are generated, the discharge pulse output unit 356 may have different directions according to the logic level of the auto refresh signal AREF_SIG. It works.

For example, when the auto refresh signal AREF_SIG is activated at logic 'high' and the semiconductor memory device operates in the auto refresh mode, all banks BANK1, BANK2, BANK3, and BANK4 included in the semiconductor memory device are operated. The plurality of charge driving units 340A, 340B, 340C, and 340D and the plurality of overdriving units 372A, 372B, 372C, and 372D are all operating at the same time. Therefore, since the level of the core voltage VCORE stage can be completely stabilized only when the operation time of the discharge common driving unit 310 is sufficiently ensured, the discharge pulse output unit 356 has a plurality of interval variation pulses VA_DENABLE_PUL1, VA_DENABLE_PUL2, The fourth section variable pulse VA_DENABLE_PUL4 having the longest activation section length among the VA_DENABLE_PUL3 and VA_DENABLE_PUL4 is output as the discharge pulse DISCHARGE_PUL.

Of course, when the auto refresh signal AREF_SIG is activated with logic 'low' to operate the semiconductor memory device in the normal mode, the banks BANK1, BANK2, BANK3, and BANK4 included in the semiconductor memory device may operate. Since only one bank is in operation, only one of the plurality of charge driving units 340A, 340B, 340C, and 340D operates and only one of the plurality of over-driving units 372A, 372B, 372C, and 372D is over. Only the driving unit is in operation. Therefore, even if the operation time of the discharge common driver 310 is normally maintained, the level of the core voltage VCORE stage can be sufficiently stabilized, so that the discharge pulse output unit 356 has a plurality of interval variation pulses VA_DENABLE_PUL1, VA_DENABLE_PUL2, Among the VA_DENABLE_PUL3 and VA_DENABLE_PUL4, the first section variation pulse VA_DENABLE_PUL1 having the relatively shortest activation section length is output as the discharge pulse DISCHARGE_PUL.

As such, the reason for generating a plurality of interval variation pulses VA_DENABLE_PUL1, VA_DENABLE_PUL2, VA_DENABLE_PUL3, and VA_DENABLE_PUL4 having different lengths of activation intervals is based on one of a plurality of interval variation pulses (VA_DENABLE_PUL1, VA_DENABLE_PUL2, and VA_DENABLE_PUL_PUL3). If output as the discharge pulse (DISCHARGE_PUL), the length of the activation interval of the discharge pulse (DISCHARGE_PUL) can be freely adjusted according to the user's selection.

Of course, in the first embodiment of the present invention, in response to the auto refresh signal AREF_SIG through the operation of the discharge pulse output unit 356, the relatively longest of the plurality of interval variation pulses VA_DENABLE_PUL1, VA_DENABLE_PUL2, VA_DENABLE_PUL3, and VA_DENABLE_PUL4. A pulse of any one of the fourth section variable pulse VA_DENABLE_PUL4 having the activation section length and the first section variable pulse VA_DENABLE_PUL1 having the shortest activation section length is output as the discharge pulse DISCHARGE_PUL, which is only an embodiment. In practice, the operation of the discharge pulse output unit 356 may be changed by the user's needs.

As described above, in the first embodiment of the present invention, a plurality of banks BANK1, BANK2, BANK3, and BANK4 share a common voltage detector 300 for discharge and a common driver 310 for discharge. or the discharge common voltage detection unit 300 having the activation of BANK3 or BANK4 is activated to detect the potential level of the core voltage VOCRE stage, and accordingly the discharge common driver 310 operates to operate the core voltage VOCRE stage. As the banks BANK1, BANK2, BANK3, and BANK4 operate in the related art in terms of stabilizing the potential level of the plurality of discharge voltage detectors 100A, 100B, 100C, and 100D and the discharge drivers 110A, Compared to the selective operation of 110B, 110C, and 110D, it can be regarded as an advanced operation.

For example, in the related art, when the first bank BANK1 is activated to perform an overdriving operation, only the first discharge voltage detector 100A and the first discharge driver 110A operate, and the remaining second to fourth rooms are operated. The dedicated voltage detectors 100B, 100C, and 100D and the second to fourth discharge drivers 110B, 110C, and 100D do not operate. However, in the first embodiment of the present invention, the fourth bank is activated regardless of whether the first bank BANK1 is activated. When only one bank is activated, even if BANK4 is activated, the discharge common voltage detector 300 and the discharge common driver 310 operate.

Therefore, in the prior art, there are components that must occupy a certain area in the semiconductor memory device even though they are not actually used in the prior art, whereas in the first embodiment of the present invention, a certain area in the semiconductor memory device is not actually used. There may not be any component to occupy.

In this case, each of the discharge voltage detectors 100A, 100B, 100C, and 100D according to the related art shown in FIG. 2 and the discharge common voltage detector 300 according to the first embodiment of the present invention shown in FIG. It can be seen that they have similar circuit configurations.

Accordingly, the area of the semiconductor memory device in which the discharge common voltage detector 300 according to the first embodiment of the present invention occupies relatively more than the plurality of discharge voltage detectors 100A, 100B, 100C, and 100D according to the related art. It must be small.

As described above, when the first embodiment of the present invention is applied to a semiconductor device employing a discharge driving method, the discharge common voltage detector 300 and the discharge common driver 310 occupy a relatively large area in the semiconductor memory device. By using a plurality of banks BANK1, BANK2, BANK3, and BANK4 shared, the area of the semiconductor memory device can be prevented from increasing.

In addition, even in an auto refresh operation in which a plurality of banks BANK1, BANK2, BANK3, and BANK4 are simultaneously activated, current is prevented from being wasted by not detecting the level of the core voltage VCORE level in duplicate.

Example 2

6 is a block diagram showing the configuration of a semiconductor memory device employing a discharge driving method according to a second embodiment of the present invention.

Referring to FIG. 6, a semiconductor memory device adopting a discharge driving method according to a second embodiment of the present invention includes a plurality of banks BANK1, BANK2, BANK3, and BANK4 for performing a predetermined operation by receiving an internal voltage; Multiple overs for controlling the overdriving operation of each bank BANK1, BANK2, BANK3, BANK4 in response to the active signals ACT1, ACT2, ACT3, ACT4 corresponding to each bank BANK1, BANK2, BANK3, BANK4. An overdriving pulse generator 690 that generates driving pulses OVER_PUL1, OVER_PUL2, OVER_PUL3, and OVER_PUL4, and a plurality of overdriving pulses (OVER_PUL1, OVER_PUL2, OVER_PUL3, OVER_PUL4) and an auto refresh signal (AREF_SIG). The discharge pulse generator 650 for generating the determined discharge pulse DISCHARGE_PUL and the discharge voltage for detecting the level of the internal voltage VINT stage based on the first target level in response to the discharge pulse DISCHARGE_PUL. Common voltage And a chulbu 600, and a common discharge voltage detection unit 600 for discharging the common driver 610 for discharge in response to a control signal (DISCH_CON) to drive the discharging internal voltage (VINT) which is output from stage.

Also, a plurality of charging voltage detectors 630A, 630B, 630C, for detecting the level of the internal voltage VINT stage based on the second target level in response to each of the active signals ACT1, ACT2, ACT3, and ACT4. 630D) and the charge control signals CON_CH1, CON_CH2, CON_CH3, and CON_CH4 that are allocated to each bank BANK1, BANK2, BANK3, and BANK4, and are output from the respective charge voltage detectors 630A, 630B, 630C, and 630D. The apparatus further includes a plurality of charge driving units 640A, 640B, 640C, and 640D for charge driving the internal voltage VINT stage in response to each of the active signals ACT1, ACT2, ACT3, and ACT4.

In addition, the active signal generator 680 for generating or activating each of the active signals ACT1, ACT2, ACT3, and ACT4 in response to the operation of each of the banks BANK1, BANK2, BANK3, and BANK4, and for discharge. The reference voltage VREF corresponding to the first target level is supplied to the common voltage detector 600, and the reference voltages VREF corresponding to the second target level are supplied to the plurality of charging voltage detectors 630A, 630B, 630C, and 630D. It is further provided with a reference voltage generator 620 for supplying.

In this case, the reference voltage VREF corresponding to the first target level output from the reference voltage generator 620 and the reference voltage VREF corresponding to the second target level are shown to be the same, which is the first target. It means that the level and the second target level may be the same or different. For example, when the first target level and the second target level are different from each other, the reference voltage VREF corresponding to the first target level used to control the discharge common driver 610 in the discharge common voltage detector 600. Reference voltage (VREF) corresponding to a second target level used to control the plurality of charge driving units (640A, 640B, 640C, 640D) in the plurality of charging voltage detection units (630A, 630B, 630C, 630D). Can be higher than the voltage level. That is, the reference voltage generator 620 may generate only one reference voltage VREF commonly used by the discharge common voltage detector 600 and the plurality of charge voltage detectors 630A, 630B, 630C, and 630D. And generate a plurality of reference voltages VREF having different levels, so that the discharge common voltage detector 600 and the charge voltage detectors 630A, 630B, 630C, and 630D have different reference voltages VREF. You can also use

Specifically, comparing the configuration of the first embodiment of the present invention shown in FIG. 3 and the second embodiment of the present invention shown in FIG. 6, in the first embodiment of the present invention, only the core voltage VCORE stage The common voltage detector 300 for discharge, the common driver 310 for discharge, the plurality of charge voltage detectors 330A, 330B, 330C, and 330D and the plurality of charge drivers 340A, 340B, 340C, and 340D In the second embodiment of the present invention, the discharge common voltage detector 600 detects all the internal voltages VINT, which are used to perform operations in the semiconductor memory device, including the internal voltages VINT. And a discharge common driver 610, a plurality of charge voltage detectors 630A, 630B, 630C, and 630D, and a plurality of charge drivers 640A, 640B, 640C, and 640D.

Therefore, the discharge common voltage detector 600 and the discharge common driver 610 and the plurality of charge voltage detectors 630A, 630B, 630C, and 630D according to the second embodiment of the present invention shown in FIG. The configuration and operation of the charge driving unit 640A, 640B, 640C, and 640D of the discharge common voltage detector 300 and the discharge common driver 310 according to the first embodiment of the present invention shown in FIG. The configuration and operation of the charge voltage detectors 330A, 330B, 330C, and 330D and the plurality of charge drivers 340A, 340B, 340C, and 340D are similar, and thus will not be described herein.

For reference, the aforementioned internal voltages are all internal voltages used to perform a predetermined operation in a semiconductor memory device, and include a boosted voltage VPP, a back bias voltage VBB, a core voltage VCORE, and a bit line precharge voltage VBLP. ), And the like.

As described above, when the second embodiment of the present invention is applied to a semiconductor device adopting a discharge driving method, the discharge common voltage detector 600 and the discharge common driver 610 occupy a relatively large area in the semiconductor memory device. By using a plurality of banks BANK1, BANK2, BANK3, and BANK4 shared, the area of the semiconductor memory device can be prevented from increasing.

In addition, even when a plurality of banks BANK1, BANK2, BANK3, and BANK4 are activated at the same time, current is prevented from being wasted by not detecting the level of the internal voltage VINT level in duplicate.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill.

For example, in the above-described embodiment, the number of banks has been described as being four, but the present invention has a larger number of banks-8, 16, 32,. This includes the case where there are fewer banks-two and one.

In addition, in the above-described first embodiment, the discharge common voltage detection unit has been described as operating in response to a plurality of overdriving pulses. The present invention provides a signal intentionally generated by a designer, for example, a test signal and an MRS ( This includes the case where the common voltage detector for discharging is operated using the MODE REGISTER SETTING signal.

In addition, the logic gate and the transistor illustrated in the above embodiment should be implemented in different positions and types depending on the polarity of the input signal.

1 is a block diagram showing the configuration of a semiconductor memory device employing a discharge driving method according to the prior art.

2A is a circuit diagram illustrating in detail a plurality of discharge voltage detectors and a plurality of discharge drivers among components of a semiconductor memory device employing the discharge drive method shown in FIG. 1;

FIG. 2B is a detailed view of a plurality of charge voltage detectors and a plurality of charge drivers of components of a semiconductor memory device employing the discharge driving method illustrated in FIG. 1;

3 is a block diagram showing the configuration of a semiconductor memory device employing a discharge driving method according to a first embodiment of the present invention.

FIG. 4 is a circuit diagram showing in detail a discharge common voltage detector and a discharge common driver among components of a semiconductor memory device employing the discharge driving method according to the first embodiment of the present invention shown in FIG.

FIG. 5 is a circuit diagram showing in detail a discharge pulse generation unit among components of a semiconductor memory device employing the discharge driving method according to the first embodiment of the present invention shown in FIG.

FIG. 6 is a block diagram showing the configuration of a semiconductor memory device employing a discharge driving method according to a second embodiment of the present invention. FIG.

* Explanation of symbols for main parts of the drawings

100A, 100B, 100C, 100D: discharge voltage detector

300: common voltage detector for discharge

110A, 110B, 110C, 110D: Driving part for discharge

310: common driver for discharge

130A, 130B, 130C, 130D, 330A, 330B, 330C, 330D: charging voltage detector

140A, 140B, 140C, 140D, 340A, 340B, 340C, 340D: Drive part for charging

120, 320: reference voltage generator

180, 380: active signal generator

190 and 390: overdriving pulse generator

160A, 160B, 160C, 160D, 360A, 360B, 360C, 360D: Bit Line Detection Amplifier

170A, 170B, 170C, 170D, 370A, 370B, 370C, 370D: Power Line Driver

Claims (8)

Multiple banks; Discharge pulse generation means for generating a discharge pulse in which an activation period is determined in response to an active signal and an auto refresh signal corresponding to the plurality of banks; Discharge common voltage detecting means for detecting a voltage level of an internal voltage terminal based on a first target level in response to the discharge pulse; And Discharge common driving means for discharging the internal voltage terminal in response to an output signal of the discharge common voltage detecting means; A semiconductor memory device having a. The method of claim 1, A plurality of charging voltage detecting means allocated to each bank and detecting a voltage level of the internal voltage terminal based on a second target level in response to each active signal; And And a charge driving means for charge driving the internal voltage terminal in response to a charge control signal output from each charge voltage detecting means and each active signal. . The method of claim 1, The discharge pulse generating means, An enable pulse generator for generating an enable pulse in which a pulse section is determined in response to the plurality of active signals; A delay unit for delaying the enable pulse by a predetermined time; A pulse section changing section for generating a plurality of section change pulses by varying the pulse section length of the pulse output from the delay section by a predetermined number of times; And And a discharge pulse output unit for outputting any one of a pulse having the longest pulse section and a pulse having the shortest pulse section as the discharge pulse in response to the auto refresh signal. A semiconductor memory device characterized by the above-mentioned. The method of claim 1, The discharge common voltage detection means, A voltage divider for dividing the level of the internal voltage terminal at a predetermined ratio to generate a divided voltage; And And a voltage comparator for comparing the reference voltage corresponding to the first target level with the level of the distribution voltage and controlling an on / off operation thereof in response to the discharge pulse being biased. . And a bit line sensing amplifier for sensing and amplifying data carried on the bit line, and a power line driver for driving the power line of the bit line sensing amplifier with a core voltage or an overdriving voltage applied through a core voltage terminal. Multiple banks; Overdriving pulse generating means for generating a plurality of overdriving pulses for controlling the overdriving operation of each bank in response to an active signal corresponding to each bank; Discharge pulse generation means for generating a discharge pulse in which an activation period is determined in response to the plurality of overdriving pulses and the auto refresh signal; Discharge common voltage detection means for detecting the level of the core voltage terminal based on a first target level in response to the discharge pulse; And Common driving means for discharging for discharging the core voltage terminal in response to an output signal of the common voltage detecting means for discharging; A semiconductor memory device having a. The method of claim 5, A plurality of charging voltage detecting means allocated to each bank and detecting a voltage level of the core voltage terminal based on a second target level in response to each active signal; And And a charge driving means for charge driving the core voltage terminal in response to a charge control signal output from each charge voltage detecting means and each active signal. . The method of claim 5, The discharge pulse generating means, An enable pulse generator for generating an enable pulse in which a pulse interval is determined in response to the plurality of overdriving pulses; A delay unit for delaying the enable pulse by a predetermined time; A pulse section changing section for generating a plurality of section change pulses by varying the pulse section length of the pulse output from the delay section by a predetermined number of times; And And a discharge pulse output unit for outputting any one of a pulse having the longest pulse section and a pulse having the shortest pulse section as the discharge pulse in response to the auto refresh signal. A semiconductor memory device characterized by the above-mentioned. The method of claim 5, The discharge common voltage detection means, A voltage divider for dividing the level of the core voltage terminal at a predetermined ratio to generate a divided voltage; And a voltage comparator for comparing the reference voltage corresponding to the first target level with the level of the distribution voltage and controlling the on / off operation in response to the bias pulse.

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