KR20090110824A - Electronic switch network - Google Patents

Abstract

Systems and methods for switching electronic signals are disclosed. The switching may be performed with a low loss and low peak voltages. The switching scheme is suitable for switching RF signals, for example, and may be used in devices such as wireless systems, terminals, and handsets. One exemplary embodiment is directed to a CMOS-implemented transmit/receive switching system. The system comprises one or more transmit ports, each coupled via a respective transmit path to an input/output port and one or more receive ports, each coupled via a respective receive path to the input/output port. Each receive path comprises a switching circuit comprising a transistor and an inductor in parallel with the transistor. The switching circuit is adapted to at least substantially isolate the respective receive port from the input/output port when the transistor is in an on state and operatively couple the respective receive port to the input/output port when the transistor is an off state.

Description

Electronic switch network {ELECTRONIC SWITCH NETWORK}

[Related Applications]

This application is incorporated by reference in the US Provisional Application Serial No. 60 / 866,147, "Electronic Switch Network", filed November 16, 2006; Non-Provisional Application Serial No. 11 / 809,203, "Electronic Switch Network", filed May 31, 2007; US Provisional Serial No. 60 / 866,144, "Distributed Multi-Stage Amplifier," filed November 16, 2006; And US Provisional Serial No. 60 / 866,139, "Pulse Amplifier," filed November 16, 2006. Each of the above applications is hereby incorporated by reference in its entirety.

This invention relates to the field of electronic and RF switching. Applications include, but are not limited to, wireless systems, microwave components, transceivers, CMOS amplifiers, and portable electronics.

Switches in analog and radio frequency (RF) applications often have to deal with the signal strength of a wide dynamic range. In particular, the transmitter sometimes has to deal with very high peak voltages. This can be a problem in the field of switching design, because signal strength may exceed the device's isolated voltage breakdown. Another problem is that the available control voltages are much smaller than the signal strength. This makes it difficult to keep the switches in the on or off position. Switches in wireless handsets are a notable example of a system that exhibits these problems. For example, for GSM handsets, the maximum signal strength can be as high as 35 dBm. For transmission through a 50 Ohm system, this results in a peak voltage of 17.88 V, while its control voltage and maximum available supply voltage are 2.5 V and 3.5 V, respectively.

1 shows one of the oldest circuits used to address the above problems. In this case, individual PIN diodes are used as the switching element. This type of diode exhibits excellent RF characteristics with large breakdown voltages. Direct current (DC) voltages are used to forward or reverse bias diodes for low or high impedance. A quarter wave matching network is required to separate off ports from on ports. This solution works well for multi-port systems. However, high performance PIN diodes are not easily integrated. In addition, multiple passive components are required to provide bias and matching. Another big problem is the current required to forward bias the diodes. This is acceptable in simple transmit and receive systems because the design can be configured so that the on diode is used only in transmit mode. However, multi-port systems require current even in receive mode.

Another conventional solution is shown in FIG. In this case, field effect transistors (FETs) are used for the switching element. Gallium arsenide (GaAs) pseudomorphic high electron mobility transistors (PHEMTs) are most commonly used because they have low losses and high breakdown voltages. However, the breakdown voltage is only about 16 V, which in itself is too low to handle the high signal levels of GSM systems. In addition, a control voltage of 2.5 V will cause the off transistor to turn on during the negative swing of the output signal. The solution to these problems is to use a plurality of FETs in series as shown in FIG. This effectively divides the signal voltage evenly across each transistor. This solution can handle high signal levels while introducing an acceptable amount of loss. It also has the advantage of near zero current requirement, can be configured for multi-port applications, and can be integrated into a single die. The disadvantage is that multiple control signals are required. The lack of complementary transistor technology for GaAs means that any logic function will draw a significant amount of current. Because of this, separate CMOS control chips are often used with GaAs switch dies. In addition, the use of a different technology means that the switch cannot be integrated with other functions in the headset.

Attempts have been made to use CMOS as a switching technology, but success has been limited. In some cases, DC converters have been used to overcome control signal limitations. However, the high loss of the substrate was unacceptable. Silicon-on-Sapphire (SOS) and other exotic technologies have overcome these problems, but their high cost makes them unsuitable for integration with other functions.

[Summary of invention]

One embodiment of the present invention relates to a switching system operable in a transmit mode and a receive mode. The switching system comprises a transmit port coupled to an input / output port via a transmit path; A receive port coupled to the input / output port via a receive path; And a switching circuit in the receive path. The switching circuit includes a switch device comprising an input terminal, an output terminal, and a control terminal, wherein the control terminal receives a control signal for controlling the state of the switch device between an on state and an off state. When the switch device is in the on state, the switching system is adapted to operate in a transmission mode in which the transmission port is effectively connected to the input / output port and the receiving port is at least substantially separated from the input / output port. do. When the switch device is in the off state, the switching system is adapted to operate in a receive mode in which the receive port is effectively connected to the input / output port.

Another embodiment of the present invention is a CMOS implementation comprising one or more transmit ports, each connected to an input / output port via a respective transmit path, and one or more receive ports, respectively, connected to the input / output port through a respective receive path. Relates to a switching system. Each receive path includes a switching circuit including a transistor and an inductor in parallel with the transistor. The switching circuit at least substantially separates each receive port from the input / output port when the transistor is in an on state and validates each receive port to the input / output port when the transistor is in an off state. It is adapted to make a connection.

Another embodiment of the present invention is an antenna; Radio frequency transmitters; A radio frequency receiver; And a transmitting / receiving device comprising a switching system. The switching system comprises a transmission port disposed between the transmitter and the antenna, the transmission port connected to the antenna via a transmission path; A receive port disposed between the receiver and the antenna, the receive port coupled to the antenna via a receive path; And a switching circuit in the receive path. The switching circuit includes a switch device comprising an input terminal, an output terminal, and a control terminal, wherein the control terminal receives a control signal for controlling the state of the switch device between an on state and an off state. When the switch device is in the on state, the switching system is adapted to operate in a transmission mode in which the transmission port is effectively connected to the input / output port and the receiving port is at least substantially separated from the input / output port. do. When the switch device is in the off state, the switching system is adapted to operate in a receive mode in which the receive port is effectively connected to the input / output port.

Still another embodiment of the present invention provides a transmission mode in which a transmission signal including a transmission carrier signal is transmitted from a transmission port to an input / output port using a CMOS switching circuit, and a reception carrier signal is received from the input / output port. And a switching method comprising switching a transmitting / receiving device between receiving modes to be transmitted. When operated in the transmission mode, the CMOS switching circuit produces no harmonics greater than approximately -60 dB with respect to the transmission carrier signal. When operated in the transmission mode, the CMOS switching circuit imposes a signal loss on the transmission signal that is less than about 2.5 dB.

Yet another embodiment of the present invention provides a transmission mode in which a transmission signal including a transmission carrier signal is transmitted from a transmission port to an input / output port, and a reception mode in which a reception carrier signal is transmitted from the input / output port to a reception port. A switching system comprising a CMOS switching circuit adapted to switch. The CMOS switching circuit is adapted to not produce harmonics greater than approximately -60 dB with respect to the transmit carrier signal when operated in the transmit mode. The CMOS switching circuit is also adapted to impose a signal loss on the transmission signal that is less than about 2.5 dB when operated in the transmission mode.

Yet another embodiment of the present invention is directed to a switching system operable in a transmit mode and a receive mode. The switching system includes a plurality of ports including at least one transmit port coupled to an input / output port and at least one receive port coupled to the input / output port; And a switching circuit adapted to select one of the plurality of ports to be effectively connected to the input / output port, wherein the transmission port is valid for the input / output port when the switching system is operated in a transmission mode. And a receiving port is effectively connected to the input / output port when the switching system is operated in a receiving mode. The switching circuit includes at least one transistor, each transistor of the switching circuit being in an on state when the switching system is operated in the transmission mode.

Yet another embodiment of the present invention is directed to a switching system operable in a first mode and a second mode. The switching system comprises a first port coupled to an input / output port via a first path, the first port passing a first signal; A second port coupled to the input / output port via a second path, the second port passing a second signal having a lower power than the first signal; And a switching circuit in the second path, the switching circuit comprising a switch device comprising an input terminal, an output terminal, and a control terminal, the control terminal receiving a control signal for controlling a state of the switch device. do. The switching circuit comprises (1) the voltage across the switch device is substantially zero, the first port is effectively connected to the input / output port, and the second port is at least substantially from the input / output port. Adapted to switch the switching system between a first mode being separated and (2) a second mode in which the second port is effectively connected to the input / output port.

Another embodiment of the invention provides one or more first ports, each connected to an input / output port via a respective first path, each first port passing a respective first signal; And one or more second ports, each connected to the input / output port via a respective second path, each second port passing a respective second signal having a lower power than each first signal. A switching system implemented. Each second path includes a switching circuit comprising a transistor and an inductor in parallel with the transistor, wherein the switching circuit includes (1) a voltage across the transistor is substantially zero and the first port is connected to the input. A first mode effectively connected to the output / output port, wherein the second port is at least substantially separated from the input / output port, and (2) a second connection of the second port to the input / output port It is adapted to switch the switching system between modes.

1 shows a conventional switch implemented using PIN diodes.

2 shows a first conventional switch implemented using FET switches.

3 shows a second conventional switch implemented using FET switches.

4 shows a first embodiment of a switching system for performing a single-pull-double-row (SPDT) function.

5 shows the circuit of FIG. 4 with a first example of an output matching network (OMN).

6 shows the circuit of FIG. 4 with a second example of OMN.

7 shows another embodiment of a switching system.

8 shows a variation on the circuit of FIG. 7.

9 shows an embodiment of a switching system usable for multi-port operation.

10 shows another embodiment of a switching system usable for multi-port operation.

11 shows a further embodiment of a switching system usable for multi-port operation.

12 shows another embodiment of a switching system usable for multi-band, multi-port operation.

Figure 1 shows how conventional PIN diodes have been used to switch RF signals. The switch 100 includes a transmit port 104 and a receive port 105, each of which is connected to an antenna 106. The transmission path includes a capacitor 108 and a diode 101, an inductor 109 connected between the capacitor 108 and the diode 101, and a capacitor 110 connected between the inductor 109 and ground. . The control signal Vc is applied to the node 111 between the inductor 109 and the capacitor. The receive path comprises a quarter wave line 103, a capacitor 112, and a diode 102 connected between the quarter wave line 103 and the capacitor 112 at one end. Include. At its other end, the diode 102 is connected to ground.

In the transmit mode, the control signal Vc is set high, which forward biases both diodes 101 and 102. When diode 101 is forward biased, it provides a low impedance path from the transmit port 104 to the receive port 105. If the diode 102 is forward biased, it provides a near short circuit for the receive port 105, which helps to isolate the receive port from high transmit signal levels. The quarter wave line 103 converts the short circuit impedance at the receive port 105 to a high new open impedance at the antenna 106. When Vc is set low, both diodes 101 and 102 are reverse biased and placed in a high impedance state. Diode 101 provides a high impedance path and separates the transmit and antenna ports 104 and 106. Diode 102 also enters a high impedance state, which allows signals to flow freely between the receive and antenna ports 105, 106.

2 shows a typical implementation of a single-pull-double-row (SPDT) switch 200 implemented using field effect transistors (FETs) 201 and 202. GaAs PHEMTs are most commonly used in this application. Because these are depletion mode devices, the gate must be biased lower than the drain and source terminals to turn off the transistor. To accommodate this, the switch is typically DC isolated (DC) by using blocking capacitors 203, 204, 205 at the respective transmit, receive and antenna ports 206, 207, 208. isolated) "floating". The control signal Vref applied to one end of the resistor 209 is set to the highest control voltage. Thus, a control signal such as Vref can switch on and a control signal of zero can switch off. When complementary signals are used for control signals Vc1 and Vc2 that are connected to FETs 202 and 201 through resistors 210 and 211, respectively, FETs 201 and 202 toggle. The switch moves between transmit and receive modes.

FIG. 3 shows a switch 300 similar to the SPDT switch of FIG. 2 where the FETs 201 and 202 have been replaced with three series FETs 201a-c and 202a-c, respectively. The control signals Vc2 and Vc1 are used to control the respective chains of FETs 201 and 202. The advantage of this technique is that the voltage is split across the off chain, avoiding breakdown.

Single-pole-multi-throw (SPMT) switch topologies share a common problem for transmit / receive systems. This is partly due to the reciprocal nature of the design. During transmission, one branch of the switch is on while multiple receive branches are off. The switch should have a low loss in the transmit branch while providing adequate isolation for the receive ports to protect low noise amplifiers (LNAs) connected to the receive ports. However, the opposite is different. In receive mode, loss is important, but separation from the transmit port is only important as long as it adversely affects the loss. The received signal strength will not cause any damage to the power amplifier connected to the transmit port. SPMT switch topologies tend to provide similar separation in both cases. Certain example embodiments disclosed herein may utilize these non-uniform or non-mutual requirements.

Another aspect of the switches for the transmit / receive systems is that the largest distortion and potential damage occurs to the devices since the switching transistor remains in the off position with high impedance while the switch is processing the highest signal levels. When the transistors are in a high impedance state, there may be all signal potentials across the terminals of the device. This increases the risk of entering the transistor breakdown region. The presence of both positive and negative voltage swings makes it difficult to keep the transistor completely off, resulting in some channel modulation and signal distortion. Such high voltage potentials with the risk of breakdown and control problems are typically not present in devices in the on position. These devices may be in a low impedance state. Instead they may have to pass large currents. If the devices are scaled to operate in the linear region, the voltage potential can be in a low state, avoiding breakdown and signal distortion, and the devices can be left in the on state. In some example embodiments disclosed herein, the switch may be configured such that all transistors remain on during the transmission mode.

4 illustrates an embodiment of a switching system that utilizes the above-described non-uniform or non-mutual requirements and can be configured to allow all transistors to remain on during the transmission mode. The transmit / receive switching system 400 includes a transmit path including a transmit port 408 connected to an output port 409 via a power amplifier 401 and an impedance matching network 403. Output port 409 is connected to load impedance 404. The switching system 400 also includes a receive path. In the receive path, the receive impedance 407, the switching transistor 406 and the transformer 405 are connected between the receive port 410 and the impedance matching network 403 in parallel with each other. An inductor 402 coupled between the power amplifier 401 and the impedance matching network 403 is used to bias the power amplifier 401. Transformer 405 is coupled to a shunt element of impedance matching network 403. The shunt element can have a wide variety of configurations including one or more resistors, capacitors, and inductors, alone or in combination. In this embodiment, the shunt element is advantageously used at the transmitter without a receive path and can be selected as the element to be connected from the impedance matching network to ground to provide the correct matching impedance to the power amplifier.

In the transmit mode, power amplifier 401 can be turned on and amplifies signal Vin to level Vd. The signal Vd then propagates through the matching network 403. The switching device 406 is on and provides a low impedance from the receive port to ground. This can effectively short out the two primary terminals of the transformer 405. The transformer may map the impedance seen in the primary winding to the secondary winding by the equation Zs = n * Zp. If the primary impedance approaches the short circuit, the secondary impedance may also approach the short circuit. This can effectively connect the shunt elements in the impedance matching network to ground. The shunt device can then have an appropriate impedance that matches the power amplifier 401 to the load impedance 404. For example, the shunt element can be designed such that when connected to ground as previously described, the shunt element has an impedance suitable for matching the power amplifier 401 to the load impedance 404. The low impedance of the switch can provide isolation for the received impedance. When made to the correct size, the switch can provide proper isolation and have a low potential voltage across its terminals. There may be circulating currents in the transformer, and the switch device may be sized to pass these currents without distortion.

In the receive mode, the power amplifier 401 may be off and provide a known impedance to the matching network 403. Depending on the design of the power amplifier 401, this may be an open circuit, a short circuit, or a reactive impedance. The switch 406 can be off and the load impedance 404 can be connected to the receiving impedance 407 via the transformer 405 and the output matching network 403. The output impedance of the power amplifier can result in a connection to the output load of the receive port. Since the separation between the output load and the power amplifier is generally not a concern, the impedance matching network can be designed to accommodate off state power amplifier impedance. An optimal design can be created that provides a good match with low loss between output and receive ports 409 and 410. Other matching elements may be used at the receive port to improve receive matching, loss, and bandwidth.

FIG. 5 shows a more detailed embodiment of the switching system of FIG. 4. In particular, an example implementation of the impedance matching network 403 of FIG. 4 is shown. Impedance matching network 503 includes a first shunt capacitor 508, a series inductor 509, a second shunt capacitor 510, and a series blocking capacitor 511. The shunt capacitor 510 is connected to the secondary winding of the transformer 505. When the switch is on, capacitor 510 is effectively connected to ground and power amplifier 401 can operate with a suitable impedance. Receive port 410 may be separated by the low impedance of the switch and only low signal potentials may be present at the switch terminals. In the receive mode, the power amplifier 401 may be off and provide an impedance characterized by a high real part in parallel with the shunt capacitance. The output capacitance of the device in combination with the shunt capacitor 508 may resonate with the bias inductor 402. The value of inductor 402 may be selected such that reactances are canceled and a high impedance is provided in series inductor 509. In this case, the receiving port 410 may be directly connected through the transformer 405, the shunt capacitance 510, and the blocking capacitance 511. The leakage inductance of the transformer may be designed to cancel the series reactance of the capacitor 510, leaving a low impedance path between the receive port and the output load.

FIG. 6 shows the switching system of FIG. 4 with another exemplary implementation of the impedance matching network 406 of FIG. 4. In this embodiment, the impedance matching network 603 includes a shunt capacitor 608, a series capacitor 609, and a shunt capacitor 610. Operation in the transmit mode is similar to the circuit of FIG. 5 and the receive network connects the inductor 610 to ground for proper fit. In the receive mode, the power amplifier may be placed in a low impedance state. This may happen in some power amplifier circuits. For example, a secondary matching circuit may convert the naturally high state of the amplifier devices from output to low impedance. In this state, capacitor 608 and inductor 602 are effectively removed from the circuit, and one side of series capacitor 609 sees a short. At this time, the capacitor 609 functions as a shunt capacitance in parallel with the inductor 610, the leakage inductance of the transformer and the receiving load. This capacitance can be used to tune the receive branch for optimal performance.

7 shows another exemplary system of a switching system. In the switching system 700, the matching network 703 may represent either the low-pass network of FIG. 5 or the high-pass network of FIG. 6. Shunt matching inductor 704 has been left out of the matching block to illustrate the operation of the switch. As shown, the transformer was realized using coupled inductors 705a and 705b. These can be characterized by the magnetic inductance and mutual inductance of each coil. Those skilled in the art will be able to convert this practical structure into a transformer network characterized by multiple turns and leakage inductances. Combined coils can be realized by parallel windings around the core, spiral inductors printed on a board or substrate, or coupled transmission lines. Capacitors 706 and 707 may be used to resonate with leakage inductance to improve the loss of the transformer. Receive impedance 407 and switch device 406 may operate in a similar manner to corresponding devices in the circuit of FIG. 6.

FIG. 8 is similar to the switching system 700 of FIG. 7, but shows a switching system 800 that replaces the capacitor 707 with a more complex and arbitrary impedance matching network 807. This provides more flexibility to resonate with the leakage current, while at the same time providing a suitable match to the load impedance R _RX 407. Impedance matching network 807 may be comprised of shunt and series capacitors and inductors.

The circuit of Figure 9 shows an embodiment providing two receive ports. This effectively creates a Single-Throw-Triple-Pull (SP3T) switch. Similar to other switching systems described herein, this switching system 900 includes a power amplifier 401 coupled between the transmit port 408 and the bias inductor 402. The bias inductor 402 is connected to an impedance matching network 703, which is connected to the output load 404 at the output port 409. Impedance matching network 703 may include first and second transformers 905 and 910 (or first and second coupled) corresponding to first and second receive ports 913 and 914 through inductor 904. Are connected to inductor pairs 905a, b and 910a, b, inductor 905b is connected in parallel with receive load 908 and switch device 909, and inductor 910b is connected to second receive load 911 and Connected in parallel with the switch device 912. During transmission, both switches 909 and 912 are on and the inductors 905b and 910b are effectively short circuited. The other switch is open while the associated inductor can be left closed to maintain it as an effective short circuit, which provides selectivity between the two ports while maintaining the same advantages during transmit mode. Additional leakage inductance and fire of losses It can be extended to any number of receive ports in exchange for benefit Other techniques and embodiments will be apparent to those skilled in the art.

FIG. 10 shows an alternative embodiment of the multi-port switch of FIG. 9. In particular, the switching system 1000 omits the transformer 910 (or coupled inductors 910a, 910b), such that the switch 1011 is a transformer 905 (or coupled inductors 905a, 905b). ) Is in the ground path. In this case, switch 1011 is not a virtual short circuit provided by transformer 910 (or coupled inductors 910a, 910b) of FIG. 9, but rather a real short circuit at one end of inductor 905a. It can be used to provide. Those skilled in the art will appreciate that various matching elements can be added to improve performance.

FIG. 11 shows a variation on the switching circuit of FIG. 9, where the amplifiers 901a and 901b are matched using inductors or transformers 1103a and 1103b in which the amplifier 901 and matching network 903 are combined. ) Using a pair of. Amplifiers 901a and 901b are associated with first and second transmit ports 908a and 908b, respectively. Amplifier pairs 901a and 901b may be configured differentially or in phase, and may have the same or substantially different sizes. Three or more amplifiers may be combined in this way. Combined inductors, or transformers 1103a and 1103b may also be configured in a similar manner to coupled inductors, or transformers 1105 and 1110. The transformer implementations of 1103a and 1103b may use a turns ratio of 1: 1, or virtually any other turns ratio, as shown.

Figure 12 shows an exemplary embodiment of the invention in which an amplifier consists of a number of small components, each of which is coupled through a coupled inductor transformer network. For example, amplifiers 1201 and 1202 may represent individual amplifiers that cover different frequency ranges. Receive switch sections 1203 and 1204 function in a similar manner to the circuit of FIG. 9, in this case allowing a choice between four receivers Rx 1, Rx 2, Rx 3, Rx 4. In this embodiment, switch sections 1203 and 1204 can be designed to work with individual amplifiers and cover different frequency ranges. Additional transmit or receive paths may be added as desired in accordance with any of the previously described embodiments. In addition, any number of receive switches can be fabricated using complementary metal oxide semiconductor (CMOS) technology. More variations on this subject will be apparent to those skilled in the art.

The circuits of the switching systems described herein include, for example, silicon bipolar transistors, CMOS transistors, gallium arsenide (GaAs), metal semiconductor field effect transistors (MESFETs), heterojunction bipolar transistors (GaBTs), and / or GaAs PHEMTs (GaAs PHEMTs). It can be implemented using a pseudomorphic high electron mobility transistor. The circuits may also be compatible with the various integrated circuit (IC) technologies associated with the above technologies, and may yield a monolithic solution.

One example application of the switching systems described herein is a transmit / receive switch. In the methods and systems described herein, the switch does not produce harmonics greater than approximately -60 dB (or, according to another example, -70 dB) with respect to the transmit carrier signal when the switching system is operated in the transmission mode. In addition, in the methods and systems described herein, a switch imposes a signal loss on the transmission signal that is approximately 2.5 dB (or, according to another example, 1.5 dB) or less. Thus, the transmit / receive switch can advantageously operate with reduced loss and distortion. It is to be understood that the transmit / receive switch is one beneficial application of the switching systems described herein, but the invention is not so limited.

While several aspects of at least one embodiment of the present invention have been described above, it should be appreciated that those skilled in the art will readily conceive of various changes, modifications, and improvements. Such changes, modifications, and improvements are intended to be part of this specification, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description and drawings are by way of example only.

Claims (38)

A switching system operable in a transmit mode and a receive mode, A transmission port connected to the input / output port via a transmission path; A receive port coupled to the input / output port via a receive path; And Switching circuitry in the receive path, the switching circuit including a switch device comprising an input terminal, an output terminal, and a control terminal, wherein the control terminal controls a state of the switch device between an on state and an off state; Receiving—comprising; When the switch device is in the on state, the switching system is in a transmission mode in which the transmission port is operatively connected to the input / output port and the receiving port is at least substantially separated from the input / output port. Adapted to operate; And when the switch device is in the off state, the switching system is adapted to operate in a receive mode in which the receive port is effectively connected to the input / output port. The switching system of claim 1, wherein the switch device comprises a transistor. The switching system of claim 1, wherein the switching system is implemented in a CMOS. The switching system of claim 1, wherein in the receive mode, the transmit path is not separated from the input / output port. 5. The switching system of claim 4, further comprising a power amplifier in the transmission path, wherein the power amplifier has a predetermined impedance when the switching system is in the receive mode. 6. The switching system of claim 5 wherein the impedance of the power amplifier is substantially zero when the switching system is in the receive mode. 6. The switching system of claim 5 wherein the impedance of the power amplifier when the switching system is in the receive mode is an impedance of an open circuit. The switching system of claim 1, wherein the switching system comprises at least one transistor, and wherein each transistor of the switching system is adapted to be in an on state when the switching system is in the transmission mode. The method of claim 1, A second receive port coupled to the input / output port via a second receive path; And A second switching circuit in the second receive path, the second switching circuit including a second switch device comprising an input terminal, an output terminal, and a control terminal, wherein the control terminal comprises the second switching device between an on state and an off state; Receiving a second control signal for controlling a state of the switch device; And when the second switch device is in the off state, the switching system is adapted to operate in a second receive mode in which the second receive port is effectively connected to the input / output port. The switching system of claim 1, wherein the switching circuit is adapted to create at least a substantially short circuit between the receive port and ground. The switching system of claim 1, wherein the switching circuit further comprises an inductor in parallel with the switch device. The switching system of claim 11, wherein the switch device is adapted to substantially short circuit the inductor when the switch device is in the on state. The switching system of claim 1, wherein the switching circuit further comprises a transformer in parallel with the switch device. The switching system of claim 1, wherein the transmit port and the receive port are connected to the input / output port via an impedance matching network. 15. The switching system of claim 14, wherein in the transmission mode, the switching circuit is adapted to create a virtual ground at a node between the impedance matching network and the receiving port. 2. The switching system of claim 1, further comprising means for at least substantially separating the receive port from the input / output port in the transmit mode. The switching system of claim 1, wherein the input / output port comprises an antenna. The switching system of claim 1 further comprising a power amplifier in the transmission path. 19. The switching system of claim 18 wherein said power amplifier is implemented in CMOS. The switching circuit of claim 1, wherein when the switching system is operated in the transmission mode, the switching circuit is adapted to not generate harmonics greater than approximately −60 dB, and when the switching system is operated in the transmission mode. And the switching circuit is adapted to impose a signal loss on the transmission signal that is less than about 2.5 dB. CMOS implemented switching system, One or more transmit ports, each connected to an input / output port through each transmit path; And One or more receive ports, each connected to the input / output port via a respective receive path; Each receive path includes a switching circuit comprising a transistor and an inductor in parallel with the transistor, the switching circuit at least substantially separating the respective receive port from the input / output port when the transistor is in an on state. And adapted to effectively connect each receive port to the input / output port when the transistor is in an off state. 22. The system of claim 21 wherein the one or more receive paths include first and second receive paths. 23. The system of claim 22, wherein the first and second receive paths comprise first and second switching circuits, respectively, including first and second transistors, respectively, wherein the first and second switching circuits comprise the switching system. And a CMOS implemented switching system configured and arranged such that each of the first and second transistors is in an on state during a transmission mode of the < RTI ID = 0.0 > As a transmission / reception device, antenna; Radio-frequency transmitters; A radio frequency receiver; And A switching system; The switching system, A transmission port disposed between the transmitter and the antenna, the transmission port being connected to the antenna via a transmission path; A receive port disposed between the receiver and the antenna, the receive port coupled to the antenna via a receive path; And Switching circuitry in the receive path, the switching circuit including a switch device comprising an input terminal, an output terminal, and a control terminal, wherein the control terminal controls a state of the switch device between an on state and an off state; Receiving—comprising; When the switch device is in the on state, the switching system is configured to operate in a transmission mode in which the transmission port is effectively connected to the input / output port and the receiving port is at least substantially separated from the input / output port. Is adapted; When the switch device is in the off state, the switching system is adapted to operate in a receive mode in which the receive port is effectively connected to the input / output port. 25. The transmit / receive device of claim 24 further comprising a power amplifier in the transmit path. 25. The transmit / receive device of claim 24 wherein the switching system is implemented in CMOS. As a switching method, Using a CMOS switching circuit, a transmission is performed between a transmission mode in which a transmission signal including a transmission carrier signal is transmitted from a transmission port to an input / output port and a reception mode in which a reception carrier signal is transmitted from the input / output port to a reception port. Switching the receiving device; When operated in the transmission mode, the CMOS switching circuit does not produce harmonics greater than approximately -60 dB with respect to the transmission carrier signal; And when operated in the transmission mode, the CMOS switching circuit imposes a signal loss on the transmission signal that is less than about 2.5 dB. As a switching system, A CMOS switching circuit adapted to switch between a transmission mode in which a transmission signal comprising a transmission carrier signal is transmitted from a transmission port to an input / output port and a reception mode in which a reception carrier signal is transmitted from the input / output port to a reception port. Including; The CMOS switching circuit is adapted to not generate harmonics greater than approximately -60 dB with respect to the transmit carrier signal when operated in the transmit mode; The CMOS switching circuit is adapted to impose a signal loss on the transmission signal that is less than about 2.5 dB when operated in the transmission mode. 29. The switching system of claim 28 wherein said CMOS switching circuit is integrated on a non-silicon on insulator (SOI) silicon substrate. 30. The switching system of claim 29, wherein said non-SOI silicon substrate comprises at least a portion of a single crystal silicon wafer. A switching system operable in a transmit mode and a receive mode, A plurality of ports including at least one transmit port connected to an input / output port and at least one receive port connected to the input / output port; And A switching circuit adapted to select one of the plurality of ports to be effectively connected to the input / output port, wherein the transmission port is effectively connected to the input / output port when the switching system is operated in a transmission mode. A receiving port is effectively connected to the input / output port when the switching system is operated in a receiving mode; The switching circuit comprises at least one transistor, each transistor of the switching circuit being in an on state when the switching system is operated in the transmission mode. 32. The switching system of claim 31 wherein at least one receive path between the at least one receive port and the input / output port comprises the at least one transistor. A switching system operable in a first mode and a second mode, A first port coupled to an input / output port via a first path, the first port passing a first signal; A second port coupled to the input / output port via a second path, the second port passing a second signal having a lower power than the first signal; And Switching circuitry in the second path, the switching circuit including a switch device comprising an input terminal, an output terminal, and a control terminal, the control terminal receiving a control signal for controlling a state of the switch device; and; The switching circuit has (1) the voltage across the switch device is substantially zero, the first port is effectively connected to the input / output port, and the second port is at least substantially from the input / output port. Switching system adapted to switch the switching system between a first mode being separated and (2) a second mode in which the second port is effectively connected to the input / output port. As a switching system, One or more first ports, each connected to an input / output port via a respective first path, each first port passing a respective first signal; And One or more second ports each connected to the input / output port via a respective second path, each second port passing a respective second signal having a lower power than each first signal; Each second path includes a switching circuit comprising a transistor and a transformer in parallel with the transistor; The switching circuit comprises (1) the voltage across the transistor is substantially zero, the first port is effectively connected to the input / output port, and the second port is at least substantially separated from the input / output port. Switching system between the first mode, and (2) a second mode in which the second port is effectively connected to the input / output port. 35. The switching system of claim 34, wherein said one or more first ports comprise a single port and said one or more second ports comprise a plurality of ports. 35. The switching system of claim 34, wherein said one or more first ports comprise a plurality of ports and said one or more second ports comprise a plurality of ports. 35. The switching system of claim 34, wherein said one or more first ports comprise a single port and said one or more second ports comprise a single port. 35. The switching system of claim 34, wherein said one or more first ports comprise a plurality of ports and said one or more second ports comprise a single port.

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