KR20090110612A - Backside illuminated image sensor and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A backside-irradiated image sensor and a manufacturing method thereof are provided to facilitate a back grinding process control by controlling a rear side grinding target of a substrate in a back grinding process. CONSTITUTION: A backside-irradiated image sensor includes a light receiving device, an interlayer insulation film(108A), an aligning key(112), a wiring layer, a protective layer(124), a pad(125), a light scattering preventing film(126A), a color filter(128), and a micro lens(130). The light receiving device is formed inside a first substrate(100C). The interlayer insulation film includes a light receiving device, and is formed on the first substrate. The aligning key is separated from the light receiving device, and penetrates the interlayer insulation film and the first substrate.

Description

BACKSIDE ILLUMINATED IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME}

TECHNICAL FIELD The present invention relates to semiconductor manufacturing technology, and more particularly, to an image sensor and a method for manufacturing the same, and more particularly to a backside illuminated image sensor and a method for manufacturing the same.

In general, a complementary metal oxide semiconductor (CMOS) image sensor has a peripheral area such as a light receiving element unit, a digital control block, an analog-to-digital converter, and the like in a limited area chip, so that the area ratio of the pixel array per chip area is high. It is limited to around 40%. In addition, the pixel size is reduced in order to achieve high quality, and thus, the amount of light that can be received by one light receiving element is reduced, resulting in various problems such as image loss due to increased noise.

Accordingly, the present invention has been proposed to solve the problems of the prior art, and an object thereof is to provide a back-illuminated image sensor and a method of manufacturing the same that emit light from the back of the wafer.

According to an aspect of the present invention, there is provided a light receiving device formed in a first substrate, an interlayer insulating film formed on the first substrate including the light receiving device, and the interlayer insulating film spaced apart from the light receiving device. And an alignment key formed through the first substrate, a wiring layer formed on a plurality of layers on the interlayer insulating film and having a rear surface of a lowermost layer connected to the alignment key, a protective layer formed to cover the wiring layer, and the first layer. A pad formed locally on the rear surface of the substrate and connected to the rear surface of the alignment key, an anti-scattering film formed on the rear surface of the first substrate including the pad, and on the light scattering prevention film so as to correspond to the light receiving element; It provides a back-illuminated image sensor comprising a color filter and a micro lens formed in the.

According to another aspect of the present invention, there is provided a light receiving device formed in a first substrate, an interlayer insulating film formed on the first substrate including the light receiving device, and spaced apart from the light receiving device. An alignment key formed through the interlayer insulating film and the first substrate, a wiring layer formed in multiple layers on the interlayer insulating film, and having a bottom surface of the lowermost layer exposed, a protective layer formed to cover the wiring layer, and the first substrate. The present invention provides a backside irradiation image sensor including a light scattering prevention film formed on the rear surface and a color filter and a micro lens formed on the light scattering prevention film so as to correspond to the light receiving element.

In addition, the present invention according to another aspect for achieving the above object, forming a light receiving element in the first substrate, forming an interlayer insulating film on the first substrate including the light receiving element, Forming a via hole by partially etching the interlayer insulating film and the first substrate, forming an alignment key to fill the via hole, and forming a multilayer wiring layer on the first substrate including the alignment key. Forming a protective layer to cover the wiring layer; bonding a second substrate to the protective layer; exposing a rear surface of the alignment key to the rear surface of the first substrate; Forming a pad locally on a rear surface of the first substrate so as to be connected to a rear surface of the first substrate, and forming a light scattering prevention layer on a rear surface of the first substrate including the pads; It provides a method of manufacturing a back-illuminated image sensor comprising the step of forming a color filter and a micro lens on the light scattering prevention film so as to correspond to the light receiving element.

In addition, the present invention according to another aspect for achieving the above object, forming a light receiving element in the first substrate, forming an interlayer insulating film on the first substrate to cover the light receiving element, Forming a via hole by partially etching the interlayer insulating film and the first substrate, forming an alignment key to fill the via hole, and forming a multilayer wiring layer on the first substrate including the alignment key. Forming a protective layer to cover the wiring layer; bonding a second substrate to the protective layer; exposing a rear surface of the alignment key to the rear surface of the first substrate; Forming a light scattering prevention film on a rear surface of the first substrate, including partially etching the light scattering prevention film, the first substrate, and the interlayer insulating film; A step of exposing the back surface, and provides a process for the production of the back illuminated image sensor comprising the step of forming a color filter and a microlens on the light scattering film to correspond with the light-receiving element.

According to the present invention having the configuration described above, the following effects can be obtained.

First, according to the present invention, by providing a back-illuminated image sensor that shines light from the back of the substrate (wafer) to minimize the loss of light incident to the light receiving element compared to the conventional CMOS image sensor (front-illuminated image sensor) The light receiving yield can be improved.

Second, according to the present invention, in the method of manufacturing a back-illuminated image sensor applying a back grinding process, a via-hole alignment key is formed in the substrate before the back grinding process of grinding the back surface of the substrate, and using the same. Therefore, the back grinding process can be easily controlled by controlling the back grinding target of the substrate during the back grinding process.

Third, according to the present invention, the upper surface of the alignment key is in contact with the wiring layer formed on the front surface of the substrate, and the rear surface is exposed to the rear surface of the substrate so as to connect with the pad and use the alignment key as a contact plug for connecting the pad and the wiring layer. It can be placed on the back of the substrate rather than on the front, providing a variety of designs for the packaging process.

Fourthly, according to the present invention, in the back-illuminated image sensor that shines light from the back side of the substrate (wafer), a light scattering prevention film for preventing the scattering of light incident on the back side of the substrate is formed to increase the light concentrating ratio to the photodiode. The light reception yield can be improved.

Hereinafter, with reference to the accompanying drawings, the most preferred embodiment of the present invention will be described in detail. In addition, in the drawings, the thicknesses and spacings of layers and regions are exaggerated for ease of explanation and clarity, and when referred to as being on or above another layer or substrate, it is different. It may be formed directly on the layer or the substrate, or a third layer may be interposed therebetween. In addition, the parts denoted by the same reference numerals throughout the specification represents the same layer, and when the reference numerals include the English, it means that the same layer is partially modified through an etching or polishing process. In addition, the first and second conductivity types are p-type or n-type means different conductivity types.

Example 1

1 is a cross-sectional view for explaining a back-illuminated image sensor according to Embodiment 1 of the present invention. For convenience of explanation, only the photodiode and the gate electrode of the driving transistor are shown among the unit pixels of the CMOS image sensor.

As shown in FIG. 1, the back-illuminated image sensor according to Embodiment 1 of the present invention includes a device wafer (a wafer on which a light receiving element such as a photodiode is formed) and a handle wafer 200 (digital). A wafer in which a peripheral circuit such as a block or an analog digital converter is formed) is bonded to each other. Hereinafter, for convenience of description, the device wafer will be referred to as a first substrate, and the handle wafer will be referred to as a second substrate.

Specifically, the back-illuminated image sensor according to the first embodiment of the present invention includes a light receiving element formed in the first substrate 100C, for example, a photodiode 106 and an image on the first substrate 100C including the photodiode 106. Formed on the interlayer insulating film 108A, the photodiode 106, and an alignment key 112 formed through the interlayer insulating film 108A and the first substrate 100C, and on the interlayer insulating film 108A. A protective layer formed in multiple layers and formed so as to cover the wiring layers 113, 116, 119, 122 connected to the alignment key 112, and the back surface of the lowermost layer 113, and the wiring layers 113, 116, 119, 122. 124, a pad 125 formed locally on the rear surface of the first substrate 100C and connected to the rear surface of the alignment key 112, and on the rear surface of the first substrate 100C including the pad 125. A color filter and a microlens 128 formed on the light scattering prevention film 126A formed on the light scattering prevention film 126A so as to correspond (overlap) with the photodiode 106. 130).

The first and second substrates 100C and 200 may use any one selected from a bulk substrate, an epitaxial substrate, or a silicon on insulator (SOI) substrate, respectively. Preferably, the first substrate 100C uses an SOI substrate in which semiconductor layers / buried oxide layers / semiconductor layers are stacked in consideration of device characteristics, and the second substrate 200 uses a relatively inexpensive bulk substrate.

The alignment keys 112 may be formed in plural, and the plurality of alignment keys 112 may be connected to one pad 125. In addition, the alignment key 112 has an upper surface connected to the lowermost layer 113 among the wiring layers 113, 116, 119, and 122, so that the signal (voltage) applied from the pad 125 is applied to the wiring layers 113, 116, 119, and the like. 122). The alignment key 112 may be formed of a conductive material such as a metal or an alloy film. In addition, the alignment key 112 is formed in a circle (including ellipse) or polygon (triangle, square, pentagon, etc.), the number and size (width) is not limited.

The light scattering prevention film 126A may be formed of a multilayer film in which materials having different refractive indices are stacked. For example, it is formed of a laminated film (oxidized film / nitride film or nitride film / oxide film) in which an oxide film and a nitride film are laminated, and a laminated film (oxide film / SiC or SiC / oxide film) in which an oxide film and carbon-containing film (SiC) are laminated. . In this case, the oxide film is any one selected from BPSG (BoroPhosphoSilicate Glass), PSG (PhosphoSilicate Glass), BSG (BoroSilicate Glass), USG (Un-doped Silicate Glass), TEOS (Tetra Ethyle Ortho Silicate), or HDP (High Density Plasma) film. It can be formed into a film. The nitride film may be formed of a silicon nitride film (Si _x N _y , where x and y are natural numbers) or a silicon oxynitride film (Si _x O _y N _z , where x and y are natural numbers). In addition, the nitride film may be formed as an NH rich nitride film having more NH bonds than Si ₃ N ₄ bonded in a relatively stable state in the silicon nitride film. Further, the nitride film or SiC is formed to a thin thickness. Preferably, the oxide film is formed to a thickness of 1000 to 10000 kPa, and the nitride film or SiC is formed to a thickness of 100 to 5000 kPa.

In addition, the backside illumination image sensor according to Embodiment 1 of the present invention further includes a barrier layer (not shown) formed to surround the outer wall of the alignment key 112. In this case, the barrier layer may be formed of a metal material or an insulating material. For example, the metal material is formed of a laminated film (Ti / TiN) in which Ti and TiN are stacked. The insulating material is composed of a nitride film (eg, silicon nitride film), an oxide film (silicon oxide film), or a laminated film (oxide film / nitride film) on which they are laminated.

In addition, the back-illuminated image sensor according to Embodiment 1 of the present invention further includes a plurality of transistors for transmitting and processing (amplifying) the optical signal focused on the photodiode 106. For example, the driving transistor among the plurality of transistors is formed in the gate electrode 104 formed between the first substrate 100C and the interlayer insulating film 108A, and in the first substrate 100C exposed to both sides of the gate electrode 104. Source and drain regions 107.

Hereinafter, a manufacturing method of a backside illuminated image sensor according to Embodiment 1 of the present invention will be described.

2A to 2K are cross-sectional views illustrating a method of manufacturing a backside illuminated image sensor according to Embodiment 1 of the present invention. As an example, an SOI substrate will be described as an example.

First, as shown in FIG. 2A, a first substrate 100, for example, an SOI substrate, is prepared. The SOI substrate includes the first semiconductor layer 100-1, the buried oxide layer 100-2, and the second semiconductor layer 100-3. In this case, the second semiconductor layer 100-3 may be doped with the first conductive type or the second conductive type. For example, it is doped with a first conductivity type. In addition, the buried oxide layer 100-2 may be formed to a thickness of 500 to 10000 GPa, and the second semiconductor layer 100-3 may be formed to a thickness of about 1 to 10 μm.

Subsequently, the device isolation layer 101 is locally formed in the first substrate 100. In this case, the device isolation layer 101 may be formed by a shallow trench isolation (STI) process or a LOCOS (LOCal Oxidation of Silicon) process. However, the device isolation layer 101 may be formed by an STI process that is advantageous for high integration, as shown in FIG. When the STI process is applied, it may be formed of a high density plasma (HDP) film having excellent embedding characteristics even at a high aspect ratio or a laminated film of an HDP film and a spin on dielectric (SOD) film.

Subsequently, the gate insulating layer 102 and the gate conductive layer 103 are formed on the first substrate 100 and then etched to form the gate electrode 104 of the driving transistor. At the same time, although not shown, the gate electrodes of the transfer transistor, reset transistor, and select transistor constituting the unit pixel of the CMOS image sensor may also be formed.

Subsequently, spacers 105 may be formed on both sidewalls of the gate electrode 104. In this case, the spacer 105 may be formed of an oxide film, a nitride film, or a laminated film in which they are stacked.

Meanwhile, a lightly doped drain (LDD) region (not shown) doped with a second conductivity type may be formed in the first substrate 100 exposed to both sides of the gate electrode 104 before the spacer 105 is formed.

Subsequently, an ion implantation process is performed in the first substrate 100 to form a photodiode 106 that is a light receiving element. At this time, the photodiode 106 is doped with low concentration to the second conductivity type.

Next, a source and drain region 107 heavily doped with a second conductivity type is formed in the first substrate 100 exposed to both sides of the spacer 105. In this case, the source and drain regions 107 are formed to have a higher doping concentration than the LDD region and the photodiode 106.

Subsequently, a doped region (not shown) that is doped with a first conductivity type may be further formed to cover the upper surface of the photodiode 106 to prevent surface noise of the photodiode 106.

Meanwhile, in the manufacturing method, a method of sequentially forming the gate electrode 104, the spacer 105, the photodiode 106, the source and drain regions 107 has been described as an example, but the order in which they are formed is not limited. It can be changed according to the manufacturing process.

Next, an interlayer insulating film 108 is formed to cover the first substrate 100 including the gate electrode 104, the spacer 105, the photodiode 106, the source and drain regions 107. In this case, the interlayer insulating film 108 may be formed of an oxide film, eg, an oxide film (SiO ₂ ) containing silicon, and more specifically, may be formed of any one selected from BPSG, PSG, BSG, USG, TEOS, and HDP films. It can be formed from these laminated films. In addition, it may be formed of a film coated by a spin coating method, such as a spin on dielectric (SOD) film.

Subsequently, as illustrated in FIG. 2B, an etching process is performed to locally etch the interlayer insulating layer 108A, thereby forming a contact hole 109 through which the source and drain regions 107 are exposed. In this case, the etching process may be either a dry etching or a wet etching process. Preferably, it is preferably carried out by a dry etching process so that the cut surface is vertical.

Subsequently, the interlayer insulating film 108A and the first substrate 100A are etched locally to form the via holes 110 extending from the interlayer insulating film 108A to the first semiconductor layer 100-1A. In this case, the via holes 110 may be formed in plural numbers arranged in a matrix type.

More specifically, the vertical angle of the via hole 110 is formed to be 88 ~ 90 °, the depth is formed to a depth of 20000 Å or less, preferably 4000 ~ 20000 Å relative to the upper surface of the interlayer insulating film (108A). More preferably, it is formed to a depth of 1000 ~ 10000Å relative to the upper surface of the second semiconductor layer (100-3A). The width (critical dimension, CD) is formed to be 2.0 µm or less, preferably 1.0 to 2.0 µm. In addition, the bottom width of the via hole 110 is formed to be 1.6 μm or less, preferably 1.0 to 1.6 μm. In addition, when the plurality of via holes 110 are implemented, it is preferable to form the via holes 110 so that the variation in angle, depth and width therebetween is 4% or less. In addition, the number and shape of the via holes 110 is not limited. In particular, without limitation to the form, it can be implemented in various forms, such as a circular or polygonal (triangle, square, pentagon, octagon, etc.) structure.

The order of forming the contact holes 109 and the via holes 110 is not limited, and the via holes 110 may be formed first, and then the contact holes 109 may be formed. In addition, these 109 and 110 may be formed by in-situ using the same plasma etching equipment.

For example, the via hole 110 is divided into two stages using a dry etching process.

First, the first step is to etch the interlayer insulating film 108A. The etching rate (selection ratio) of the interlayer insulating film 108A with respect to the photosensitive film pattern (not shown) is 5: 1 to 2: 1 (interlayer insulating film: photosensitive film pattern), preferably 2.4: 1 (interlayer insulating film: photosensitive film pattern) Under conditions of In addition, the etching amount is performed to be 7000 to 8000 Å / min, preferably 7200 Å / min. For example, as etching conditions, a pressure of 100 to 200 mTorr and a source power of 100 to 2000 W are used, and a fluorocarbon compound such as CHF ₃ or CF ₄ is used as a source gas to improve etching speed and anisotropy. Ar is further added to the source gas to be used. At this time, the flow rate of CHF ₃ is set to 5 to 200 sccm, the flow rate of CF ₄ is set to 20 to 200 sccm, and the flow rate of Ar is set to 100 to 2000 sccm.

The second step is to etch the first substrate 100A. In the second step, the etching amount is 1000 to 3000 m 3 / min, preferably 2000 m 2 / min. For example, as an etching condition, a pressure of 15 to 30 mTorr, 400 to 600 W of source power (RF power), and 80 to 120 W of bias power (power to improve ion straightness) are used. SF ₆ and O ₂ are used. At this time, the flow rate of SF ₆ is 5 ~ 200sccm, the flow rate of O ₂ is 1 ~ 100sccm.

In the second step, the etching process may be performed so that the buried oxide layer 100-2A is partially etched or the buried oxide layer 100-2A is completely etched to partially etch the first semiconductor layer 100-1A. In the former case, the buried oxide layer 100-2A may be over-etched about 100 to 4000 kPa.

Subsequently, as illustrated in FIG. 2C, a barrier layer (not shown) may be formed on inner surfaces of the contact hole 109 (see FIG. 2B) and the via hole 110 (see FIG. 2B). In this case, the barrier layer may be formed of any one of Ti, TiN, Ta, TaN, AlSiTiN, NiTi, TiBN, ZrBN, TiAlN, TiB ₂ or a laminated film thereof, such as Ti / TiN and Ta / TaN. The barrier layer has a thickness of less than or equal to 100 μs, preferably 50 to 100 μs, using an ALD (Atomic Layer Deposition) process having excellent coating properties to minimize the reduction of the width of the contact hole 109, especially the via hole 110. It is formed to a thickness of about. In addition, it may be formed by a MOCVD (Metal Organic Chemical Vapor Deposition), PVD (Physical Vapor Deposition) process.

In addition, the barrier layer may be formed of any one of an oxide film (eg, silicon oxide film), a nitride film (eg, silicon nitride film), or a laminated film thereof (nitride film / oxide film). For example, in the case of a nitride film / oxide film laminated film, the oxide film and the nitride film are each formed in a liner shape such that the total thickness thereof is 200 kPa or less. This minimizes the width reduction of the via hole 110.

Subsequently, a conductive material is embedded in the contact hole 109 and the via hole 110 to form a contact plug 111 and an alignment key 112. In this case, as the conductive material, any one of Cu, Pt, W, Al, or an alloy film including these materials may be used. However, the conductive material is not limited to these materials, and any metal or alloy film having conductivity may be used. For example, when using W as a conductive material, it is formed by CVD (Chemical Vapor Depostion) process or ALD process, and when Al is formed by CVD process. In addition, when using Cu, it forms by an electroplating method or a CVD process.

Meanwhile, the contact plug 111 and the alignment key 112 may be formed at the same time as described above, or the contact plug 111 may be formed first, and then the alignment key 112 may be formed, or the alignment key 112 may be formed. After the contact plug 111 may be formed. When the contact plug 111 and the alignment key 112 are not formed at the same time, the contact plug 111 and the alignment key 112 may be formed of different materials. For example, the contact plug 111 is formed of a polysilicon film doped with impurity ions, and the alignment key 112 is formed of the conductive material described above.

As an example, a method of forming the contact plug 111 and the alignment key 112 will be described below. First, the contact hole 109 is formed by depositing a polysilicon film doped with impurity ions or the aforementioned conductive material so as to fill the contact hole 109, and then performing an etch back process or a chemical mechanical polishing (CMP) process. An isolated contact plug 111 is formed therein. Then, after the conductive material is deposited to fill the via hole 110, an etch back or CMP process is performed to form an isolated alignment key 112 inside the via hole 110.

Subsequently, as illustrated in FIG. 2D, a plurality of metal wiring layers 113, 116, 119, and 122, contact plugs 115, 118, and 121, and an interlayer insulating layer 114, 117, 120, and 123 are formed. For example, some of the lowermost layers 113 among the plurality of wiring layers 113, 116, 119, and 122 are electrically separated from each other and connected to the contact plug 111, and some of them are connected to the alignment key 112.

The wiring layers 113, 116, 119 and 122 are formed through a deposition process and an etching process. It is formed of a conductive film such as a metal or an alloy film in which at least two kinds of metals are mixed. It is preferably formed of Al. The contact plugs 115, 118, and 121 are formed through damascene processes in the interlayer insulating layers 114, 117, 120, and 123, respectively, and the wiring layers 113, 116, 119, and 122 stacked up and down are formed. It is formed by any one selected from a conductive material such as a polycrystalline silicon film doped with impurity ions, a metal, or an alloy film containing at least two kinds of metals for electrical connection. It is preferably formed of W. The interlayer insulating layers 114, 117, 120, and 123 may be formed of any one oxide film selected from a BPSG, PSG, BSG, USG, TEOS, or HDP film, or may be formed as a laminated film in which two or more layers are stacked. In addition, the interlayer insulating layers 114, 117, and 120 may be planarized through a CMP process after deposition.

On the other hand, the number and structure of the wiring layer 113, 116, 119, 122 and the contact plugs (115, 118, 121) is not limited, it can be applied to a variety of layers and structures according to the device design.

Subsequently, a passivation layer 124 is formed on the interlayer insulating layer 123. In this case, the protective layer 124 may be formed of a film selected from among BPSG, PSG, BSG, USG, TEOS, or HDP. Preferably, the film is formed to a thickness of 1000 to 40000 kV using a TEOS film or an HDP film. The protective layer 124 may be formed of a nitride film or a laminated film of an oxide film and a nitride film.

Next, the protective layer 124 is planarized. At this time, the planarization process may be performed by a CMP process.

Subsequently, a heat treatment process can be performed to achieve densification of the protective layer 124. In this case, the heat treatment process may be performed by an annealing process using a furnace (furnace) equipment.

Subsequently, as illustrated in FIG. 2E, the first substrate 100A and the second substrate 200 manufactured through the processes of FIGS. 2A to 2D are bonded. In this case, the bonding process may use any one method selected from among oxide film-oxide film bonding, oxide film-silicon bonding, oxide film-metal film bonding, oxide film-bonding member-oxide film bonding or oxide film-bonding member-silicon bonding.

For example, the oxide film-oxide film (formed on the second substrate 200) junction and the oxide film-silicon (silicon substrate) junction are both plasma treatment—O ₂ or N ₂ used—and water treatment. ) And then join. Moreover, in addition to the method of joining after water treatment, the application of the method of joining after chemical processing, such as an amine, is also possible. In the oxide film-metal film (formed on the second substrate 200), a metal such as titanium (Ti), aluminum (Al), copper (Cu), or the like may be used as the metal film. In the oxide film-adhesive member-oxide film bonding and the oxide film-adhesive member-silicon bonding method, BCB (Benzo Cyclo Butene) may be used as the adhesive member.

Subsequently, as shown in FIG. 2F, a back grinding process is performed to grind the back surface of the first substrate 100A (see FIG. 2E). In this case, when the alignment key 112 is formed to penetrate the buried oxide layer 100-2A, the back grinding process is performed until the buried oxide layer 100-2A is exposed to expose the alignment key 112. In this process, the buried oxide layer 100-2A may be removed to a certain thickness. On the other hand, when the alignment key 112 is formed of a structure that does not penetrate the buried oxide layer 100-2A (a structure extended to a predetermined depth into the buried oxide layer 100-2A), the buried oxide layer ( 100-2A) Alternatively, the buried oxide layer 100-2A may be etched by removing a predetermined thickness or all or performing a separate etching process.

Subsequently, as illustrated in FIG. 2G, a plurality of pads 125 are formed on the rear surface of the buried oxide layer 100-2A so as to be electrically connected to the rear surface of the alignment key 112. In this case, the pad 125 may be formed of any one of a conductive material, for example, a metal or an alloy film in which at least two kinds of metals are mixed. It is preferably formed of Al. In addition, each of the pads 125 may be formed to be connected to a plurality of alignment keys 112 arranged in a matrix.

Subsequently, as illustrated in FIG. 2H, a region overlapping with the photodiode 106 in the buried oxide layer 100-2B is etched and removed. That is, the buried oxide layer 100-2B is locally removed so that the buried oxide layer 100-2B does not exist in the region overlapping with the photodiode 106. As a result, the second semiconductor layer 100-3A in the region overlapping the photodiode 106 is exposed.

Subsequently, as shown in FIG. 2I, a light scattering prevention layer 126 is formed on the pad 125, the second semiconductor layer 100-3A, and the buried oxide layer 100-2B. In this case, the light scattering prevention film 126 may be formed as a multilayer film in which materials having different refractive indices are stacked. For example, it is formed of a laminated film (oxidized film / nitride film or nitride film / oxide film) in which an oxide film and a nitride film are laminated, and a laminated film (oxide film / SiC or SiC / oxide film) in which an oxide film and carbon-containing film (SiC) are laminated. .

The oxide film may be formed of any one of TEOS, USG, HDP, BSG, PSG, and BPSG. The nitride film may be formed of a silicon nitride film (Si _x N _y , where x and y are natural numbers) or a silicon oxynitride film (Si _x O _y N _z , where x and y are natural numbers). In addition, the nitride film may be formed as an NH rich nitride film having more NH bonds than Si ₃ N ₄ bonded in a relatively stable state in the silicon nitride film. At this time, the NH-enriched nitride film is formed by performing a flow rate ratio (SiH ₄ : NH ₃ ) of silane (SiH ₄ ) gas and ammonia (NH ₃ ) gas at 1: 1 to 1:20, preferably 1:10.

The nitride film or SiC is formed in a thin thickness. Preferably, the oxide film is formed to a thickness of 1000 ~ 10000 Pa, the nitride film or SiC is formed to a thickness of 100 ~ 5000 kPa.

On the other hand, the light scattering prevention film 126 (in the case of a multilayer film) is to perform the film deposition process in-situ method in the same chamber without moving the chamber in order to reduce the stability and processing time of the manufacturing process. desirable. However, if the in-situ method is not allowed, the film deposition process may be performed in an ex-situ method in different chambers.

Subsequently, as shown in FIG. 2J, a protective layer 126 may be formed on the light scattering prevention film 126. In this case, the protective layer 126 may be formed of an insulating material, for example, an oxide film.

Subsequently, the protective layer 126 may be locally etched to partially expose the light scattering prevention layer 126 on the pad 125.

Subsequently, the color filter 128 and the microlens 130 are sequentially formed on the passivation layer 127 overlapping the photodiode 106. In this case, the planarization layer 129 may be formed as an over coating layer (OCL) between the protective layer 127 and the color filter 128, and between the color filter 128 and the microlens 130, respectively. In this case, the planarization layer may be formed of an organic material.

Subsequently, a low temperature oxide film 131 called LTO (Low Teperature Oxide) may be formed on the microlens 130, the light scattering prevention film 126, and the protective layer 127.

Subsequently, as illustrated in FIG. 2K, the low temperature oxide layer 131A and the light scattering prevention layer 126A are locally etched to expose some or all of the pads 125 for wire bonding.

Next, a packaging process is performed to package the first substrate 100C and the second substrate 200. At this time, the packaging process includes a wire bonding process and a sawing process. Here, the wire bonding is made by connecting the pad 125 and the external chip with a wire.

Example 2

3 is a cross-sectional view illustrating a backside illumination image sensor according to Embodiment 2 of the present invention. For convenience of description, only the photodiode and the gate electrode of the driving transistor are shown among the unit pixels of the CMOS image sensor.

Referring to FIG. 3, a back side illumination image sensor according to Embodiment 2 of the present invention may include a first substrate including a light receiving element formed in the first substrate 300D, for example, a photodiode 306 and a photodiode 306. On the interlayer insulating film 308B formed on the insulating layer 300D, the alignment key 312A formed to penetrate the interlayer insulating film 308B and the first substrate 300D while being spaced apart from the photodiode 306, and on the interlayer insulating film 308B. A protective layer 324 formed in multiple layers and formed to cover the wiring layers 313, 316, 319, and 322 on which the bottom surface of the lowermost layer 313 is exposed, the wiring layers 313, 316, 319, and 322, and a first layer; The light scattering prevention film 325 formed on the rear surface of the substrate 300D and the color filter and the micro lenses 327 and 329 formed on the light scattering prevention film 325 to correspond to the photodiode 306 are included. The backside illumination image sensor according to Embodiment 2 of the present invention further includes a second substrate (handle wafer) 400 bonded to the top surface of the protective layer 324.

Embodiment 2 of the present invention has a configuration similar to that of the first embodiment. However, in Example 1, the pad is formed on the back surface of the first substrate 100C (see FIG. 1). In Example 2, the pad is exposed by exposing the bottom surface of the bottom layer 313 among the wiring layers 313, 316, 319, and 322. As a separate pad is formed on top of it. That is, the first and second embodiments differ only in the positions where the pads are formed, and the other configurations are the same. In addition, in the second embodiment, the alignment key 312A is formed of an insulating material rather than a conductive material like the alignment key 112A according to the first embodiment.

As such, the backside illumination image sensor according to the second exemplary embodiment of the present invention differs only in a material related to the pad and the material constituting the alignment key, and the other configuration is the same as that in the first exemplary embodiment. The description described in 1 will be replaced.

Hereinafter, a method of manufacturing a backside illuminated image sensor according to Embodiment 2 of the present invention will be described.

4A to 4K are cross-sectional views illustrating a method of manufacturing a backside illuminated image sensor according to Embodiment 2 of the present invention. As an example, an SOI substrate will be described as an example.

First, FIGS. 4A and 4B proceed in the same manner as FIGS. 2A and 2B of the first embodiment.

Subsequently, as shown in FIG. 4C, a conductive material is embedded in the contact hole 309 (see FIG. 4B) to form the contact plug 311. In this case, as the conductive material, any one of Cu, Pt, W, Al, or an alloy film including these materials may be used. However, the conductive material is not limited to these materials, and any metal or alloy film having conductivity may be used. For example, when using W as a conductive material, it is formed by CVD (Chemical Vapor Depostion) process or ALD process, and when Al is formed by CVD process. In addition, when using Cu, it forms by an electroplating method or a CVD process.

Subsequently, an insulating material 312 is formed on the entire surface including the interlayer insulating film 308A so as to fill the via hole 310 (see FIG. 4B). At this time, the insulating material 312 is preferably formed of a material having excellent embedding characteristics. For example, the insulating material 312 is formed of an oxide film-based material or a nitride film-based material. Specifically, the oxide-based material may be formed of a silicon oxide film, more specifically, a film selected from any one of BPSG, BSG, USG, TEOS, and HDP film, or a laminated film thereof. In addition, the nitride film-based material may be formed of a silicon nitride film. In addition, it may be formed of a film coated by a spin coating method such as a spin on dielectric (SOD) film having excellent coating properties.

Next, as shown in FIG. 4D, a planarization process is performed to form an alignment key 312A having an isolated pillar structure inside the via hole 310 (see FIG. 4B). In this case, the planarization process may include an etch back process or a chemical mechanical polishing (CMP) process.

4E to 4G then proceed in the same manner as FIGS. 2D to 2F of the first embodiment.

Subsequently, FIGS. 4H and 4I illustrate a buried oxide layer 300-2B etching process and light for locally exposing the second semiconductor layer 300-3A excluding the pad in a localized manner (region overlapping the photodiode). The scattering prevention film 325 forming process is performed in the same manner as in the first embodiment.

Subsequently, as shown in FIG. 4J, the light scattering prevention film 325, the buried oxide layer 300-2C, the second semiconductor layer 300-3B, and the interlayer insulating film 308B are removed from the rear surface of the first substrate 300D. Local etching is performed to locally expose the back surface of the lowermost wiring layer 313. As a result, the lowermost wiring layer 313 exposed serves as a pad and is wire bonded through a subsequent process.

Meanwhile, after exposing the back surface of the wiring layer 313, an additional pad conductive material may be formed on the back surface of the wiring layer 313. In this case, the conductive material may be formed of a metal or a mixed film mixed with metal. It is preferably formed of aluminum.

Subsequently, as shown in FIG. 4K, a protective layer 326 may be formed on the light scattering prevention layer 325. In this case, the protective layer 326 may be formed of an insulating material, for example, an oxide film.

Subsequently, the color filter 327 and the microlens 329 are sequentially formed on the protective layer 326 overlapping the photodiode 306. In this case, the planarization layer 328 may be formed as an over coating layer (OCL) between the protective layer 326 and the color filter 327, and between the color filter 327 and the microlens 329, respectively. In this case, the planarization layer may be formed of an organic material.

Subsequently, a low temperature oxide film 330 called LTO (Low Teperature Oxide) may be formed on the microlens 329, the light scattering prevention film 325, and the protective film 326.

Subsequently, a packaging process is performed to package the first substrate 300D and the second substrate 400. At this time, the packaging process includes a wire bonding process and a sawing process. Here, wire bonding is performed by connecting a pad (wiring layer) and an external chip with a wire.

As described above, although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In particular, although the embodiment of the present invention has been described as an example of the CMOS image sensor, it can be applied to both the image sensor and the integrated device of the 3D structure using the back irradiation method. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a cross-sectional view showing a back-illuminated image sensor according to Embodiment 1 of the present invention.

2A to 2K are cross-sectional views illustrating a method of manufacturing a backside illuminated image sensor according to Embodiment 1 of the present invention.

3 is a cross-sectional view showing a back-illuminated image sensor according to Embodiment 2 of the present invention;

4A to 4K are cross-sectional views illustrating a method of manufacturing a backside illuminated image sensor according to Embodiment 2 of the present invention;

<Explanation of symbols for the main parts of the drawings>

100, 100A, 100B, 300, 300A, 300B, 300C, 300D: first substrate (element wafer)

101, 301: device isolation film

102, 302: gate insulating film

103 and 303: gate conductive film

104, 304: gate electrode

105, 305: spacer

106, 306: Photodiode

107 and 307: source and drain regions

108, 108A, 114, 117, 120, 123, 308, 308A, 314, 317, 320, 323: interlayer insulating film

109, 309: Contact hole

110, 310: Via Hole

111, 115, 118, 121, 311, 3115, 3118, 321: contact plug

112, 312A: Sort Key

113, 116, 119, 122, 313, 316, 319, 322: wiring layer

124, 126, 324, 326,: protective layer

125: pad

126, 325: light scattering prevention film

128, 327: color filter

129, 328: planarization film

130, 329: Micro Lens

131, 330: low temperature oxide film

200, 400: second substrate (handle wafer)

Claims (46)

A light receiving element formed in the first substrate; An interlayer insulating layer formed on the first substrate including the light receiving element; An alignment key spaced apart from the light receiving element and penetrating the interlayer insulating layer and the first substrate; A wiring layer formed on the interlayer insulating film in multiple layers and having a rear surface of a lowermost layer connected to the alignment key; A protective layer formed to cover the wiring layer; A pad locally formed on a rear surface of the first substrate and connected to a rear surface of the alignment key; A light scattering prevention film formed on a rear surface of the first substrate including the pad; And Color filters and micro lenses formed on the light scattering prevention film so as to correspond to the light receiving element Back irradiation image sensor comprising a. A light receiving element formed in the first substrate; An interlayer insulating layer formed on the first substrate including the light receiving element; An alignment key spaced apart from the light receiving element and penetrating the interlayer insulating layer and the first substrate; A wiring layer formed on the interlayer insulating film in multiple layers and having a rear surface of a lowermost layer exposed; A protective layer formed to cover the wiring layer; A light scattering prevention film formed on the rear surface of the first substrate; And Color filters and micro lenses formed on the light scattering prevention film so as to correspond to the light receiving element Back irradiation image sensor comprising a. The method according to claim 1 or 2, The light scattering prevention film is a back-illuminated image sensor consisting of a multilayer film laminated with materials having different refractive indices. The method of claim 3, wherein The multilayer film may be formed of a laminated film in which an oxide film and a nitride film are laminated, or a back-illuminated image sensor comprising a laminated film in which an oxide film and a carbon-containing film are laminated. The method of claim 4, wherein The oxide film is any one selected from BPSG (BoroPhosphoSilicate Glass), PSG (PhosphoSilicate Glass), BSG (BoroSilicate Glass), USG (Un-doped Silicate Glass), TEOS (Tetra Ethyle Ortho Silicate), or HDP (High Density Plasma) film. Membrane back-illuminated image sensor. The method of claim 4, wherein The nitride film is a back irradiation image sensor consisting of a silicon nitride film or a silicon oxynitride film. The method of claim 4, wherein The nitride film is a back-illuminated image sensor consisting of an NH-enriched nitride film with more NH bonds than Si ₃ N ₄ . The method of claim 4, wherein The carbon-containing film is a SiC film back-illuminated image sensor. The method of claim 4, wherein The oxide film is a back irradiation image sensor formed to a thickness of 1000 ~ 10000Å. The method of claim 4, wherein The nitride film or the carbon-containing film is a back-illuminated image sensor formed to a thickness of 100 ~ 5000Å. The method of claim 1, And the alignment key is formed of a conductive material. The method of claim 2, The alignment key is a back irradiation image sensor formed of an insulating material. The method according to claim 1 or 2, And a plurality of alignment keys. The method according to claim 1 or 2, The alignment key is a rear irradiation image sensor formed of a pillar (pillar) structure. The method of claim 1, And a barrier layer formed to surround the outer wall of the alignment key. The method of claim 15, The barrier layer is a back irradiation image sensor made of a metal material or an insulating material. The method according to claim 1 or 2, And a second substrate bonded to the protective layer. The method of claim 1, And the first substrate is any one selected from a bulk substrate, an epitaxial substrate, and a silicon on insulator (SOI) substrate. The method of claim 18, And the alignment key is formed through the buried oxide layer of the SOI substrate. The method of claim 19, And the pad is partially formed on the back side of the buried oxide layer of the SOI substrate. The method of claim 19, And the light scattering prevention layer is formed on a rear surface of the buried oxide layer and a rear surface of a semiconductor layer of the SOI substrate to which the buried oxide layer is removed. The method of claim 21, And a region of the semiconductor layer to which the buried oxide layer is removed and exposed is an area overlapping the light receiving element. The method of claim 2, And the first substrate is any one selected from a bulk substrate, an epitaxial substrate, and a silicon on insulator (SOI) substrate. Forming a light receiving element in the first substrate; Forming an interlayer insulating film on the first substrate including the light receiving element; Partially etching the interlayer insulating layer and the first substrate to form via holes; Forming an alignment key to fill the via hole; Forming a multilayer wiring layer on the first substrate including the alignment key; Forming a protective layer to cover the wiring layer; Bonding a second substrate to the protective layer; Exposing a back side of the alignment key to a back side of the first substrate; Forming a pad locally on a rear surface of the first substrate to be connected to a rear surface of the alignment key; Forming a light scattering prevention film on a rear surface of the first substrate including the pad; And Forming a color filter and a micro lens on the light scattering prevention layer so as to correspond to the light receiving element; Method of manufacturing a back irradiation image sensor comprising a. Forming a light receiving element in the first substrate; Forming an interlayer insulating film on the first substrate to cover the light receiving device; Partially etching the interlayer insulating layer and the first substrate to form via holes; Forming an alignment key to fill the via hole; Forming a multilayer wiring layer on the first substrate including the alignment key; Forming a protective layer to cover the wiring layer; Bonding a second substrate to the protective layer; Exposing a back side of the alignment key to a back side of the first substrate; Forming a light scattering prevention film on a rear surface of the first substrate including the alignment key; Partially etching the light scattering preventing film, the first substrate, and the interlayer insulating film to expose a bottom surface of a lowermost layer of the wiring layer; And Forming a color filter and a micro lens on the light scattering prevention layer so as to correspond to the light receiving element; Method of manufacturing a back irradiation image sensor comprising a. The method of claim 24 or 25, The light scattering prevention film is a method of manufacturing a back-illuminated image sensor formed of a multilayer film in which materials having different refractive indices are stacked. The method of claim 26, The multilayer film may be formed of a laminated film in which an oxide film and a nitride film are laminated, or a method of manufacturing a backside irradiation image sensor formed of a laminated film in which an oxide film and a carbon-containing film are laminated. The method of claim 27, The multilayer film is a method of manufacturing a back-illuminated image sensor is carried out in-situ process in the same chamber. The method of claim 27, The multi-layer film manufacturing method of the back-illuminated image sensor is carried out in an ex-situ method in another chamber, The method of claim 27, The oxide film is any one selected from BPSG (BoroPhosphoSilicate Glass), PSG (PhosphoSilicate Glass), BSG (BoroSilicate Glass), USG (Un-doped Silicate Glass), TEOS (Tetra Ethyle Ortho Silicate), or HDP (High Density Plasma) film. Method of manufacturing a back-illuminated image sensor formed of a film. The method of claim 27, The nitride film is a silicon nitride film or a silicon oxynitride film is a manufacturing method of the backside irradiation image sensor. The method of claim 27, The nitride film is a method of manufacturing a back-illuminated image sensor formed of an NH-enriched nitride film with a lot of NH bonds compared to Si ₃ N ₄ . The method of claim 32, The NH-enriched nitride film is a method of manufacturing a backside irradiation image sensor formed by performing a flow rate ratio (SiH ₄ : NH ₃ ) of a silane (SiH ₄ ) gas and an ammonia (NH ₃ ) gas within a range of 1: 1 to 1:20. The method of claim 27, The oxide film is a manufacturing method of the back-illuminated image sensor to form a thickness of 1000 ~ 10000Å. The method of claim 27, The nitride film or the carbon-containing film is a method of manufacturing a back-illuminated image sensor to form a thickness of 100 ~ 5000Å. The method of claim 24, And the alignment key is formed of a conductive material. The method of claim 25, And the alignment key is formed of an insulating material. The method of claim 24 or 25, And a plurality of alignment keys. The method of claim 24 or 25, The alignment key is a manufacturing method of a back-illuminated image sensor formed in a pillar (pillar) structure. The method of claim 24, After forming the via hole, And forming a barrier layer on an inner surface of the via hole. The method of claim 24 or 25, The first substrate is a method of manufacturing a back-illuminated image sensor using any one selected from a bulk substrate, an epitaxial substrate or a silicon on insulator (SOI) substrate. 42. The method of claim 41 wherein In the case of using the SOI substrate, the forming of the via hole may include: And a via hole penetrating the buried oxide layer of the SOI substrate. 42. The method of claim 41 wherein In the case of using the SOI substrate, the forming of the via hole may include: And forming a portion of the via hole to extend into the buried oxide layer of the SOI substrate. The method of claim 43, Exposing the back of the alignment key, Back grinding the back surface of the SOI substrate; And Etching the buried oxide layer so that the back side of the alignment key is exposed Method of manufacturing a back irradiation image sensor comprising a. The method of claim 43, After forming the pad, And removing the buried oxide layer formed in an area overlapping with the light receiving element. The method of claim 24 or 25, After forming the color filter and the micro lens, And packaging the first and second substrates.

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