KR20090109730A - Substrate for semiconductor device and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A substrate for semiconductor device and method for manufacturing the same are provided to minimize the product failure by performing easily substrate handling. CONSTITUTION: The semiconductor substrate includes the substrate(301), the hemi spherical metal layer(302), and the semiconductor layer(304). The hemi spherical metal layer is formed by the discontinuous on the substrate. The hemi spherical metal layer includes the group III metal. The semiconductor layer is formed on the hemi spherical metal layer. The semiconductor layer includes the nitride of the group III metal. The hemi spherical metal layer which is discontinuous on the substrate is formed. The semiconductor layer is formed on the overall structure including the hemi spherical metal layer.

Description

SUBSTRATE FOR SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

The present invention relates to a semiconductor substrate, and more particularly, to a semiconductor substrate comprising a discontinuously formed hemispherical metal layer formed to minimize interlayer stress and a semiconductor layer formed on the metal layer and a method of manufacturing the same.

A semiconductor device is one of electronic components that implements electronic devices such as a power device, a light emitting device, and a light receiving device on a predetermined substrate by using semiconductor processing technology. For example, a power device includes a transistor, a MOSFET, an Insulated Gate Bipolar Transistor (IGBT), a Schottky diode, and the like, and a light receiving device includes a solar cell, a photo sensor, and the like on a substrate.

In particular, III-V nitride semiconductors such as GaN have been spotlighted as core materials of light emitting devices such as light emitting diodes (LEDs) or laser diodes (LDs) due to their excellent physical and chemical properties. LEDs or LDs using III-V nitride semiconductor materials are widely used in light emitting devices for obtaining light in the blue or green wavelength band, and these light emitting devices are used as light sources of various products such as electric signs and lighting devices. The III-V nitride semiconductor is generally made of a GaN-based material having a composition formula of In _X Al _Y Ga _{1 -X-YN} (0 <X, X + Y <1).

1 is a cross-sectional view showing a nitride light emitting device according to the prior art.

Referring to FIG. 1, the nitride light emitting device includes a GaN buffer layer 110, an n-type cladding layer 120, and a single quantum well (SQW) structure InGaN or InGaN on a sapphire substrate 100, which is a light transmissive substrate. An active layer 130 and a p-type cladding layer 140 having a multi-quantum well (MQW) structure are sequentially stacked. At this time, a portion of the p-type cladding layer 140 and the active layer 130 is removed by a mesa etching process, a part of the upper surface of the n-type cladding layer 120 is exposed. In addition, an n-type electrode 170 is formed on the exposed n-type cladding layer 120, and the transparent conductor layer 150 made of ITO and the p-type electrode 160 are sequentially formed on the p-type cladding layer 160. Are stacked. In addition, the buffer layer 110 is generally formed to a thickness of several nm.

However, conventionally, the problem of the generation of stress and crystal defects due to the difference in the crystal lattice of each layer generated by using a heterogeneous substrate is not solved. As a result, the electrostatic (ESD), breakdown voltage, leakage current, etc. characteristics of the electronic device, in particular, the light emitting device are degraded, resulting in a problem of reliability deterioration, such as a low yield and short product life. have.

In addition, a nitride semiconductor substrate has been studied as an alternative substrate to solve the problem of such a heterogeneous substrate, but it is still insufficient in commercialization. In the case of forming the nitride semiconductor by a conventional deposition technique, u-GaN or n-Ga including a buffer layer having a thickness of about 2 μm is used on a heterogeneous substrate, because technical limitations are followed in a subsequent device manufacturing process. In general, when a total of 5 μm or more of nitride semiconductors are formed on a heterogeneous substrate, warpage of the substrate is remarkably generated, which makes it difficult to perform a subsequent manufacturing process, particularly a photo process and an etching process.

In order to overcome these technical limitations, the current limit of the thickness of the entire nitride semiconductor, using a thick substrate, or using a substrate having a small diameter to reduce the warpage of the substrate. However, this method is only a temporary measure to overcome technical limitations and is not a fundamental solution.

The present invention has been proposed to solve the above problems, by forming a discontinuous hemispherical metal layer on the substrate and then forming a semiconductor layer thereon to planarize, thereby forming a plurality of cavities at the interface with the substrate and metal concentration in the semiconductor layer. It is an object of the present invention to provide a semiconductor substrate and a method of manufacturing the same, in which a gradient is formed so that deformation of the substrate can be prevented.

In addition, the present invention is 70μm or less when the thickness of the final substrate is 5 to 100μm including the semi-spherical metal layer and the semiconductor layer under the condition that the warp of the final substrate is 2 inches in diameter and the substrate thickness is 430μm applied to the subsequent semiconductor device process Another object of the present invention is to provide a semiconductor substrate and a method of manufacturing the same, which can be controlled, thereby making it easy to apply to subsequent device fabrication processes and minimizing product defect rates.

According to an aspect of the present invention, there is provided a semiconductor substrate comprising: a substrate; A hemispherical metal layer formed discontinuously on the substrate; And a semiconductor layer formed on the hemispherical metal layer. Characterized in that it comprises a.

It is preferable that the hemispherical metal layer contains a Group 3 metal, and the semiconductor layer contains a nitride of the Group 3 metal.

The Group 3 metal preferably contains at least one of gallium (Ga) and indium (In).

The discontinuous hemispherical metal layer preferably has a diameter in the range of 0.1 to 5μm.

Preferably, the semiconductor layer includes a plurality of cavities formed at an interface with the substrate.

The semiconductor layer preferably has a concentration gradient in which the density of the metal is lowered in the thickness direction.

A semiconductor substrate according to another aspect of the present invention for achieving the above object, the substrate; A hemispherical metal layer formed discontinuously on the substrate; And a semiconductor layer formed on the hemispherical metal layer. Wherein the semiconductor layer has a concentration gradient in which the metal density is lowered in the thickness direction by the hemispherical metal layer, and the total size of the hemispherical metal film and the semiconductor layer is under a condition that the size of the substrate is 2 inches and the thickness is 430 μm. When the thickness is 5 to 100 μm, the final bending characteristic is characterized by less than 70 μm.

It is preferable that the hemispherical metal layer contains a Group 3 metal, and the semiconductor layer contains a nitride of the Group 3 metal.

The Group 3 metal preferably contains at least one of gallium (Ga) and indium (In).

Preferably, the semiconductor layer includes a plurality of cavities formed at an interface with the substrate.

According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor substrate, including: preparing a substrate; Forming a discontinuous hemispherical metal layer on the substrate; And forming a semiconductor layer on the entire structure including the hemispherical metal layer. Characterized in that it comprises a.

It is preferable that the hemispherical metal layer contains a Group 3 metal, and the semiconductor layer contains a nitride of the Group 3 metal.

The Group 3 metal preferably contains at least one of gallium (Ga) and indium (In).

The hemispherical metal layer preferably has a diameter in the range of 0.1 to 5μm.

The hemispherical metal layer forming step is preferably performed at a temperature above the melting point of the metal or at a temperature below 450 degrees.

Preferably, the hemispherical metal layer forming step and the semiconductor layer forming step are repeated at least once or more times.

Cleaning the surface of the substrate after at least one of the substrate preparing step, the hemispherical metal layer forming step and the semiconductor layer forming step; And treating the surface of the substrate; It is preferable to further comprise at least one step of.

Preferably, the hemispherical metal layer forming step and the semiconductor layer forming step are performed in different chambers. At this time, the step of forming the hemispherical metal layer is carried out by any one of the method of sputtering, E-Beam and MBE, the step of forming the semiconductor layer is preferably performed by any one of the MOCVD, HVPE and MBE.

Alternatively, the hemispherical metal layer forming step and the semiconductor layer forming step may be performed in the same chamber. At this time, the hemispherical metal layer forming step and the semiconductor layer forming step is preferably carried out by HVPE method.

Preferably, the semiconductor layer includes a plurality of cavities formed at an interface with the substrate.

The semiconductor layer preferably has a concentration gradient in which the density of the metal is lowered in the thickness direction.

According to the present invention, a non-continuous hemispherical metal layer is formed on a substrate, and then a semiconductor layer is formed and planarized thereon, whereby a plurality of fine cavities are formed at an interface with the substrate and a metal concentration gradient perpendicular to the semiconductor layer is formed. The hemispherical metal layer remains at the interface of. Therefore, the microcavity inherent in the semiconductor layer, the vertical metal concentration gradient of the semiconductor layer, and the residual hemispherical metal layer serve to absorb or relieve interfacial stress, thereby preventing substrate deformation.

In addition, the present invention is that the semiconductor layer formed on the discontinuous hemispherical metal layer to relieve stress, when the semiconductor layer including the hemispherical metal layer is 5 to 100 μm under the condition that the substrate size is 2 inches and the thickness is 430μm The final bending property of the substrate can be controlled to 70 μm or less. Therefore, since substrate handling such as substrate chucking and substrate alignment is easy, subsequent device fabrication processes such as a photo process and an etching process may be smoothly performed, thereby minimizing product defect rates.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information. Like reference numerals in the drawings refer to like elements.

In the drawings, the thickness of layers, films, panels, regions, etc., may be exaggerated for clarity, and like reference numerals designate like elements. In addition, when a part such as a layer, a film, an area, or a plate is expressed as “above” or “above” another part, each part is not only when the part is “right above” or “just above” the other part, This includes the case where there is another part between other parts.

2 is a process flowchart illustrating a method of manufacturing a semiconductor substrate according to an embodiment of the present invention, and FIGS. 3A to 3C are cross-sectional views illustrating a process of manufacturing a semiconductor substrate according to an embodiment of the present invention.

In the substrate loading step (S110), the substrate is loaded into the chamber in a state in which the prepared chamber is purged with N ₂ gas, and the substrate is mounted in a substrate holder provided in the chamber. The substrate holder may be any means as long as the substrate can be stably fixed to a predetermined deposition position. For example, the substrate holder may be a holder type for holding the substrate surface vertically, or a stage type for placing the substrate surface horizontally may be used. Also, the substrate may be a silicon on insulation (SOI) substrate or a single crystal semiconductor wafer having a single crystal semiconductor layer. The single crystal semiconductor layer may be any one of a single crystal silicon layer, a single crystal sapphire layer, a single crystal germanium layer, a single crystal silicon germanium layer or a single crystal silicon carbide layer, and the single crystal semiconductor wafer is a single crystal silicon wafer, a single crystal sapphire wafer, a single crystal germanium wafer , A single crystal silicon germanium wafer or a single crystal silicon carbide wafer. In this embodiment, a case of using a single crystal sapphire wafer (hereinafter referred to as a sapphire substrate) will be described.

In the surface cleaning step (S120), impurities remaining on a surface, for example, a substrate surface, are removed using a cleaning gas. In this embodiment, the surface was washed for about 5 to 30 minutes using a mixed gas having a mixing ratio of HCl and N2 of 1: 5 to 1:10.

In the surface treatment step (S130), a nitrogen (N) -containing gas and / or an oxygen (O) -containing gas are supplied to the surface of the substrate to form a nitride layer, an oxide layer, or an oxynitride layer. At least one thin film layer is formed. In the case of using a sapphire substrate, if a reaction gas containing nitrogen, for example, N ₂ , NH ₃ , NH ₃ / N _2, etc. is supplied, a nitride film will be formed, and a reaction gas containing nitrogen and oxygen may be used. For example, supplying a mixed gas of NH ₃ and O ₂ will form an oxynitride film. In addition, when a reaction gas containing nitrogen, oxygen, and silicon, for example, a mixed gas of N ₂ O and Si, is supplied, a silicon oxynitride layer will be formed.

On the other hand, the surface cleaning step (S120) and surface treatment step (S130) may be carried out at the same time, any one step may be omitted. In addition, the surface cleaning step (S120) and surface treatment step (S130) is preferably carried out using a HVPE (Hydride Vapor Phase Epitaxy) process. The HVPE process is connected to the inside of the chamber and provides a reaction gas and a transfer gas to a container in which a raw material is introduced, for example, a feed tube into which a metal raw material is inserted, thereby heating raw substrates decomposed from the raw material into a heated substrate. By allowing it to be supplied to the surface, raw material particles are deposited on the substrate surface by the gas phase reaction to grow a desired thin film on the substrate. At this time, HCl gas may be used as the reaction gas, and inert gas such as N ₂ or Ar may be used as the transfer gas.

The step of forming a semiconductor layer including a discontinuous hemispherical metal layer (S140) is a step of forming a discontinuous hemispherical metal layer with a Group 3 metal on the surface-treated substrate (S142) and a single layer or multiple layers on the hemispherical metal layer. A step (S144) of forming the configured nitride semiconductor layer.

First, as shown in FIG. 3A, sputtering, molten beam epitaxy (MBE), E-Beam evaporator, metal organic chemical vapor deposition (MOCVD), and HVPE (HVPE) at a temperature above the melting point of the metal used or a temperature below 450 degrees Ga metal is deposited on the surface-treated substrate 301 by various methods such as Vapor Phase Epitaxy. At this time, the Ga metal 302 is formed as a seed that does not spread widely in the horizontal direction of the substrate 301 due to the surface tension and is formed discontinuously in large and small hemispherical shapes to help the growth of the nitride semiconductor layer to be formed later. Function. In particular, the hemispherical metal layer 302 is preferably formed in a size of approximately 0.1 to 5μm over the entire area of the substrate 301. Of course, the hemispherical metal layer 302 is not limited to the above-described Ga metal, and may be formed of a Group 3 metal, for example, In metal.

3B, when the nitride semiconductor layer 303 is deposited on the entire structure including the hemispherical metal layer 302, the nitride semiconductor layer 303 grows vertically and horizontally on the surface of the hemispherical metal layer 302. . Accordingly, as the fine cavity 305 is formed between the hemispherical metal layers 302, the space between the hemispherical metal layers 302 is gradually narrowed, and the nitride semiconductor layer 303 is deposited to a sufficient thickness as shown in FIG. 3C. As the space between the metal layers 302 is filled, the top surface of the nitride semiconductor layer 303 is planarized to be suitable for subsequent device growth. In this case, the nitride semiconductor layer 303 may be formed to have a thickness of about 5 to 100 μm by various methods such as MBE, MOCVD, and HVPE. Of course, in the present embodiment, the hemispherical metal layer 302 and the nitride semiconductor layer 303 are formed separately, but they may be formed almost simultaneously. In addition, the nitride semiconductor layer 303 may be formed in multiple layers instead of a single layer.

On the other hand, the step (S142) to form the above-described hemispherical metal layer may be carried out by varying the post-process (S130, S144) and the process equipment. In other words, when the surface treatment of the substrate, which is a preliminary process (S130), is finished, the substrate is unloaded in the HVPE equipment, and then the substrate is loaded in the MBE equipment to form a hemispherical metal layer on the substrate, and the substrate is unloaded again in the MBE equipment. Thereafter, the substrate may be loaded on the HVPE apparatus to form a nitride semiconductor layer.

In addition, in the semiconductor layer forming step (S140) including the discontinuous hemispherical metal layer, each process step (S142 or S144) may be repeatedly performed one or more times (S140), and the entire process steps (S142 and S144) are performed. Can be repeated one or more times. In addition, at least one of the surface cleaning step (S120) and the surface treatment step (S130) is selectively performed between each step (S142 or S144) in the semiconductor layer forming step (S140) including a discontinuous hemispherical metal layer. Can be. For example, the surface cleaning step S120 may be performed before the step S142 or S144, and the surface treatment step S130 may be subsequently performed, or the surface cleaning step S130 may be performed according to a process requirement. The surface treatment step S130 may be performed alone.

In the substrate unloading step S160, first, after the steps S110 to S130 are completed, purging using N ₂ gas is performed. Subsequently, while purging with N ₂ gas, the temperature is gradually lowered until the internal temperature of the chamber reaches room temperature. Through this, it is possible to minimize the thermal shock of the substrate. Thereafter, the substrate is detached from the substrate holder, and the detached substrate is taken out of the chamber. In this case, the substrate drawn out of the chamber may be introduced into a subsequent process for forming an electronic device such as a power layer, a light emitting device, a light receiving device, and the like on top thereof.

Through such a process step, a semiconductor layer including a discontinuous hemispherical metal layer having a thickness of 15 μm may be formed on the substrate, thereby manufacturing a semiconductor substrate having less warpage characteristics. Hereinafter, the characteristics of the semiconductor substrate will be described.

4A and 4B are SEM plan and cross-sectional photographs of a hemispherical metal layer according to an embodiment of the present invention. The hemispherical metal layer is formed by MBE in a temperature condition of about 200 degrees using Ga metal. Referring to Figure 4, the hemispherical metal layer can be confirmed that the size of approximately 0.1 to 2μm, it can be seen that such a hemispherical metal layer has a three-dimensional solid structure. 5A and 5B are SEM plan and cross-sectional photographs of a nitride semiconductor layer according to an exemplary embodiment of the present invention, wherein the nitride semiconductor layer is formed in an HVPE method at a temperature of approximately 1050 degrees. Referring to FIG. 4B, the nitride layer semiconductor layer also has three-dimensional thin film characteristics due to the three-dimensional three-dimensional structure of the hemispherical metal layer existing below. As a result, a plurality of fine voids may be formed in the nitride semiconductor layer, thereby relieving the interfacial stress between the nitride semiconductor layer and the substrate. In addition, the hemispherical metal layer continuously supplies Ga metal to the nitride semiconductor layer at the time of forming the nitride semiconductor layer, whereby a concentration gradient of the vertical Ga metal along the height is formed in the nitride semiconductor layer. The vertical gradient of Ga metal serves to relieve the interfacial stress between the substrate and the nitride semiconductor layer, and the Ga metal remaining on the substrate also contributes to relieving the interfacial stress between the substrate and the nitride semiconductor layer. As a result, it is possible to manufacture a semiconductor substrate having relatively less warpage characteristics of the substrate.

FIG. 6A is a graph illustrating the warpage characteristics of a semiconductor substrate according to an experimental example of the present invention, and FIG. 6B is a graph illustrating the warpage characteristics of a semiconductor substrate according to a comparative example of the present invention.

First, in the semiconductor substrate according to the experimental example of the present invention, a Ga metal, which is a hemispherical metal layer, is formed on the sapphire substrate by the MEB method to about 0.1 to 2 μm in size, and a nitride semiconductor layer having a thickness of 3 μm is formed by the HVPE method. In this case, as shown in FIG. 6A, warpage of about 7.25 μm occurred under the condition that the sapphire substrate had a thickness of 430 μm and a size of 1 inch. This is calculated as a warpage of approximately 28 to 30 μm in terms of the sapphire substrate thickness of 430 μm and the size of a 2 inch substrate. On the other hand, in the semiconductor substrate according to the comparative example of the present invention, a nitride semiconductor layer having a thickness of about 2 μm was formed on the sapphire substrate under the same conditions except for the hemispherical metal layer. In this case, as shown in FIG. 6B, it was confirmed that warpage of approximately 18.01 μm occurred under the condition that the sapphire substrate had a thickness of 430 μm and a size of 1 inch. This is calculated as a warpage of approximately 72 to 75 μm in terms of the sapphire substrate thickness of 430 μm and the size of a 2 inch substrate. Through such comparative experiments, it can be seen that the semiconductor substrate according to the present invention has a relatively small bending property. As described above, a plurality of microcavities and Ga metals formed in a nitride semiconductor layer including a discontinuous hemispherical metal layer are described. This is because the concentration gradient of and the residual Ga metal relaxed the interfacial stress between the substrate and the nitride semiconductor layer.

7 is a process flowchart showing a method of manufacturing a semiconductor substrate according to a modification of the present invention.

Referring to FIG. 7, all processes including substrate surface cleaning (S210), substrate surface treatment (S220), discontinuous hemispherical metal layer formation (S241), and nitride semiconductor layer formation (S242) may be performed in a single process equipment. . For example, using HVPE equipment that can supply various gases by connecting a single or multiple gas lines to a single chamber, substrate surface cleaning (S210), substrate surface treatment (S220), and discontinuous hemispherical metal layers are formed in a single chamber. (S241) and nitride semiconductor layer formation (S242) can proceed continuously. Therefore, the problem of increase in manufacturing time and contamination of the substrate that occur in the process of moving the substrate to the plurality of chambers does not occur.

On the other hand, the semiconductor substrate according to the present invention can be used for the manufacture of various semiconductor devices. Hereinafter, as an example of such a possibility, a semiconductor device in which various electronic devices are formed on the semiconductor substrate described above will be described. In this case, a description overlapping with the above-described embodiment will be omitted or briefly described.

8 is a cross-sectional view of a semiconductor device having a semiconductor substrate according to the present invention.

Referring to FIG. 8, the semiconductor device may include a substrate 410, a nitride semiconductor layer 420 including a discontinuous hemispherical metal layer formed on the substrate 410, and a nitride semiconductor layer 420 including the discontinuous hemispherical metal layer. And an element layer 430 formed on it. In the semiconductor device, at least one light emitting device L may be provided in the device layer 430 to convert electrical energy into light energy.

As described above, the substrate 410 may be an SOI substrate or a single crystal semiconductor wafer having a single crystal semiconductor layer. For example, this embodiment uses a sapphire substrate.

The nitride semiconductor layer 420 including the discontinuous hemispherical metal layer is formed on the surface-treated substrate 410 with a Group 3 metal having a hemispherical metal layer having a size of approximately 0.1 to 5 μm, and then a single layer or the whole structure including the hemispherical metal layer. The nitride semiconductor layer of multiple layers was formed in thickness of about 5 micrometers or more. As described above, a plurality of fine cavities are formed in the nitride semiconductor layer 420 including the discontinuous hemispherical metal layer, and the concentration gradient of the Ga metal, which is the hemispherical metal layer, and the residual Ga metal interface between the substrate 410 and the nitride semiconductor layer. By relieving the stress, the substrate 410 has less warpage.

At least one light emitting device L is provided in the electronic device layer 430. The light emitting device L may include a semiconductor layer including an n-type layer 431, an active layer 432, and a p-type layer 433 stacked on a nitride semiconductor layer 420 including a discontinuous hemispherical metal layer of a substrate 410. And a first electrode 434 formed in a portion of the n-type layer 431 and a second electrode 435 formed in a portion of the p-type layer 433.

The n-type layer 431, the active layer 432, and the p-type layer 433 may be formed of a semiconductor thin film including at least one of Si, GaN, AlN, InGaN, AlGaN, and AlInGaN. On the other hand, for example, in the present embodiment, the n-type layer 431 and the p-type layer 433 are formed of a GaN thin film, and the active layer 432 is formed of an InGaN thin film. The n-type layer 431 is a layer providing electrons, and may be formed by injecting an n-type dopant, for example, Si, Ge, Se, Te, C, or the like into the semiconductor thin film. The p-type layer 433 is a layer for providing holes, and may be formed by implanting a p-type dopant, for example, Mg, Zn, Be, Ca, Sr, or Ba into the semiconductor thin film. The active layer 432 is a layer for outputting light having a predetermined wavelength while the electrons provided in the n-type layer 431 and the holes provided in the p-type layer 433 are recombined to form a well layer and a barrier layer. By alternately stacking may be formed as a multi-layered semiconductor thin film having a single quantum well structure or multiple quantum well structure. Since the wavelength of light to be output varies according to the semiconductor material constituting the active layer 432, it is preferable to select an appropriate semiconductor material according to the target output wavelength.

In the semiconductor device, the device layer 430 including the light emitting device L is formed on the nitride semiconductor layer 420 including the discontinuous hemispherical metal layer. The nitride semiconductor layer 420 including the discontinuous hemispherical metal layer may be formed. Since the interlayer stress between the substrate 510 and the device layer 430 is relieved, deformation of the substrate 410, in particular, warpage is less likely in the process of forming the device layer 430 on the substrate 410. Therefore, since the substrate is easily handled, such as substrate chucking and substrate alignment in a subsequent process, there is no problem in yield reduction and defect increase as in the prior art.

Meanwhile, the above-described semiconductor device forms a transistor, a solar cell, or a light emitting device on a substrate on which a nitride semiconductor layer including a discontinuous hemispherical metal layer is formed, but the present invention is not limited thereto. For example, a MOSFET, a Schottky diode, a photo sensor, or the like may be formed.

As mentioned above, although this invention was demonstrated with reference to the above-mentioned Example and an accompanying drawing, this invention is not limited to this, It is limited by the following claims. Therefore, it will be apparent to those skilled in the art that the present invention may be variously modified and modified without departing from the technical spirit of the following claims.

1 is a cross-sectional view showing a nitride light emitting device according to the prior art.

2 is a process flowchart of a semiconductor substrate according to an embodiment of the present invention.

3A through 3C are cross-sectional views illustrating a process of manufacturing a semiconductor substrate in accordance with an embodiment of the present invention.

4A and 4B are SEM plan and cross-sectional photographs of a hemispherical metal layer according to an embodiment of the present invention.

5A and 5B are SEM plan and cross-sectional photographs of a nitride semiconductor layer according to an embodiment of the present invention.

6A is a graph for explaining bending characteristics of a semiconductor substrate according to an experimental example of the present invention.

6B is a graph for explaining bending characteristics of a semiconductor substrate according to a comparative example of the present invention.

7 is a process flowchart of a semiconductor substrate according to a modification of the present invention.

8 is a cross-sectional view of a semiconductor device having a semiconductor substrate according to the present invention.

<Explanation of symbols for the main parts of the drawings>

301, 410 substrate 302 hemispherical metal layer

303: nitride semiconductor layer 305: cavity

420: nitride semiconductor layer including discontinuous hemispherical metal layer

Claims (23)

Board; A hemispherical metal layer formed discontinuously on the substrate; And A semiconductor layer formed on the hemispherical metal layer; A semiconductor substrate comprising a. The method according to claim 1, The semispherical metal layer includes a Group 3 metal, and the semiconductor layer includes a nitride of the Group 3 metal. The method according to claim 2, The group 3 metal includes at least one of gallium (Ga) and indium (In). The method according to claim 1, The discontinuous hemispherical metal layer has a diameter in the range of 0.1 to 5μm. The method according to any one of claims 1 to 4, The semiconductor layer includes a plurality of cavities formed at the interface with the substrate. The method according to any one of claims 1 to 4, The semiconductor layer has a concentration gradient in which the density of the metal is lowered in the thickness direction. Board; A hemispherical metal layer formed discontinuously on the substrate; And A semiconductor layer formed on the hemispherical metal layer; Including, The semiconductor layer has a concentration gradient in which the metal density decreases in the thickness direction by the hemispherical metal layer. And a final bending property of 70 μm or less when the total thickness of the hemispherical metal film and the semiconductor layer is 5 to 100 μm under the condition that the size of the substrate is 2 inches and the thickness is 430 μm. The method according to claim 7, The semispherical metal layer includes a Group 3 metal, and the semiconductor layer includes a nitride of the Group 3 metal. The method according to claim 8, The group 3 metal includes at least one of gallium (Ga) and indium (In). The method according to any one of claims 7 to 9, The semiconductor layer includes a plurality of cavities formed at the interface with the substrate. Preparing a substrate; Forming a discontinuous hemispherical metal layer on the substrate; And Forming a semiconductor layer on the entire structure including the hemispherical metal layer; Method for manufacturing a semiconductor substrate comprising a. The method according to claim 11, The semispherical metal layer includes a Group 3 metal, and the semiconductor layer comprises a nitride of the Group 3 metal. The method according to claim 12, The group 3 metal includes at least one of gallium (Ga) and indium (In). The method according to claim 11, The hemispherical metal layer has a diameter in the range of 0.1 to 5μm manufacturing method of a semiconductor substrate. The method according to claim 11, The step of forming a hemispherical metal layer is carried out at a temperature above the melting point of the metal or at a temperature of 450 degrees or less.        The method according to claim 11, The semispherical metal layer forming step and the semiconductor layer forming step are repeated at least one or more times. The method according to claim 11, After at least one of the substrate preparing step, the hemispherical metal layer forming step and the semiconductor layer forming step, Cleaning the surface of the substrate; And Treating the surface of the substrate; The method of manufacturing a semiconductor substrate further comprising at least one step. The method according to claim 11, The semispherical metal layer forming step and the semiconductor layer forming step are performed in a different chamber. The method according to claim 18, The hemispherical metal layer forming step is performed by any one of sputtering, E-Beam and MBE, The semiconductor layer forming step is a method of manufacturing a semiconductor substrate is carried out by any one method of MOCVD, HVPE and MBE. The method according to claim 11, The semispherical metal layer forming step and the semiconductor layer forming step are performed in the same chamber. The method of claim 20, The semispherical metal layer forming step and the semiconductor layer forming step is performed by the HVPE method. The method according to any one of claims 11 to 21, And the semiconductor layer comprises a plurality of cavities formed at an interface with the substrate. The method according to any one of claims 11 to 21, The semiconductor layer has a concentration gradient in which the density of the metal is lowered in the thickness direction.

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