KR20090104643A - Semiconductor device and method thereof - Google Patents

Abstract

PURPOSE: A semiconductor device and a method thereof are provided to implement a memory device having a high endurance characteristic. CONSTITUTION: A semiconductor device includes a recording layer, a first electrode, and a second electrode. The recording layer records information by changing electric resistance installed on a base, and the first electrode is installed on one side of the base at the recording layer. The second electrode is installed at the other side facing with the one side of the recording layer. The recording layer is composed of the first layer and the second layer.

Description

Semiconductor device and method for manufacturing same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a memory cell using a solid electrolyte material for discriminating memory information by using a difference in resistance, for example, a high density integrated memory circuit, or a memory circuit and a logic circuit. The present invention relates to an effective technique applied to a logic mixed memory installed on the same semiconductor substrate or a semiconductor integrated circuit device having an analog circuit, and also to a high speed and nonvolatile random access memory operating at a low voltage. random access memory).

As a recording technique using a solid electrolyte material, a solid electrolyte memory has been proposed. Non-Patent Documents 1 and 2 describe the details of the solid electrolyte memory. The memory section of the memory and its structure will be described with reference to FIG. The solid electrolyte memory has a structure in which the memory portion RM is sandwiched between the BC and the upper electrode 15. The storage section RM has a laminated structure of the solid electrolyte layer 21 and the electrode 22 serving as an ion supply source. Ions with high mobility move in the solid electrolyte layer 21. "High mobility ions" are defined as ions that move in a long distance when a certain voltage is applied in a certain electrolyte. The material of the electrode 22 is element A (for example, Cu) having high mobility.

The material of the solid electrolyte layer 21 is, for example, an alloy having a composition of Cu and S, and the solid electrolyte layer 21 contains ions A. The VEC is formed by laminating the plug material 13 and the adhesion layer 14 having low ion conductivity. The upper electrode 15 uses a metal material with low mobility. This prevents movement when an electric field is applied. In the " ON state " in which the memory portion RM has a low resistance, an electrically conductive filament formed by the metal A in the solid electrolyte is connected between the electrode 22 and the EC.

On the other hand, the electrically conductive filament is cut | disconnected in the "OFF state" with high resistance of the memory | storage part RM. The operation method is described below. The reading of a value measures the resistance of the memory | storage part RM, and associates the height with "0" and "1", respectively. The 'ON operation' which sets the storage unit RM to the 'ON state' is performed as follows. By applying a positive voltage to the electrode 22, the electrode 22 is oxidized to be ion A. Thereafter, the ion A ion-conducts in the solid electrolyte and is reduced in the vicinity of the lower electrode (VEC) or the filament, whereby a filament is produced or grown. The filament connects between the electrodes 22 and VEC, whereby the storage portion RM becomes a low resistance. The " OFF operation " which sets the storage unit RM to the " OFF state " is performed as follows. By applying a negative voltage to the electrode A, the metal A constituting the filament is oxidized to be ion A. Thereafter, ions A diffuse into the solid electrolyte.

Moreover, the non-patent document 3 reports the crystal structure which consists of Cu, TA, and O, and whose composition ratio is close to Cu-Ta-O = 1: 2: 6. Hereinafter, the crystal is referred to as Cu-Ta-O crystal.

Patent document 1 describes a semiconductor memory using an oxide material. Forming or dissipating the metal filament causes a change in resistance. In the semiconductor memory of Patent Literature 1, the place where the metal filament is produced and destroyed is not in the oxide material.

In addition, Patent Document 2 describes a semiconductor memory having a structure in which a stack of Cu (the Tellurium compound and Gadolinium oxide) is sandwiched between two electrodes, for example. A method of improving the breakdown voltage of a memory layer by adding a metal element (for example, Cu) is described.

[Patent Document 1] US 6,891,186

[Patent Document 2] Japanese Unexamined Patent Publication No. 2006-351780

[Non-Patent Document 1] T. Sakamoto, S. Kaeriyama, H. Sunamura, M. Mizuno, H. Kawaura, T. Hasegawa, K. Terabe, T. Nakayama, M. Aono, IEEE International Solid-State Circuits Conference (ISSCC) 2004, "Digest, ( US issuing country ), 2004, page number 16.3

[Non-Patent Document 2] MN Kozicki, C. Gopalan, M. Balakrishnan, M. Park, M. Mitkova, Proc. Non-Volatile Memory Technology Symposium (NVMTS) 2004, ”(Publishing United States ), 2004, Page No. 10-17

[Non-Patent Document 3] Journal of applied physics, Vol. 96, p. 4400-4404

The solid electrolyte memory has a problem that stable rewriting is difficult because the amount of ions A and the shape of the electrode in the solid electrolyte are changed by repeating rewriting. To solve this problem, a representative structure of the circuit device under consideration will be described with reference to FIG. 3. The supply layer of ion A was electrode A in the conventional solid electrolyte memory, but was used as the solid electrolyte material in this memory. For example, Cu-Ta-S. Hereinafter, the cu-Ta-S will be described as an example. In addition, a filament formation part was made into the ternary oxide. For example, Cu-Ta-O. Hereinafter, a description will be given taking Cu-Ta-O as an example. In the following, the filament forming portion is referred to as an ion confinement layer. The effect obtained by setting it as this structure is described below. The first point is to limit the total amount of ions that can be supplied by changing the ion source from the electrode A to the solid electrolyte Cu-Ta-S, and also to suppress physical changes such as the generation of voids in the ion source. A 2nd point is to use Cu and TA which differ in mobility as metal ion. TA having low mobility creates a stable structure of TA and TA. On the other hand, Cu having high mobility produces a change in the resistance of the memory portion RM by generating and extinguishing the electrically conductive filaments.

First, the ON operation will be described with reference to FIG. 3. By applying a voltage higher than the lower electrode 34 to the upper electrode 31, the cu ion 33 having a positive charge in the Cu supply layer, which is a solid charge quality, is ion-conducted, and the ion confinement layer 11 Go to). For simplicity, in the following description, it is assumed that a positive voltage is applied to the upper electrode, and the lower electrode is maintained at OＶ. In the ion confinement layer 11, the cu ion 33 becomes the metal Cu 34 by a reduction reaction. The metal Cu 34 is produced in a portion in which the current of the ion confinement layer 11 flows in particular. In addition, when the metal Cu 34 is generated, the resistance of the portion drops, and current is concentrated. Therefore, the metal Cu 34 often has a filament shape. By the formation of the cu filament, the resistance of the storage unit RM decreases.

Next, the OFF operation will be described with reference to FIG. 4. By applying a negative voltage to the upper electrode 32 and keeping the lower electrode 34 at 0 kV, the metal Cu 34 in the cu filament is oxidized to become Cu ion. As a result, a part of Cu filament is extinguished, and the memory | storage part RM becomes high resistance. Cu ion moves to the Cu supply layer 12 by ion conduction.

The above explanation will be described once again using the current-voltage waveform shown in FIG. This waveform was measured using a semiconductor parametric analyzer. By applying the upper electrode voltage at about 0.3 kW, the ON operation 51 occurs and the resistance decreases. When the voltage was applied about 0.5 mA, the current showed a constant value of 300 micro amps, because the compliance current of the measuring instrument was reached. Next, by applying a voltage of about -0.3 kV to the upper electrode voltage, the OFF operation 52 occurs and the resistance rises. Each of the above explanations holds true even if the polarity of the voltage during operation is reversed. Further, this is true even if the vertical relationship between the ion confinement layer and the ion supply layer is reversed. As described above, we are examining this circuit device for the purpose of high reliability operation. However, in some applications such as DRAM (dynamic access memory) for high reliability applications, more reliable operation is required.

The technical problem to be solved by the present invention is to improve the problems of the above technology, and to provide a circuit device such as a memory device having high reliability. Specifically, the increase in the number of endurances and the variation in the rewrite voltage and the rewrite resistance are reduced.

MEANS TO SOLVE THE PROBLEM In order to achieve the said subject, this invention provides the semiconductor device whose phase state of the ion confinement layer of memory | storage part RM is a crystal | crystallization. In particular, the ion confinement layer in the crystalline state has a composition of ions C having low mobility compared to ions A and ions A having high mobility, and ions D having polarities opposite to ions A and ions C. An example of the composition of the ion confinement layer in the crystalline state is Cu-Ta-O = 1: 2: 6. Since the crystallized ion confinement layer is stable, physical deformation of the storage unit RM and excessive variation of the composition ratio in the storage unit when the rewrite operation is performed are unlikely to occur. Therefore, stable rewrite operation is possible.

Among the inventions disclosed herein, the effects obtained by the representative ones are briefly described as follows. A memory device having high endurance characteristics can be realized.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in detail based on drawing. In this application, the contact between the conductor layers includes not only the case of direct contact but also the case of contact between layers or regions such as an insulator or a semiconductor thin enough to flow a current.

Example 1

1 is a cross-sectional view showing the configuration of a memory element using the solid electrolyte material according to the first embodiment according to the present invention. As shown in the figure, the memory device of the present invention has a structure in which a storage unit (RM) in which an ion confinement layer (11) and an ion supply layer (12) are stacked is sandwiched between a lower electrode (EC) and an upper electrode (15). Consists of The lower electrode VEC is constituted by the adhesion layer 14 and the plug material 13. As the adhesive layer 14, for example, TiN having excellent embedding properties into a hole shape having a small dimension can be used. As a material of the plug material 13 and the upper electrode 15, a low electric resistance can be used. As the material of the VEC, TIAION, TIi, TISiC, TA, and carbon clusters (carbon allotropes such as C60) that are high melting point materials can be used. In this case, as a method of dissipating the electrically conductive filaments, a method of generating joule heat in the ion confinement layer and dissipating the filaments by thermal diffusion can be used. As a result, the voltage of the same polarity can be used in the ON operation and the OFF operation, and the area of the peripheral circuit can be reduced.

The material of the plug material 13, the adhesion layer 14, and the upper electrode 15 is preferably made of an element having low mobility so as not to affect the rewriting operation. It goes without saying that the same material, for example, TiN, can be used for the plug material 13 and the adhesion layer 14. The phase state of the ion confinement layer 11 is crystal | crystallization, and the composition which consists of Cu, TA, and O can be used as a material. The ion confinement layer 11 consists of a cation and an anion. As a cation, it consists of two or more types of cations and anions which differ in mobility. The cation with high mobility is an ion with few valences and a small ion radius, which corresponds to Ag, Cu, Au, or Vin. Moreover, the cation with low mobility is an ion with a large valence and a large ion radius, and it corresponds to Ta, Ｗ, MO, and a rare earth element (particularly Ｇd). As the material of the ion supply layer 12, a composition composed of Cu and TA and S can be used. The ion supply layer consists of a cation and an anion. In addition, by using two or more kinds of cations having different mobility as the cations, the stable structure formed by the cations and the anions having the low mobility can prevent the ion supply layer from physical changes such as voids or excessive resistance changes.

In addition, by making the anion of the ion confinement layer 11 different from the anion of the ion supply layer 12, the ion conductivity of the ion confinement layer 11 and the ion supply layer 12 is different, resulting in a gradient of ion concentration. Can be kept in one direction. The ion concentration is high in the vicinity of the upper electrode 15 and low in the vicinity of the lower electrode VEC. If the gradient of the ion concentration is reversed, the polarity of the rewrite voltage is reversed, so that a stable rewrite operation cannot be performed. In this embodiment, an object of the present invention is to maintain a gradient of ion concentration by varying ion conductivity.

In the present invention, the phase state of the ion confinement layer 11 is characterized as a crystal. 6, the crystal structure in the case where Cu, Ta, and O are used as the composition of the ion confinement layer and the composition ratio is close to Cu-Ta-O = 1: 2: 6 will be described. The crystal structure consists of a slight modification of the perovskite structure. Oxygen is located at the apex of the octahedron, and TA is located at the center. Note that the Cu site shown in Fig. 6 and the Cu site indicated by the public, half of the Cu site are public. On the other hand, there is a report that the ratio of the public in the CU site is 1/3. In addition, there is a report that the composition ratio is Cu-Ta-O = 1.03: 2: 6. Many of the pores included in the Cu site have a high ion conductivity because they become a path when the Cu ion moves. On the other hand, the structure composed of TA and O is stable, and even when an electric field is applied or a Cu ion is moved, the structure does not easily deteriorate, voids are generated, or TA or O moves. I think there is little work. This is because cations with low mobility generally have a lot of valences, and thus form a strong bond with oxygen as an anion. Therefore, it is possible to provide a memory element having high reliability.

As for the preferable composition of an ion supply layer, an average composition is represented by following General formula (1).

_{Cu X Ta Y S (100-} X-Y) (1)

(Wherein, Ｘ and 중의 in the formula are 40≤Ｘ≤80, 5≤Ｙ≤20, respectively)

If the composition ratio of Cu is higher than this, the resistance itself is lowered like the electrode, and thus it does not function as a solid electrolyte. If less than this, the film becomes chemically unstable, and the set becomes insufficient. If the composition ratio of TA is greater than this, the set resistance is excessively high. When less than this, since a space | gap arises when an ion moves, the rewritable frequency | count is reduced. In addition to this, another element of 10 atomic% or less may be included.

As for the preferable composition of an ion confinement layer, an average composition is represented by following General formula (2).

_{Cu X Ta Y O (100-} X-Y) (2)

(Wherein, 중의 and 중의 in the formula are respectively 10≤Ｘ≤50, 10≤Ｙ≤30)

If the composition ratio of Cu is higher than this, the resistance itself is lowered like the electrode, and thus it does not function as a solid electrolyte. If less than this, the chemical stability becomes unstable, and the set becomes insufficient. If the composition ratio of TA is larger than this, the set resistance is too high. If less than this, the heat resistance of a low resistance state is lacking. If there is more oxygen, the set is insufficient. When less than this, since a space | gap arises when an ion moves, the rewritable frequency | count is reduced. In addition to this, another element of 10 atomic% or less may be included.

Fig. 7 and Fig. 8 show a comparison between the case where the phase state of the ion confinement layer in our experiment was made amorphous and the case where it was crystallized. In Fig. 7, the phase state is determined, and Fig. 8 is amorphous. The amount of current flowing when the read operation is performed is shown. It is shown that the stability of the read current when the rewriting operation is repeated by making the phase state a crystal is shown. From this, it is proved that by setting Cu-Ta-O as the crystal, a memory of high reliability operation can be provided. One model for explaining this reason is as follows. If Cu-Ta-O is amorphous, the bonding force between the ions varies from place to place. An unstable bond exists in the center, and the bond between Ta-O is broken by applying an electric field or by moving the Cu ion. When the bond of the cut | disconnected TA-O reaches a predetermined ratio, an air gap arises by electro-migration. As a result, the ON resistance, the OFF resistance, and the operating voltage change. In the case where Cu-Ta-O is the crystal, a model in which the Cu ion is moved around the Cu site in the Cu-Ta-O and a model that moves around the grain boundary can be considered. In the model which moves around Cusite in Cu-Ta-O, the binding force between ions is substantially constant at least in a mouth, and the place where the binding force which a void | gap can generate | occur | produce is weak is not produced. Therefore, the possibility that a stable rewriting operation is possible can be considered. In the model where the Cu ion moves the grain boundary, it is conceivable that the stable rewriting operation is possible since the grain boundary is almost stable.

Next, the crystal | crystallized Cu-TA-O which we created, and the cross-sectional SEM image of the peripheral part is shown in FIG. Observation by SEM revealed that a structure of about 5 nm exists in the crystal Cu-Ta-O 91. This suggests that the grain size of the crystal Cu-Ta-O 91 is about 5 nm. In addition, FIG. 9 shows the Cu-Ta-S 92, the upper electrode 94, and the PETOS 93.

Moreover, the schematic diagram of FIG. 9 is shown in FIG. The crystal Cu-Ta-O 104 is positioned between the silicon oxide 103 and the ion supply layer, that is, Cu-Ta-S. It is shown by the shape of the crystal grain boundary 101 that the grain size of Cu-Ta-O is about 5 nm. In the mouth 102 and the grain boundary 101, the electrical conductivity and the mobility of Cu are different. When the particle diameter is sufficiently small compared to the diameter of the lower electrode, the effect of the Cu-Ta-O grain boundary on the memory characteristics is averaged, and the variation between the elements is reduced. It is easy to think that it is possible to precipitate Cu, Ta, and its oxide at the grain boundary 101 by the composition of Cu-Ta-O and the crystallization conditions. By the magnitude and the composition of the amount of precipitation, it is considered that it is possible to determine whether the shift of Cu mainly occurs in the mouth or at the grain boundary. By reducing the variation between the devices, a large memory can be provided. In addition, the high reliability operation enables application to RAM, which requires a high number of rewritable times. In particular, it is possible to provide the present memory device as a main memory device corresponding to the miniaturization smaller than 45 nm, instead of DRAM having a large market as a computer main memory device but having a problem of miniaturization smaller than the process generation 45 nm.

The crystallization condition of Cu-Ta-O is demonstrated using FIG. First, amorphous Cu-Ta-O was formed into a film by the sputtering method. Next, heat processing for 30 minutes was performed in nitrogen atmosphere at predetermined temperature, respectively. As a result of performing the QR measurement of this sample, the Cu-Ta-O crystal was not observed at the asdepo film and the heat treatment temperature of 500 ° C or lower. On the other hand, Cu-Ta-O crystal | crystallization was observed by performing 700 degreeC heat processing.

In addition, we are conducting an experiment to investigate the electrical resistance of Cu-Ta-O, but it is known that the crystallization temperature of Cu-Ta-O used in the experiment is 500 ° C or more and 700 ° C or less. The film thickness of Cu-Ta-O is 5 to 60 nm, for example, and the film thickness of Cu-Ta-S is 3 to 30 nm, for example.

We perform cross-sectional TEM (transmission electron microscope) observation of the test-made memory cell, and the electron diffraction figure obtained by the nano-deflection method is shown in FIG. Also shows the calculation results of the diffraction pattern from a CuTa ₂ O ₆ crystal structure in Fig. By the agreement of the results in FIG. 25 and FIG. 26, it is found that the Cu ₂ O ₆ crystal exists in the memory cell. As described above, it is possible to easily check whether the ion confinement layer is crystallized by the cross-sectional TEM observation.

The vertical relationship between Cu-Ta-O and Cu-Ta-S is described below. When the Cu-Ta-O film is formed, the Cu-Ta-O is crystallized, and then the Cu-Ta-S film is formed, the heat resistance of the Cu-Ta-S crystallizes the Cu-Ta-O. Since it may be lower than temperature, a Cu-Ta-S material can be selected from a wide composition. For example, the composition of Cu: Ta: S = 60: 10: 30 which sublimes by applying the heat load of 600 degreeC can be used. As the composition ratio of Cu-Ta-S, for example, if the Cu concentration is 10% or more and 50% or less, and the TA concentration is 10% or more and 30% or less, the amount of Cu supplied is sufficient to change the resistance. Although it is thought that it is suitable for suppressing the space | gap of the Cu-Ta-S material at the time of supplying, of course, it is also possible to use other compositions. Next, the manufacturing process of this memory is demonstrated using FIG.

First, an MIS transistor is formed and a diffusion layer is separated by a field oxide film using a normal semiconductor process. Next, after the interlayer insulating film is formed, a contact hole connected to the drain of the transistor is formed, and the adhesion layer 14 and the plug material 13 are formed by chemical vapor deposition (CHD). Thereafter, CMP (chemical mechanical polishing) is performed to form VEC. In addition, film formation of the crystal Cu-Ta-O is performed. The schematic diagram of the structure obtained as a result is shown in FIG. Only the top from the VEC is shown. Plasma Tetra Ethyle Ortho Silicate (PETOS) may be used as the interlayer insulating film 121.

Three types of film formation methods of the crystal Cu-Ta-O are shown in FIG. In the present Example, Cu-Ta-O film-forming by the base heating spattering method was selected. The method performs sputtering by controlling the wafer base temperature to, for example, 500 ° C. or higher. Of course, it is possible to use materials other than Cu-Ta-O crystals as the ion confinement layer, and since the crystallization temperature varies depending on the composition, it is necessary to select an appropriate base temperature according to the composition.

The sputtered particles incident on the substrate by sputtering have a high kinetic energy and can move freely to a certain extent on the substrate, so that they tend to be in a thermodynamically stable crystal state. Therefore, compared with the case where it forms into an amorphous state first and heat loads after that, the temperature required for crystallization can be made low temperature. As a result, since the dopant injected into the silicon base is moved by a high thermal load, the problem of deterioration of transistor characteristics can be avoided.

Next, the processing method of Cu-Ta-O and Cu-Ta-S is demonstrated. In general, the material containing Cu is difficult to be micromachined by etching. For example, a damascene process is used in the wiring process of Cu. The processing method of this embodiment will be described using FIGS. 14 to 16.

FIG. 14 shows a schematic view of coating, exposing and developing the resist 142 after further forming the Cu-Ta-S, the upper electrode 15, and the hard mask 141 from the state shown in FIG. 12. As the hard mask 141, SiN (silicon nitride) can be used. The film thickness of the hard mask 141 is 150 nm, for example. The film thickness is appropriately selected in accordance with the process generation of the manufacturing apparatus or the film thicknesses of Cu-Ta-S and Cu-Ta-O. Using the resist 142 as a mask, the hard mask 141 is processed by dry etching. Thereafter, resist ashing is performed to remove the resist 142. The schematic diagram of this state is shown in FIG.

In addition, using the hard mask 141, the processing of Cu-Ta-S and Cu-Ta-O is performed by dry etching. Since the hard mask 141 can take a large selection ratio of Cu-Ta-O and Cu-Ta-S as compared with the resist 142, finer processing is possible.

Hereinafter, the connection portion of the storage portion RM and the bit line or the connection portion of the source and source line of the MSI transistor is formed, and the upper wiring is formed sequentially. 17 to 19 show the layout of the memory cells formed by the above procedure. In FIG. 17, the diffusion layer 171, the VEC 172, and the connection portion 173 between the source line and the diffusion layer are illustrated.

Next, the word line 181 and the source line 182 are shown in FIG. The source line spacing is 3 F when F is the minimum dimension. The word line spacing is 2F. 19, the bit line 191 is shown. The bit line spacing is 3F. In this embodiment, the memory cell area can be 6F ² . The plug diameter of the lower electrode VEC is, for example, 0.2 F ² to ² F ² . In the case where the plug diameter of the lower electrode VEC is processed to 1 F ² or less, a method of processing using a step such as a sidewall as a hard mask and the like can be used.

20 and 21 show schematic cross-sectional views of the main part of the embodiment. FIG. 20 is a schematic cross-sectional view of VIII-VIII 'in FIG. 19, and FIG. 21 is a cross-sectional schematic view of VIII-VIII' in FIG. 19. In FIG. 20, the word line 202 is separated from the VEC using the sidewall 201. The diffusion layer 171 is separated by the field oxide film 203.

In FIG. 21, the diffusion layer-source line connecting portion 173 formed of the adhesion layer 214 and the plug material 213 connects the source line 182 and the diffusion layer 171. The adhesion layer 214 is TiN, for example, and the plug material 213 is ZI, for example. Moreover, it can form by CD. The source line 182 is formed of the barrier layer 215 and the wiring material 216. TA may be used as the barrier layer and Cu may be used as the wiring material.

Example 2

This embodiment is characterized in that, among the Cu-Ta-O crystallization method in FIG. 13, crystallization of the ion confinement layer is performed by laser irradiation. The film formation of Cu-Ta-O is performed as follows. The base temperature at the time of sputtering is controlled so low that Cu-Ta-O does not crystallize, and an amorphous Cu-Ta-O is formed. Next, the crystallization of Cu-Ta-O using laser irradiation is performed.

By performing laser irradiation instead of the heat treatment using a furnace body, temperature rise based on a silicon wafer can be reduced. As a result, since the dopant in the diffusion layer moves, not only the problem of deteriorating transistor characteristics can be avoided, but also the degradation of the low-k material can be prevented. ) Material can be used as an interlayer insulating film. By using the low-k material, it is possible to reduce the wiring delay of the semiconductor circuit and to perform high speed operation. Low-k materials are generally low in heat resistance. For example, when a porous low-k material is subjected to a heat load exceeding 400 ° C., the internal micro voids disappear and the dielectric constant k increases, so that the wiring delay is increased or the low-k is low-k. ) Deformation of the material may cause a wiring short. It goes without saying that the temperature at which the low-k material deteriorates varies depending on the type of the low-k material.

The laser irradiation method is explained. The wafer is rotated about an axis perpendicular to the silicon wafer surface and passing through the wafer center, and the laser irradiation part is moved in the radial direction of the wafer. Moreover, the rotational speed is changed by the position of the laser irradiation part, and the linear speed of the laser is kept constant. By this, laser heat treatment at a uniform irradiation intensity is possible.

The refractive index of Cu-Ta-O in the amorphous state measured by us was 3.9 at a wavelength of 632.8 nm. Crystallization is considered possible by setting the laser irradiation intensity to 16 kW / mm ² , the moving speed of the laser irradiation part to 25 mm / sec, and the irradiation length of the laser moving direction to 1 μm, but the composition of the Cu-Ta-O material Since the refractive index, the crystallization temperature, and the time required for crystallization change, needless to say, control the irradiation intensity or the moving speed of the irradiation section to an optimum value.

Moreover, it becomes possible to crystallize by selectively heating Cu-Ta-O by laser irradiation, and to suppress the temperature rise of Cu-Ta-S formed in the lower part. As a result, it is possible to form a structure in which Cu-Ta-S is lower than Cu-Ta-O by using Cu-Ta-S having lower heat resistance than the crystallization temperature of Cu-Ta-O.

Example 3

In the Cu-Ta-O crystallization method of FIG. 13, the present embodiment is characterized by crystallizing Cu-Ta-O by performing heat treatment in an electric furnace or an infrared furnace after amorphous Cu-Ta-O film formation. It is done. Since crystallization takes place over time, the rate of crystal growth can be suppressed and the probability of crystal nucleation can be relatively increased, whereby a fine crystal structure is obtained. As a result, the number of grain boundaries on the VEC can be made uniform, and the influence of grain boundaries on the rewriting operation can be averaged. As a result, a semiconductor circuit device with less variation can be provided. The heat treatment time is 30 minutes, for example. As described in Example 1, the crystallization temperature of Cu-Ta-O is 600 ° C or higher, so the heat treatment temperature is preferably 600 ° C or higher.

Example 4

This embodiment is characterized in that the memory section is separated by CPM. The manufacturing process of this memory will be described with reference to FIGS. 22 to 24. First, an MIS transistor is formed and a diffusion layer is separated by a field oxide film using a normal semiconductor process. Next, after the interlayer insulating film is formed, contact holes connected to the drain and the source of the transistor are formed, and the adhesion layer 225 and the plug material 224 are formed by chemical vapor deposition (CHD). Thereafter, CMP (chemical mechanical polishing) is performed to form a connection portion between the diffusion layer-1 metal wires. Next, one metal wire 223 is formed by using the CD film forming and damascene processing. An example of one metal wire material is Ｗ. Thereafter, the etching stopper layer 221 and the interlayer insulating film 226 are formed, and further, the CDD and dry etching are performed to form the stepped portion 222. An example of the material of the etching stopper layer is SiN, and an example of the material of the interlayer insulating film 226 is PET. In addition, an example of the material of the step part 222 is SiN. The schematic diagram of the cross section obtained as a result is shown in FIG.

In addition, the ion confinement layer 11, the ion supply layer 12, and the upper electrode 15 are formed. All these film formation can be performed by the sputtering method. However, when using the deep hole whose height ratio of a step part and the aspect ratio of an opening part exceeds 1, each layer is formed using a CBD method. The schematic diagram of the cross section obtained as a result is shown in FIG.

Next, by performing CMP, a structure in which the storage unit shown in FIG. 24 is separated can be formed. By using this embodiment, it is possible to form a particularly fine memory cell structure.

Thereafter, the upper wiring is formed to manufacture a memory device. On the other hand, when the present structure is formed using a general semiconductor process, a step of 10 to 500 nm occurs in Cu-Ta-O or Cu-Ta-S. On the other hand, in the present embodiment, the source line is disposed under the bit line, and the source line is wired using one metal line 223. Further, the dry etching spatter layer 221 is formed so that the connection portion between the one metal wire and the upper wiring can be easily formed.

1 is a sectional view of principal parts of a memory device in one embodiment of the present invention.

2 is a sectional view of principal parts of a solid electrolyte memory device.

It is a schematic diagram which shows ON operation in one Embodiment of this invention.

It is a schematic diagram which shows the OFF operation in one Embodiment of this invention.

5 is a diagram illustrating a relationship between current and voltage.

Fig. 6 is a view showing the Cuta ₂ O ₆ crystal structure.

FIG. 7 is a diagram showing the relationship between the cycle count and the readout current when the ion confinement layer is a crystal. FIG.

Fig. 8 is a diagram showing the relationship between the cycle number and the read current when the ion confinement layer is amorphous.

Fig. 9 is a cross-sectional SEM photograph of the crystal Cu-Ta-O periphery.

10 is a schematic sectional view of the vicinity of the crystal Cu-Ta-O.

It is a figure which shows the CRD measurement result of Cu-Ta-O.

12 is a cross-sectional view schematically showing a structural example of a main part in the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

Fig. 13 is a view showing the crystallization method of three kinds of ion confinement layers.

FIG. 14 is a cross-sectional view schematically illustrating a semiconductor device during a manufacturing step following FIG. 12.

FIG. 15 is a cross-sectional view schematically showing a semiconductor device during a manufacturing step following FIG. 14; FIG.

FIG. 16 is a cross-sectional view schematically illustrating a semiconductor device during a manufacturing step following FIG. 15.

FIG. 17 is a diagram schematically showing a layout of main parts in a manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG.

FIG. 18 is a diagram schematically showing a layout of main parts in a manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG.

FIG. 19 is a diagram schematically showing a layout of main parts in a manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG.

20 is a cross-sectional view schematically showing the main parts of the manufacturing process in the semiconductor device according to the first embodiment of the present invention.

Fig. 21 is a cross-sectional view schematically showing the main parts of the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

Fig. 22 is a cross-sectional view schematically showing the main parts of the manufacturing process of the semiconductor device according to the fourth embodiment of the present invention.

FIG. 23 is a cross-sectional view schematically illustrating a semiconductor device during a manufacturing step following FIG. 22.

FIG. 24 is a cross-sectional view schematically illustrating a semiconductor device during a manufacturing step following FIG. 23.

Fig. 25 is a diffraction diagram of Cuta ₂ O ₆ crystals obtained by analyzing memory cells by electron diffraction.

Fig. 26 is an electron diffraction diagram of Cutau ₂ O ₆ crystal obtained by calculation.

[Description of the code]

11... Ion Confinement Layer,

12... Ion Supply Layer,

13, 213, 224. Plug material,

14, 214, 225... Adhesive Layer,

15, 94... Upper electrode,

21... Solid electrolyte layer,

22... An electrode as an ion source,

33... ion,

34... metal,

51... ON operation,

52... OFF operation,

91, 104. Crystal Cuuc-Ta-O,

92... Ｃｕ-Ｔａ-Ｓ,

93, 103... ＴＴＥＯＳ,

101... Grain boundary,

102... Mouth,

103... Silicon oxide,

121... Interlayer insulating film,

141... Hard Mask,

142... Resist,

171... Diffusion Layer,

172... Bottom electrode,

173... Connection between source line and diffusion layer,

181... Word Line,

182... Source Line,

191... Bit line,

201... Sidewall,

202... Word Line,

203... Field oxide,

215... Barrier layer,

216... Wiring Material,

221... Etching stopper layer,

222... Step,

223... 1 metal wire,

RM… Memory,

VEC… Bottom electrode.

Claims (20)

A recording layer for recording information by causing a change in electrical resistance installed on a substrate; A first electrode provided on a main surface of the base side of the recording layer; A second electrode provided on another circumferential surface of the recording layer opposite to the circumferential surface; The recording layer is composed of at least two layers of a first layer disposed on the side in contact with the first electrode and a second layer disposed on the side in contact with the second electrode, The first layer contains at least one element selected from the group consisting of Ag, Cu, Au, and nu, at least one element selected from the group consisting of Ta, Xu, Mo, and Vd, and oxygen. Is a crystalline phase formed by And said second layer comprises at least one element selected from the group consisting of Ag, Cu, Au, and nu, and at least one element selected from the group consisting of S, Se, and Te. The method of claim 1, An element selected from the group consisting of Ag, Cu, Au, and Vin contained in the first layer and the second layer is a common element in each layer. The method of claim 1, The second layer may include at least one element selected from the group consisting of Ag, Cu, Au, and bene, at least one element selected from the group consisting of S, Se, and Te and a metal element or silicon. A semiconductor device characterized by the above-mentioned. The method of claim 3, wherein At least Cu-Ta-S is contained in the said 2nd layer, The semiconductor device characterized by the above-mentioned. The method of claim 4, wherein Wherein the composition ratio of _{Cu-Ta-S, Cu X} Ta Y S (100-X-Y) when called, the X and Y is a semiconductor device, characterized in that, 80≥X≥40, 5≤Y≤20 . The method of claim 1, At least Cu-Ta-O is contained in the said 1st layer, The semiconductor device characterized by the above-mentioned. The method of claim 6, The semiconductor device of the composition ratio of the Cu-Ta-O, characterized in that said X and Y are, 10≤X≤50, 10≤Y≤30 when said _{Cu X Ta Y O (100-} X-Y). The method of claim 1, A semiconductor device, wherein the diameter of the metal particles or the metal compound particles observed in the first layer is 5 nm or less. The method of claim 1, And the first layer has a structure deformed within a range of 10% from an atomic position for determining a perovskite structure or a perovskite structure. A plurality of memory cells comprising a plurality of word lines and an information storage unit provided at an intersection of a plurality of bit lines intersecting the word lines through an insulating layer and selection elements. In a semiconductor memory device, The information storage section has the semiconductor device according to claim 1, And writing information or reading information by applying a pulse voltage to the information storage section. Forming a lower electrode on the base, On the lower electrode, at least one element selected from the group consisting of Ag, Cu, Au, and nu, at least one element selected from the group consisting of Ta, Va, Mo, and Wed, and a first containing oxygen A memory layer is formed, and on the first memory layer, at least one element selected from the group consisting of Ag, Cu, Au, and nu, and at least one element selected from the group consisting of S, Se, and TE. Forming a memory layer comprising at least two layers of the first memory layer and the second memory layer by forming a second memory layer comprising: Forming an upper electrode on the recording layer; Annealing is performed after the formation of the first memory layer, and the second memory layer is formed after the annealing. The method of claim 11, The phase state of the first memory layer is changed from amorphous to crystal by annealing after the formation of the first memory layer. The method of claim 12, And a Cu-Ta-O in the first memory layer, wherein the annealing temperature is 600 ° C. or higher. The method of claim 11, Has a process of forming an interlayer insulating film using a low-k material on the base, A method of manufacturing a semiconductor device, characterized in that the base temperature at the time of annealing is 400 ° C. or less. The method of claim 11, A method of manufacturing a semiconductor device, wherein the first memory layer is formed while the base is heated. The method of claim 15, The heating method of the base is a manufacturing method of a semiconductor device, characterized in that more than 500 ℃. The method of claim 12, After film formation of the first memory layer, annealing using a laser is performed, followed by film formation of the second memory layer. The method of claim 17, Forming an interlayer insulating film using a low-k material on the base; A method of manufacturing a semiconductor device, wherein the base temperature at the time of annealing is 400 ° C. or less. The method of claim 11, And the lower electrode comprises at least one composition selected from the group consisting of Ti, Ti, Ti, TiA, Ni, Ti, Ti, Ti, and carbon clusters. Forming a lower electrode on the base, On the lower electrode, a first storage layer containing at least one element selected from the group consisting of Ag, Cu, Au, and gen, and at least one element selected from the group consisting of S, Se, and Te is formed. Further, on the first memory layer, at least one element selected from the group consisting of Ag, Cu, Au, and vn, at least one element selected from the group consisting of Ta, Va, Mo, and Vd, and oxygen Forming a memory layer comprising at least two layers of the first memory layer and the second memory layer by forming a second memory layer comprising a crystalline phase comprising a; And a step of forming an upper electrode on the recording layer.

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