KR20090101673A - Flash memory system - Google Patents

Abstract

PURPOSE: A flash memory system is provided to perform a program operation stably. CONSTITUTION: A flash memory system(1000) includes a flash memory(100), a controller(200), a pull down driver(101), and a first charging unit(102). The flash memory stores the data. The controller controls the flash memory. The pull down driver inactivates the command latch enable signal provided to the flash memory by the controller while the power is off. The flash memory does not receive the command from the controller in response to the command latch enable signal. The first charging unit supplies the power to the flash memory while the power is off.

Description

Flash memory system {FLASH MEMORY SYSTEM}

The present invention relates to a flash memory system, and more particularly to a flash memory system that can increase the reliability of the operation when sudden power off.

In a nonvolatile memory device, data written in a cell remains undeleted even when power is not supplied. Among nonvolatile memories, flash memory has a function of electrically erasing data of cells collectively, and thus is widely used in computers and memory cards. For example, storage devices such as SSDs, MP3s, digital cameras, camcorders, and the like use flash memory to store information.

Flash memory is divided into NOR type and NAND type according to the connection state of cells and bit lines. In general, NOR-type flash memory is disadvantageous for high integration, but there is an advantage that it can easily cope with high speed. In addition, since the NAND flash memory uses less cell current than the NOR flash memory, there is an advantage in that it is advantageous for high integration. As is well known, memory cells of a NAND flash memory are erased and programmed using F-Nordheim tunneling current. NOR flash memory cells, as is well known, are programmed using a channel hot electron scheme and erased using F-N tunneling current.

In systems using flash memory, power off may occur randomly. For example, the memory card used in the camera may be pulled out by the user during use, and the flash memory used in the SSD may be powered off by a power failure or forcedly powered off by the user. This power off is called sudden power off.

Power off includes normal power off and sudden power off. Normal power off is performed by a power off command. By normal power off, the command is processed normally and after the data is stored, the system is powered off stably. However, sudden power off may not process the command normally. For example, if a power off occurs after an instruction (for example, a program instruction or an erase instruction) occurs but before the processing of the instruction is completed, the instruction processing cannot be completed normally. In addition, even when a command occurs after a sudden power off, processing of the command is not normally performed. When using a multi-level cell flash memory, if sudden power off occurs in the MSB page program after the LSB page program operation is performed, the memory cell is programmed with unwanted data.

To solve this problem, developers use a CRC or stamp a confirmation mark on the spare area. Cyclic redundancy checking (CRC) is one of the methods to check if there is an error in the data transmitted over the communication link. The system can use the CRC to identify the error that occurred when the power off. The method of writing a confirmation mark in the spare area writes a data pattern in the spare area and checks an error state by comparing the data of the cell in which the program operation is performed with the data pattern. Since these methods are performed by executing the related software, the program code must be entered. As a result, the code size becomes large and must be executed each time the instruction is processed, thereby degrading system performance.

An object of the present invention is to provide a flash memory system that can increase the reliability of the operation when sudden power off.

A flash memory system according to an aspect of the present invention comprises: a flash memory for storing data; A controller for controlling the flash memory; And a pull-down driver configured to deactivate the command latch enable signal provided from the controller to the flash memory while the power is turned off, wherein the flash memory receives a command from the controller in response to the deactivated command latch enable signal. Not provided

In this embodiment, the flash memory system further includes a first charging unit configured to supply power to the flash memory while the power is turned off.

In this embodiment, the flash memory normally processes a command received from the controller before the power is turned off.

In this embodiment, the power off is sudden power off.

In this embodiment, the pull-down driver is composed of a resistor.

In this embodiment, the first charging unit is composed of a capacitor.

In this embodiment, the flash memory system includes a power sensor for detecting that the power is off; A switch controlled by the power sensor, the switch switching the command latch enable signal from the controller to the flash memory; And a second charging unit configured to supply power to the power sensor while the power is turned off.

In this embodiment, the power sensor turns off the switch while the power is off.

In this embodiment, the second charging unit is composed of a capacitor.

The flash memory system according to the present invention can increase the reliability of the operation during sudden power off.

1 is a block diagram of a flash memory system according to an embodiment of the present invention;

2 and 3 are timing diagrams of power off and command signals;

4 is a block diagram of a flash memory system according to another embodiment of the present invention;

5 is a schematic diagram of a computing system including a flash memory system according to the present invention.

<Description of the symbols for the main parts of the drawings>

1000,2000: flash memory system 100: flash memory

200: controller 101: pull-down drive unit

102: first charging unit 201: switch

202: power sensor 203: second charging unit

300: modem 400: microprocessor

500: user interface 600: battery

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1 is a block diagram of a flash memory system according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a flash memory system 1000 according to an exemplary embodiment of the present invention includes a flash memory 100, a controller 200, a pull-down driver 101, and a charger 102.

The flash memory 100 includes a plurality of memory cells (not shown) for storing data. The plurality of memory cells are arranged at the intersection of rows and columns. The controller 200 controls the overall operation of the flash memory 100. For example, when a program or erase operation is requested from an external host (not shown), the controller 110 performs the requested operation to program data received from the host into a flash memory or stored in the flash memory. Clear the data. In a program or erase operation, the controller 200 transmits a program command or an erase command provided from a host to the flash memory. At this time, the controller 200 provides the activated command latch enable signal to the flash memory 100. The flash memory 100 receives a command from the controller 200 in response to an activated command latch enable (hereinafter referred to as CLE) signal. The flash memory 100 performs a corresponding operation (program or erase operation) in response to the received command. When the CLE signal is deactivated, the flash memory 100 does not receive a command from the controller 200 in response to the deactivated CLE signal.

The pull-down driver 101 is composed of a resistor (R). Resistor R is a pull-down resistor. The pull-down driving unit 101 discharges the CLE signal to the ground voltage at the time of sudden power-off and deactivates it. Since the CLE signal is deactivated, the flash memory 100 does not receive a command from the controller 200 during the sudden power off.

The charging unit 102 is composed of a capacitor (C1). The charging unit 102 supplies the charged power to the flash memory 100 so that the operation of the flash memory 100 according to the transmitted command is stably performed during the sudden power off after the command signal is transmitted.

2 and 3 are timing diagrams of power off and command signals.

FIG. 2 illustrates a case where a command is transmitted during a sudden power off, and FIG. 3 illustrates a case where a sudden power off occurs as soon as the command is transmitted.

Hereinafter, the operation of the flash memory system 1000 will be described by taking a program operation as an example. In the program operation, the controller 200 transmits the activated CLE signal to the flash memory 100. Therefore, the flash memory 100 performs a program operation in response to a program command provided from the controller 200.

In the case of sudden power off, there is a power off period A as shown in FIGS. 2 and 3.

1 and 2, when a program command is transmitted to the flash memory 100 while the power is off, the operation of the flash memory system 1000 will be described as follows.

As illustrated in FIG. 2, the flash memory 100 may receive a program command from the controller 200 even while the power is turned off. In this case, since the power is turned off, the flash memory 100 cannot normally perform a program operation in response to the provided program command. The pull-down driver 101 discharges the CLE signal to the ground voltage level when sudden power off occurs. In other words, the pull-down driver 101 inactivates the CLE signal. Therefore, no program command is sent to the flash memory 100 during the sudden power off.

1 and 3, when sudden power off occurs as soon as a program command is transmitted from the controller 200 to the flash memory 100, the operation of the flash memory system 1000 will be described.

When sudden power off occurs after a program command is transmitted from the controller 200 to the flash memory 100, the flash memory 100 may not receive sufficient power to perform a program operation in response to the program command. . In this case, the capacitor C1 of the charging unit 102 provides the flash memory 100 with the charged power during the sudden power off. Therefore, the flash memory 100 can stably perform a program operation.

As a result, the pull-down driver 101 of the flash memory system 1000 according to an embodiment of the present invention prevents a command generated during sudden power off from being transmitted to the flash memory 100. In addition, when sudden power off occurs after the command is transmitted, the charged power is provided to the flash memory 100 so that the program operation of the flash memory 100 of the charging unit 102 of the flash memory system 1000 is stably performed. .

Therefore, the flash memory system 100 of the present invention can increase the reliability of the operation when sudden power off.

4 is a block diagram of a flash memory system according to another exemplary embodiment.

Referring to FIG. 4, a flash memory system 2000 according to another embodiment of the present invention may include a flash memory 100, a controller 200, a pull-down driving unit 101, a first charging unit 102, a switch 201, The power sensor 202 and the second charging unit 203 is included.

The connection configuration and operation of the flash memory 100, the controller 200, the pull-down driving unit 101, and the first charging unit 102 may be performed by using the flash memory 100, the controller 200, and the pull-down driving unit 101 illustrated in FIG. 1. ) And the charging unit 102, and the description thereof will be omitted.

The power sensor 202 is connected to the power VDD and senses a sudden power off in which the power VDD suddenly turns off. The power sensor 202 controls the switch 201 according to the detection result. The second charging unit 203 is composed of a capacitor (C2). The second charging unit 203 supplies the charged power to the power sensor 202 so that the power sensor 202 can operate normally when sudden power off.

When a sudden power off occurs, the power sensor 202 detects a sudden power off and turns off the switch 201. Since the switch 201 is off, the CLE signal is not transmitted to the flash memory 100. Thus, the command is not sent to the flash memory 100. When sudden power off occurs, the power sensor 202 may not be supplied with power, and thus may not operate normally. However, the capacitor C2 of the second charging unit 203 supplies the charged power to the power sensor 202 at the sudden power off. Thus, the power sensor 202 operates normally.

As a result, the flash memory system 2000 according to another embodiment of the present invention can increase the reliability of the operation when sudden power off.

5 is a schematic diagram of a computing system including a flash memory system according to the present invention.

The semiconductor memory device is a nonvolatile memory device capable of retaining stored data even when power is cut off. With the increasing use of mobile devices such as cellular phones, PDA digital cameras, portable game consoles, and MP3Ps, semiconductor memory devices are becoming more widely used as code storage as well as data storage. Semiconductor memory devices may also be used in home applications such as HDTV, DVD, routers, and GPS. A computing system including the semiconductor memory device 100 according to the present invention is schematically illustrated in FIG. 5.

The computing system according to the present invention includes a microprocessor 400 electrically connected to a bus 30, a user interface 500, a modem 300 such as a baseband chipset, a memory controller 200, and a semiconductor memory. Device 100. The memory controller 200 and the semiconductor memory device 100 constitute a memory system. Although the pull-down driver, the first and second chargers, the power sensor, and the switch are not shown in FIG. 5, the memory system will be configured substantially the same as those shown in FIGS. 1 and 4. In the semiconductor memory device 100, N-bit data (N is an integer of 1 or larger) to be processed / processed by the microprocessor 400 may be stored under the control of the memory controller 200.

When the computing system according to the present invention is a mobile device, a battery 600 for supplying an operating voltage of the computing system will be further provided. Although not shown in the drawings, the computing system according to the present invention may further be provided with an application chipset, a camera image processor (CIS), a mobile DRAM, and the like. Self-explanatory to those who have learned.

Although not shown in FIG. 5, the first and second charging units 102 and 203 shown in FIGS. 1 and 4 may be configured as auxiliary batteries in addition to the capacitor in the computing system shown in FIG. 5.

As described above, the best embodiment has been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (12)

A flash memory for storing data; A controller for controlling the flash memory; And A pull-down driver for deactivating a command latch enable signal provided from the controller to the flash memory while the power is off; And the flash memory is not provided with a command from the controller in response to the inactivated command latch enable signal. The method of claim 1, And a first charging unit configured to supply power to the flash memory while the power is turned off. The method of claim 2, The flash memory system normally processes a command received from the controller before the power is turned off. The method of claim 1, And the power off is sudden power off. The method of claim 1, The pull down driving unit is configured by a resistor. The method of claim 2, And the first charging unit comprises a capacitor. The method of claim 2, A power sensor detecting that the power is turned off; A switch controlled by the power sensor, the switch switching the command latch enable signal from the controller to the flash memory; And The flash memory system further comprises a second charging unit for supplying power to the power sensor while the power is off. The method of claim 7, wherein And the power sensor turns off the switch while the power is off. The method of claim 7, wherein The second charging unit is a flash memory system consisting of a capacitor. Microprocessor; Flash memory; A memory controller configured to control the flash memory device at the request of the microprocessor; A pull-down driver configured to disable a command latch enable signal provided from the memory controller to the flash memory while power is turned off; And A first charging unit configured to supply power to the flash memory while the power is off; And the flash memory normally processes a command received from the controller before powering off, and receives no command from the controller in response to the inactivated command latch enable signal. The method of claim 12, A power sensor detecting that the power is turned off; A switch controlled by the power sensor, the switch switching the command latch enable signal from the controller to the flash memory; And Further comprising a second charging unit for supplying power to the power sensor while the power is off, The power sensor turns off the switch while the power is off. The method of claim 11, The first and second charging unit is a computing system consisting of a secondary battery.