KR20090099372A - Apparatus for transmitting image data and system including the same - Google Patents

Abstract

An apparatus for transmitting image data and a system including the same are provided to transmit image data to a host at the same speed as the receiving speed without any restriction of transmission speed of the communication unit by splitting and processing the received image data through an independent path. An apparatus for transmitting image data includes a field programmable gate array(210), a buffer memory(220), a main communication unit controller(250) and at least one auxiliary communication unit controller(260-260n). The filed programmable gate array split the received image data and processes the split image through an independent path. In addition, field programmable gate array outputs the first and second split image data simultaneously. The buffer memory stores the first and second image data received from the gate array temporarily. The main communication unit controller receives the first split image data from the filed programmable gate array, and converts the received image data and transmits the converted image data to a host.

Description

Apparatus for transmitting image data and system including the same}

The present invention relates to image data transmission, and more particularly, to an image data transmission apparatus and a system including the same for the high-speed transmission of image data through a communication means such as a USB port.

Image capturing is performed through an image sensor, which is a device that reproduces an image by using a semiconductor-responsive property. Such an image sensor includes a complementary metal oxide semiconductor (CMOS) image sensor and a charge coupled device. device).

CMOS Image Sensor (CIS) consists of a pixel array that senses light and an analog-to-digital converter that converts signals output from the pixel array into digital signals. It is connected to an image signal processor (ISP). Broad image sensors include System on a chip (SoC), including CCD, CIS, ISP and ISP. Hereinafter, the image sensor used in the present invention is considered to mean a wide range of image sensor.

The image sensor has a register therein. For example, the CMOS image sensor may include registers for image scaling, bad pixel replacement (BPR), and the like, and the image signal processing apparatus may include registers for auto exposure (AE), auto white balance (AWB), and the like. have.

Optimum register settings are needed to maximize the performance of the image sensor, and this process is called tuning. The conventional image tuning apparatus converts an image of a subject placed under a specific light source into an electrical signal and outputs the image sensor, a register included in the image sensor, and an electrical signal output from the image sensor to a communication means such as a USB, thereby converting the image into an image. A viewer for displaying, and a computer device for controlling register setting values.

With the development of image sensor manufacturing technology, the number of pixels per frame increases and it operates at high speed, but the transmission speed of communication means such as USB port connecting to a computer is limited. it's difficult.

For example, a CMOS-type image sensor of 2048 pixels wide by 1536 pixels wide can be used to generate 15 frames of image data per second with RAW 10bit, a register setting that is used a lot in sensor evaluation. If you transfer image data over USB 2.0, a widely used means of communication, you need to transfer 2048 pixels / width * 1536 pixels / length * 10 bits / pixel * 15 frames = 471,859,200 bits per second. The maximum transfer speed of USB 2.0 is 480Mbps, so it can be said that it shows the best efficiency in terms of effective data. However, the result will be different considering the data format required by USB (Universal Serial Bus) transfer.

USB was developed by seven companies from IBM, Compaq, Intel, Microsoft, NEC, Northern Telecom, and DEC to integrate peripherals into one device for easier and lower cost connectivity. If you have only one USB connector, you can connect up to 127 peripheral devices in a star connection or radial form. By using USB, all peripheral devices are connected to the same connector without any software or hardware setup when connecting peripheral devices to a PC, which not only reduces the number of ports, but also enables easy installation and miniaturization of portable PCs. There is an advantage to doing that.

The transmission speed of USB is 1.5Mbps in low-speed mode and 12Mbps in full-speed mode. Recently, USB 2.0 has improved the transmission speed up to 480Mbps.

1 is a diagram showing a detailed format of USB data. A Sort of Frame (SOF) packet in the frame sequence indicates the beginning of a frame. The frame may be repeated at a time of 1 ms or 125 us. In addition to the SOF packet, there is isochronous, interrupt, and bulk in one frame. These represent transmission methods and have a constant bandwidth within one frame. Each transmission method has different characteristics. Generally, isochronus is suitable for real-time transmission such as microphone, interrupt transmission for aperiodic input such as keyboard, and bulk transmission for large data. The packet sequence is composed of a token packet, a data packet, and a handshake packet. Among them, the data packet is composed of data (DATA), SYNC, PID (packet ID), cyclic redundancy checks (CRC) 16, and end of point (EOP). SYNC is the beginning of all USB packets and is 32 bits long in high-speed transmission. PID determines the type of packet and has a length of 8 bits. CRC16 checks for errors and has a length of 16 bits. E0P indicates the end of a packet and has a length of 3 bits. The important part is the data that will transfer the image. The data may be up to 1024 bytes in size in the case of isochronous transmission used in image data transmission, but transmission in bytes is required.

After all, even if the size of the valid image data is within the maximum transfer speed of the USB port, if there is an output of RAW 10bit, it must be reconfigured to 8-bit according to the USB data format, and 6-bit unnecessary information is included. Is sent. In this case, it is the same as sending 16-bit output. When transferring image data generated by the above-mentioned image sensor through the USB port, 2048 pixels / width * 1536 pixels / length * 16 bits / pixel * 15 frames = 754,974,720 bits should be sent This exceeds the maximum transfer rate of the USB port. Considering the maximum transfer rate, only about 9.5 frames per second are sent. Therefore, due to the limitation of USB port transfer speed, it is not possible to fully utilize the image data provided at high speed. The transmission rate is a calculation of an ideal frame rate, and actually shows a lower frame rate.

Therefore, in the case of a CMOS image sensor of 3 megapixels or more, real-time transmission of the image data is difficult, and thus may be limited in tuning or performance evaluation of the sensor. For convenience, a description has been given on the basis of USB, which is a representative communication means. However, the same problem occurs with other communication means.

In order to solve the above problems, an object of the present invention is to provide an image data transmission apparatus for overcoming the transmission rate limitation of the communication means at the time of image data transmission.

It is also an object of the present invention to provide a system comprising an image data transmission apparatus for overcoming the transmission rate limitation of a communication means.

In order to achieve the above object, an image data transmission apparatus according to an embodiment of the present invention includes a field programmable gate array (FPGA), a buffer memory, a main communication means controller and one or more auxiliary communication means controller. .

The FPGA divides image data received from an external device, processes the divided image data through independent paths, respectively, and simultaneously outputs first divided image data and one or more second divided image data. The buffer memory temporarily receives the first divided image data and the one or more second divided image data from the FPGA. The main communication means controller receives the first divided image data from the FPGA, converts it, and transmits the first transmission image data to a host. The at least one auxiliary communication means controller receives the at least one second divided image data from the FPGA, converts the at least one second divided image data, and transmits at least one second transmitted image data to the host.

The buffer memory may include a main buffer memory and one or more auxiliary buffer memories. The configuration of the one or more auxiliary buffer memories is based on the one or more second divided image data. The main buffer memory may receive the first divided image data from the FPGA and temporarily store the first divided image data, and the one or more auxiliary buffer memories may receive the one or more second divided image data from the FPGA and store the temporary data.

The main communication means controller may receive a control signal from the host. The image data transmission device may further include a clock generator. The clock generator generates a clock signal based on the control signal received by the main communication means controller and outputs the clock signal to the FPGA. The FPGA may operate in synchronization with the clock signal.

The image data transmission device may further include a receiver. The receiver converts a format of image data generated by an external device and outputs the image data to the FPGA. That is, when the format of the image data generated by the external device is different from the image data format required by the FPGA, the image data format may be converted to generate and output the image data in a format that the FPGA can process. have. The receiver may also serve to adjust a voltage level suitable for communication with the main communication means controller.

In one embodiment, the image data may be composed of 10 bits, the first divided image data may be 8 bits and the second divided image data may be 2 bits.

The system according to an embodiment of the present invention includes an image data generating device, an image data transmitting device and a host. The image data generating device provides image data to the image data transmitting device. The image data transmission device receives and processes the image data from the image data generating device. The host receives the processed image data and visually displays it. The image data transmission device includes an FPGA, a buffer memory, a primary communication means controller and one or more auxiliary communication means controllers. The FPGA divides the image data received from the image data generator, processes the divided image data through independent paths, respectively, and simultaneously outputs the first divided image data and the one or more second divided image data. The buffer memory temporarily receives the first divided image data and the one or more second divided image data from the FPGA. The main communication means controller receives the first divided image data from the FPGA and converts the first divided image data into first transmission image data, which can be transmitted to a communication means including a USB port, and transmits the converted first image data to the host. The at least one auxiliary communication means controller receives the at least one second divided image data from the FPGA, and converts the at least one second transmission image data into at least one second transmission image data in a form that can be transmitted to a communication means including a USB port. do.

In one embodiment, the host may include a first processing unit and one or more second processing units. The first processing unit may receive and process the first transmission image data from the main communication means controller, and the one or more second processing units respectively receive and process the one or more second transmission image data from the auxiliary communication means controller. can do.

The image data transmission apparatus according to embodiments of the present invention divides image data received from the outside, processes them through independent paths, and simultaneously outputs the image data without being limited to the transmission speed limit of the communication means. Can transmit to the host at the same rate.

In addition, the system including the image data transmission apparatus according to the embodiments of the present invention as described above is processed by separate paths through the received image data and output at the same time without being limited by the transmission speed limit of the communication means Can be transmitted to the host at the same speed as the reception speed, thereby accurately evaluating the performance of the image data generating device.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features It should be understood that it does not exclude in advance the possibility of the presence or addition of numbers, steps, operations, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. .

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. The same reference numerals are used for the same elements in the drawings, and duplicate descriptions of the same elements are omitted.

2 is a block diagram illustrating a system including an image data transmission device according to an embodiment of the present invention.

Referring to FIG. 2, the system 1000 includes an image data generating apparatus 100, an image data transmitting apparatus 200, and a host 300. The image data generating apparatus 100 generates image data and provides the image data to the image data transmitting apparatus 200. The image data generator may be an image sensor such as a CMOS image sensor (CIS), or may be implemented as a system on chip (SoC) including an image sensor and an image signal processor (ISP). The generated image data may have formats such as RGB Bayer and YUV. The image data transmission device 200 receives the generated image data, divides it, processes it through independent paths, and transmits it to the host 300. The host 300 may receive the processed image data and visually display it. The host 300 may receive a control signal for selecting an image data communication method such as a USB data transmission method as well as a clock signal to the image data transmission device 200. The host 300 may include a display unit for visually displaying image data received from the image data transmission device 200. The host 300 may be a personal computer, a cellular phone, a personal data assistant, or the like. The reconstruction operation of the image data for displaying the image in the host 300 will be described later.

3 is a block diagram illustrating an image data transmission apparatus according to an embodiment of the present invention.

Referring to FIG. 3, the image data transmission apparatus 200a may include a field programmable gate array (FPGA) 210, a main buffer memory 220, one or more auxiliary buffer memories 230a to 230n, and a clock generator. 240, primary communication means controller 250, and one or more secondary communication means controllers 260a through 260n. The FPGA 210 splits the received image data IMG, respectively, to generate first divided image data IMG1 and one or more second divided image data IMG2a to IMG2n. The first divided image data IMG1 and one or more second divided image data IMG2a to IMG2n are temporarily stored in the main buffer memory 220 and the one or more auxiliary buffer memories 230a through 230n, respectively. The main communication means controller 250 receives a control signal CON including a signal for determining an operating frequency of the clock signal CLK from the host 300 of FIG. 2 and based on the clock information included in the clock reference signal. It generates (CLK_CON) and outputs it to the clock generator 240. The clock generator 240 receives the clock reference signal CLK_CON to generate a clock signal CLK and outputs the clock signal CLK to the FPGA 210. The FPGA 210 may synchronize the first divided image data IMG1 and the one or more second divided image data IMG2a to IMG2n with the main buffer memory 220 and the at least one auxiliary buffer memory in synchronization with the received clock signal CLK. Received at 230a through 230n and the first divided image data IMG1 is simultaneously communicated to the main communication means controller 250 and at least one second divided image data IMG2a to IMG2n is the at least one secondary communication means controller 260a to 260n. Output That is, the FPGA 210 divides the image data IMG received from the external device and processes the divided image data through independent paths, respectively, so that the first divided image data IMG1 and the one or more second divided image data ( IMG2a to IMG2n) are output simultaneously. The main buffer memory 220 and the at least one auxiliary buffer memory 230 may be implemented in a structure independent from each other or as a buffer memory. The primary communication means controller 250 and the one or more auxiliary communication means controllers 260a to 260n receive the first divided image data IMG1 and the one or more second divided image data IMG2a to IMG2n from the FPGA 210 to receive the USB. The data is converted into a data format suitable for communication means, and the converted first transmission image data IM_TRS1 and one or more second transmission image data IM_TRS2a to IM_TRS2n are transmitted to the host 300 of FIG. 2. By dividing the received image data in this way and processing and transmitting it simultaneously through two or more independent paths, the problem that the image data cannot be transmitted at the same speed as the received speed due to the transmission speed limitation of the communication means including the USB port can be solved. Can be.

 For example, if there is an output of RAW 10bit from a CMOS type image sensor, it is a data format suitable for communication means including USB data. The first divided image data IMG1 is 8 bits, and the second divided image data IMG2a is 2 bits. It can be a bit configuration. If the FPGA 210 processes and outputs the first and second divided image data IMG1 and IMG2a through separate paths, respectively, the primary communication means controller 250 is 2048 pixels / width * 1536 pixels / length * 8 bits per second. / Pixel * 15 frames = 377,487, 360 bits of the first transmission image data (IM_TRS1) is transmitted to the host 300 of FIG. Auxiliary communication means controller 260a also transmits 2 bits of valid information, but since the data required by communication means including USB is configured in 8-bit units, it transmits meaningless 6 bits per pixel, so that the main communication means per second The second transmission image data IM_TRS2a having the same size as that of the controller 260 is transmitted to the host 300 of FIG. 2. Therefore, the image data can be transmitted at the same speed as the received speed without being limited by the USB port transfer speed limit of 480Mbps. In addition, if the image data is generated in units of 20 bits, the first divided image data IMG1 may be composed of 8 bits and the two second divided image data IMG2a and IMG2b may be composed of 8 bits and 4 bits, respectively. In this way, when the size of the image data increases, the configuration of the auxiliary buffer memory and the auxiliary communication means controller can be expanded.

The main communication means controller 250 may receive the control signal CON from the host 300 of FIG. 2. The control signal CON includes a signal for selecting an operating frequency of the clock signal CLK and a data transmission method between the host 300 and the image data transmission device 200.

When a connection device such as an image data transmission device is connected to the host 300 of two, the auxiliary communication means controllers 260a to 260n may interact with each other such as to recognize and install the connection device so that the connection device can communicate with the host 300. Do it. This is commonly referred to as Plug and Play, eliminating the need for users to manually tune the software environment for hardware or peripherals, and use dynamic configuration changes to drive proper behavior. The auxiliary communication means controllers 260a to 260n receive signals from the host 300 only at the initial stage of installation so that the connection device can operate smoothly in communication with the host 300. In the normal transmission operation, the main communication means Like the controller 250, the control signal CON may not be received.

In the host 300 of FIG. 2, the main communication means controller 250 and the one or more auxiliary communication means controllers 260a to 260n may include the first divided image data IMG1 and the one or more second divided image data IMG2a to IMG2n. Receives the first transmission image data IM_TRS1 and one or more second transmission image data IM_TRS2a to IM_TRS2n converted according to a data format required by a communication means including a USB port. The performance of the image data generating apparatus 100 of FIG. 2 may be evaluated by restoring and visually displaying the same in the host 300. When the FPGA 210 divides the image data IMG to generate the first divided image IMG1 and the one or more second divided images IMG2a to IMG2n, each of the same pixels is identified by the same mark and the host 300 is separated. ) Recognizes the same identification mark and restores the image data IMG before being divided. For example, the host 300 includes a first processing unit and one or more second processing units, and the first processing unit includes the first transmission image data IM_TRS1, and the one or more second processing units includes one or more second transmission image data ( IM_TRS2a to IM_TRS2n) may be respectively received to collect portions having the same identification mark in the plurality of transmission image data, and reconstruct the divided image data into one image data IMG.

4 is a block diagram illustrating an FPGA included in an image data transmission apparatus according to an embodiment of the present invention.

Referring to FIG. 4, the FPGA 210 includes an image data divider 211, a first image data communication unit 212, and a second image data communication unit 213. The second image data communication unit 213 may have one or more configurations according to the number of the second divided image data IMG2a to IMG2n. Hereinafter, for convenience, the second image data communication unit 213 will have one second divided image data IMG2a. Do it.

The image data divider 211 divides the received image data IMG into the first divided image data IMG1 and the second divided image data IMG2a. The image data divider 211 receives the image data processed by the image data transmission apparatus 200 of FIG. 2 from the host 300 of FIG. 2 and visually displays each of the first and second divided image data. (IMG1, IMG2a) may be labeled with identification. The first divided image data IMG1 is temporarily stored in the main buffer memory 220 of FIG. 3, and the second divided image data IMG2a is temporarily stored in the auxiliary buffer memory 230a of FIG. 3. The first image data communication unit 212 displays the first divided image data IMG1 stored in the main buffer memory 220 of FIG. 2 in synchronization with the clock signal CLK generated by the clock generator 240 of FIG. 3. The main communication means of the controller 250 outputs. The second image data communication unit 213 is stored in the auxiliary buffer memory 230a of FIG. 2 in synchronization with the clock signal CLK generated by the clock generator 240 of FIG. 3 simultaneously with the first image data communication unit 212. The two divided image data IMG2a are output to the auxiliary communication means controller 260a of FIG. Therefore, the image data IMG is divided and processed through independent paths, respectively, and the first and second divided image data IMG1 and IMG2a are output at the same time so that the main communication means controller 250 and the auxiliary communication means controller 260a of FIG. ) Simultaneously receives the first and second divided image data IMG1 and IMG2a. As a result, the main communication means controller 250 and the auxiliary communication means controller 260a of FIG. 3 convert the received first and second divided image data IMG1 and IMG2a to the first and second transmission image data IM_TRS1. , IM_TRS2a) is transmitted to the host 300 of FIG. Fast transmission speed as a means of communication of image data USB port can be used, the communication means is not limited to the USB port.

5 is a block diagram illustrating an image data transmission apparatus according to an embodiment of the present invention.

Referring to FIG. 5, the image data transmission apparatus 200b includes a receiver 500, an FPGA 210, a main buffer memory 220, one or more auxiliary buffer memories 230a to 230n, a clock generator 240, and main communication. Means controller 270 and one or more auxiliary communication means controllers 260a to 260n. The receiver 500 may include an interface unit 510 and a level shifter 520. The interface unit 510 converts the image data S_IMG generated by the external device into the image data IMG and provides the converted image data to the FPGA 210. This is because the image data S_IMG generated by the external device is provided to the FPGA 210 when the image data S_IMG generated by the external device is not suitable for the data format required by the FPGA 210. This is because the transmission device 200a is difficult to perform its own operation. That is, the interface unit 510 converts the image data S_IMG generated from the external device into image data IMG suitable for the data format required by the FPGA 210 and outputs the image data IMG to the FPGA 210. The level shifter 520 adjusts the voltage level to match the format of the received data when the operating voltages of the main communication means controller 270 and the interface unit 510 differ according to the data format.

The FPGA 210 divides the received image data IMG to generate first divided image data IMG1 and one or more second divided image data IMG2a to IMG2n. The first divided image data IMG1 and one or more second divided image data IMG2a to IMG2n are temporarily stored in the main buffer memory 220 and the one or more auxiliary buffer memories 230a to 230n, respectively. The FPGA 210 simultaneously synchronizes the first divided image data IMG1 and the one or more second divided image data IMG2a in the main buffer memory 220 and the one or more auxiliary buffer memories 230a through 230n in synchronization with the clock signal CLK. To IMG2n). The FPGA 210 outputs the first divided image data IMG1 to the main communication means controller 270 and outputs one or more second divided image data IMG2a to IMG2n to the one or more auxiliary communication means controllers 260a to 260n, respectively. Output at the same time. The clock signal CLK includes the clock generator 240 in response to the clock reference signal CLK_CON generated according to the clock information included in the control signal CON received by the main communication means controller 270 from the host 300 of FIG. 2. Is a signal generated by providing to. The FPGA 210 outputs the first divided image data IMG1 to the main communication means controller 270 and outputs one or more second divided image data IMG2a to IMG2n to the one or more auxiliary communication means controllers 260a to 260n, respectively. Output The main communication means controller 270 converts the first divided image data IMG1 to generate the first transmission image data IM_TRS1 and transmits it to the host 300 of FIG. 2, and the one or more auxiliary communication means controllers 260a to 260n. ) Converts one or more second divided image data IMG2a to IMG2n, generates one or more second transmission image data IM_TRS2a to IM_TRS2n, and transmits them to the host 300 of FIG. 2, respectively.

In other words, the first divided image IMG1 divided by the FPGA 210 may be temporarily stored in the main buffer memory 220, and then output to the main communication means controller 270 in synchronization with the clock signal CLK, and then the main communication. The means controller 270 converts the first transmission image data IM_TRS1 to the host 300 shown in FIG. 2 in accordance with the data format required by the communication means including USB. Similarly, one or more second divided image data IMG2a to IMG2n are temporarily stored in one or more auxiliary buffer memories 230a to 230n, respectively, and then one or more auxiliary communication means controllers 260a to 260n in synchronization with the clock signal CLK. Are respectively outputted to the one or more second transmission image data IM_TRS2a to IM_TRS2n by the one or more auxiliary communication means controllers 260a to 260n to be adapted to the data format required by the communication means including USB. 300 respectively. As such, the first divided image data IMG1 and the one or more second divided image data IMG2a to IMG2n divided by the FPGA 210 are processed and transmitted simultaneously through independent paths. The main buffer memory 220 and the auxiliary buffer memories 230a to 230n may have a plurality of structures independent of each other or may be implemented as one buffer memory.

As described with reference to FIG. 3, the host 300 may receive and visually display the first transmission image data IM_TRS1 and one or more second transmission image data IM_TRS2a to IM_TRS2n.

The present invention can be used when transmitting image data, and is particularly useful when transmitting a large amount of image data at high speed. Image data can be transmitted without being limited by the maximum transmission speed of the communication means including the USB port, so it can be more useful when using an image data generating device having high quality or high speed operation. When the image data is transmitted using the port, the user's convenience can be achieved.

While the invention has been described above with reference to preferred embodiments, those skilled in the art will be able to make various modifications and changes to the invention without departing from the spirit and scope of the invention as set forth in the claims below. I will understand.

1 is a diagram showing a detailed format of USB data.

2 is a block diagram illustrating a system including an image data transmission device according to an embodiment of the present invention.

3 is a block diagram illustrating an image data transmission apparatus according to an embodiment of the present invention.

FIG. 4 is a block diagram illustrating a field programmable gate array (FPGA) included in an image data transmission apparatus according to an embodiment of the present invention.

5 is a block diagram illustrating an image data transmission apparatus according to an embodiment of the present invention.

Claims (7)

A field programmable gate array for dividing image data received from an external device and processing the divided image data through independent paths to output first divided image data and at least one second divided image data simultaneously. ; A buffer memory configured to temporarily receive the first divided image data and the one or more second divided image data from the field programmable gate array, and to temporarily store the first divided image data; A main communication means controller for receiving the first divided image data from the field programmable gate array, converting the received image data, and transmitting the first transmitted image data to a host; And One or more auxiliary communication means controllers each receiving the one or more second divided image data from the field programmable gate array, converting the received image data and transmitting one or more second transmission image data to the host, respectively; Data transmission device. The method of claim 1, wherein the buffer memory comprises a main buffer memory for temporarily storing the first divided image data and at least one auxiliary buffer memory for temporarily storing the one or more second divided image data. Image data transmission device. The image data transmission device according to claim 1, wherein said main communication means controller receives a control signal from said host. 4. The clock generator of claim 3, further comprising a clock generator for generating a clock signal based on clock information included in the control signal from the main communication means controller and outputting the clock signal to the field programmable gate array. Image data transmission device. The image data transmission apparatus of claim 1, further comprising a receiver configured to convert a format of image data generated by the external device and output the image data to the field programmable gate array. An image data generator for providing image data; An image data transmission device which receives the image data, divides the image data, and processes the image data through independent paths; And Consists of a host receiving and visually processing the processed image data, The image data transmission device, A field programmable gate array for dividing the image data received from the data generating device, and processing the divided image data through independent paths, respectively, to simultaneously output the first divided image data and the one or more second divided image data; A buffer memory configured to temporarily receive the first divided image data and the one or more second divided image data from the field programmable gate array, and to temporarily store the first divided image data; A main communication means controller for receiving the first divided image data from the field programmable gate array, converting the received image data, and transmitting first transmitted image data to the host; And One or more auxiliary communication means controllers each receiving the one or more second divided image data from the field programmable gate array and converting the received image data to transmit one or more second transmission image data to the host, respectively. System characterized. The apparatus of claim 6, wherein the host receives and processes the second transmission image data from the first processor and the at least one auxiliary communication means controller, respectively, for receiving and processing the first transmission image data from the main communication means controller. And at least one second processing unit.

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