KR20090099354A - Liquide crystal display device and method for fabricating the same - Google Patents

Abstract

A liquid crystal display device and a method for manufacturing the same are provided to uniformly rub an area where a pixel electrode and a common electrode are overlapped each other and an area between the pixel electrode and the common electrode with an alignment film in the same direction. A liquid crystal display device comprises a substrate, a thin film transistor(104), a protective layer(105), a pixel electrode forming groove(105a), a common electrode forming groove(105b), a pixel electrode(106), and a common electrode(107). A gate line and a data line cross each other to form the substrate. The thin film transistor is formed in an area where the gate line and the data line of each pixel of the substrate cross each other. The thin film transistor comprises a gate electrode(104a), a source electrode(104d), and a drain electrode(104e). The protective layer is formed on the substrate in which the thin film transistor is formed. The pixel electrode forming grooves and the common electrode forming grooves are alternatively formed in every protective layer of each pixel in parallel. The pixel electrode forming grooves and the common electrode forming grooves are formed from an upper surface to a lower part of the protective layer.

Description

Liquid crystal display and its manufacturing method {LIQUIDE CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method of manufacturing the same. The present invention relates to a liquid crystal display device having an alignment film having a uniform degree of rubbing due to the rubbing of the alignment film in a region where the pixel electrode and the common electrode are formed.

BACKGROUND ART In general, liquid crystal display devices have tended to be gradually widened due to their light weight, thinness, and low power consumption. Accordingly, the liquid crystal display device is widely used as a means for displaying a screen in portable computers, mobile phones, office automation equipment and the like.

In general, a liquid crystal display device displays a desired image on a screen by adjusting the amount of light transmitted according to image signals applied to a plurality of control switching elements arranged in a matrix.

The liquid crystal display device includes a liquid crystal panel in which a color filter substrate as an upper substrate and a thin film transistor array substrate as a lower substrate are opposed to each other, and a liquid crystal layer is filled between the two substrates, and a scan signal and image information are supplied to the liquid crystal panel to provide a liquid crystal. It comprises a drive unit for operating the panel.

A conventional liquid crystal display device having such a configuration will be described below with reference to the accompanying drawings.

As shown in FIG. 1, a conventional liquid crystal display device includes a first substrate 1 that is a thin film transistor array substrate and a second substrate 20 that is a color filter substrate, and the first substrate 1 and the second substrate. The liquid crystal layer is formed between the substrates 20.

Although not shown in detail in the drawing, a gate line and a data line are formed on the first substrate 1 so as to cross each other in a longitudinal direction and define a plurality of pixels, and an area where the gate line and the data line of each pixel cross each other. The thin film transistor is provided.

The thin film transistor includes a gate electrode formed on the first substrate 1, a gate insulating film formed on the gate electrode, a semiconductor layer formed on the gate insulating film, a source electrode and a drain electrode formed on the semiconductor layer. The protective layer 5 is formed on the source electrode and the drain electrode.

The gate electrode of the thin film transistor is connected to the gate line, the source electrode is connected to the data line, and the drain electrode is connected to the pixel electrode 6. Here, a plurality of pixel electrodes 6 are provided in each pixel to be substantially parallel to the data lines.

In addition, each pixel includes a common electrode 7 which is formed in parallel with the pixel electrode 6 to form a horizontal electric field along with the pixel electrode 6 to drive the liquid crystal layer. 6) and a first alignment layer 10 that determines the initial alignment of the liquid crystal on the first substrate 1 on which the common electrode 7 is formed.

In addition, a color filter layer 21 including red, green, and blue sub color filters is formed on the second substrate 20 facing the first substrate 1, and the initial alignment of liquid crystals is formed on the color filter layer 21. A second alignment film 25 is formed to determine.

In the conventional general liquid crystal display having the above configuration, the pixel electrode 6 and the common electrode 7 formed on the first substrate 1 are stepped with respect to the protective layer 5 as shown in FIG. 1. And the first alignment layer 10 formed on the first substrate 1 has the same structure as the pixel electrode 6 and the same in the rubbing operation of the first alignment layer 10 using a rubbing roll or the like. A problem arises in that the region in which the electrode 7 is formed to have a step with respect to the protective layer 5 does not rub or rub in a desired direction. As described above, when a portion of the first alignment layer 10 does not rub or does not rub in a desired direction, the rubbing is not uniform, so that light leakage, a phenomenon in which unwanted light is transmitted, occurs in the region. In particular, when the pixel implements black, it is observed as a large defect, thereby lowering the screen display quality of the liquid crystal panel.

The present invention is to solve the above problems, an object of the present invention is formed so that the pixel electrode and the common electrode do not have a step with respect to the protective layer and the upper surface of each of the pixel electrode, common electrode and the protective layer is on the same plane. As a result, a smooth rubbing of the alignment layer is achieved, and thus a liquid crystal display device and a method of manufacturing the same, which do not generate a light leakage problem due to poor rubbing.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes: a substrate formed by crossing a gate line and a data line with each other; A thin film transistor formed at an area where the gate line and the data line of each pixel of the substrate cross each other and having a gate electrode, a source electrode, and a drain electrode; A protective layer formed on the substrate on which the thin film transistor is formed; A plurality of pixel electrode formation grooves and common electrode formation grooves formed in an alternating manner in substantially parallel to each of the passivation layers of each pixel, and formed from an upper surface of the passivation layer to a lower portion of the passivation layer; A pixel electrode formed in the pixel electrode forming groove of each pixel, the upper surface of which is in plan with the upper surface of the protective layer; And a common electrode formed in the common electrode forming groove of each pixel, the upper surface of which is in plan with the upper surface of the protective layer; It is configured to include.

In the manufacturing method of the liquid crystal display device according to the preferred embodiment of the present invention for achieving the above object, a plurality of pixels are defined, each pixel is formed with a thin film transistor consisting of a gate electrode, a source electrode and a drain electrode Providing a substrate; Forming a protective layer on the substrate on which the thin film transistor is formed; The protective layer is removed by a thickness equal to the thickness of the protective layer to form a contact hole exposing a part of the drain electrode of the thin film transistor, and the protective layer is removed by a thickness smaller than the thickness of the protective layer, thereby substantially in each pixel. Forming a plurality of pixel electrode forming grooves and common electrode forming grooves alternately arranged in parallel; Forming a pixel electrode in the pixel electrode forming groove and forming a common electrode in the common electrode forming groove, wherein the upper surface of the pixel electrode, the upper surface of the common electrode, and the upper surface of the protective layer form a plane together; And forming an alignment layer on the substrate on which the pixel electrode and the common electrode are formed. It is made, including.

According to the present invention composed of the above-described configuration and manufacturing method, the upper surface of each of the pixel electrode, the common electrode, and the protective layer does not form a step, but is formed at a position corresponding to the same height with respect to the upper surface of the first substrate to form a plane. The alignment film formed on the pixel electrode, the common electrode, and the protective layer is also formed in a plane without forming a step. In a rubbing operation using a rubbing roll or the like, the common electrode and the region overlapping with the boundary region of the pixel electrode and the protective layer in the alignment layer; There is an effect that rubbing is performed smoothly over the entire region including the region overlapping with the boundary layer of the protective layer.

Accordingly, in the alignment layer, both the region overlapping the pixel electrode and the common electrode and the region overlapping the region between the pixel electrode and the common electrode are uniformly rubbed in the same direction.

Therefore, light leakage due to a rubbing defect generated due to the step of the alignment layer does not occur, and thus the display quality of the liquid crystal panel is improved.

Hereinafter, a liquid crystal display and a manufacturing method thereof according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to FIGS. 2 and 3 as follows.

2 and 3, a liquid crystal display according to an exemplary embodiment of the present invention includes a first substrate 101 formed by crossing a gate line 102 and a data line 103 with each other; It is formed in an area where the gate line 102 and the data line 103 of each pixel of the first substrate 101 intersect, and include a gate electrode 104a, a source electrode 104d, and a drain electrode 104e. Thin film transistor 104; A protective layer 105 formed on the first substrate 101 on which the thin film transistor 104 is formed; A plurality of pixel electrode forming grooves 105a and a common electrode forming groove 105b formed in an alternating manner in substantially parallel to each of the passivation layers 105 of each pixel, and formed from an upper surface of the passivation layer 105 downward; A pixel electrode 106 formed in the pixel electrode forming groove 105a of each pixel, the upper surface of which is in plane with the upper surface of the protective layer 105; And a common electrode 107 formed in the common electrode forming groove 105b of each pixel, the upper surface of which is in plane with the upper surface of the protective layer 105; It is configured to include.

Each component of the liquid crystal display according to the preferred embodiment of the present invention having such a configuration will be described in detail as follows.

Although not shown in detail in the drawings, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel including a first substrate 101 which is a thin film transistor array substrate and a second substrate which is a color filter substrate (not shown). A liquid crystal layer (not shown) is formed between the first substrate 101 and the second substrate.

Referring to FIG. 2, a gate line 102 and a data line 103 are formed on the first substrate 101 to cross each other longitudinally and horizontally to define a plurality of pixels, and the gate line 102 of each pixel is formed. The thin film transistor 104 is formed in an area where the data line 103 intersects with the gate line 102 and the data line 103.

2 and 3, the thin film transistor 104 formed in each pixel includes a gate electrode 104a formed on the first substrate 101 and a gate insulating film formed on the gate electrode 104a. 104b, a semiconductor layer 104c formed on the gate insulating film 104b, and a source electrode 104d and a drain electrode 104e formed on the semiconductor layer 104c.

The protective layer 105 is formed on the first substrate 101 on which the thin film transistor 104 having the above configuration is formed.

Referring to FIG. 3, the protective layer 105 is provided with a plurality of pixel electrode forming grooves 105a and common electrode forming grooves 105b for each pixel. The pixel electrode forming grooves 105a and the common electrode forming grooves are provided. 105b is formed one by one in turn so as to be substantially parallel in each pixel.

The pixel electrode forming groove 105a and the common electrode forming groove 105b have a groove shape formed downward from an upper surface of the protective layer 105, but preferably, the thickness is smaller than the thickness of the protective layer.

The protective layer 105 is provided with a pixel electrode connector forming groove 105c for each pixel, and the pixel electrode connector forming groove 105c is formed to be connected to the pixel electrode forming groove 105a in the pixel.

In addition, a contact hole 109 exposing a part of the drain electrode 104e of the thin film transistor 104 is formed in each passivation layer 105 in the pixel, which will be described in detail below.

Referring to FIG. 3, the pixel electrode 106 is formed inside the pixel electrode forming groove 105a formed in the protective layer 105, and the common electrode 107 is formed inside the common electrode forming groove 105b. The upper surface of the pixel electrode 106 and the upper surface of the common electrode 107 form a plane together with the upper surface of the region adjacent to the pixel electrode 106 and the common electrode 107 in the passivation layer 105. That is, the upper surface of the pixel electrode 106 and the upper surface of the common electrode 107 are formed on the first substrate 101 together with the upper surface of the region adjacent to the pixel electrode 106 and the common electrode 107 in the protective layer 105. It is located at the same height with respect to the upper surface.

Each pixel includes a pixel electrode connecting portion 108a for connecting a plurality of pixel electrodes 106. The pixel electrode connecting portion 108a is formed in the pixel electrode connecting portion forming groove 105c formed in the protective layer 105. The pixel electrode 106 is formed inside and connected to the drain electrode 104e of the thin film transistor 104 of the pixel through the contact hole 109 formed in the protective layer 105, so that the pixel electrode 106 is a drain electrode of the thin film transistor 104. To be connected to 104e.

Referring to FIG. 3, the alignment layer 110 is formed on the passivation layer 105 in which the pixel electrode 106 is formed in the pixel electrode forming groove 105a and the common electrode 107 is formed in the common electrode forming groove 105b. Is formed.

The alignment layer 110 is formed on a region formed on the region where the pixel electrode 106 is formed, on a region formed on the region where the common electrode 107 is formed, and on a region between the pixel electrode 106 and the common electrode 107. The regions are formed so that they do not form a step with each other and are positioned at the same height with respect to the upper surface of the first substrate 101, where the pixel electrode 106 and the common electrode 107 form pixel electrodes of the protective layer 105. Each of the grooves 105a and the common electrode forming groove 105b is formed so that the top surfaces of the pixel electrode 106 and the common electrode 107 are coplanar with the top surface of the protective layer 105, that is, the first substrate ( It is because it is formed so that it may exist in the position corresponding to the same height with respect to the upper surface of 101).

As such, the first substrate does not form a step between an area in which the alignment layer 110 overlaps with the pixel electrode 106 and the common electrode 107, and an area overlapping with the area between the pixel electrode 106 and the common electrode 107. When the upper surface of the 101 is formed at a position corresponding to the same height to form a plane, the pixel electrode 106, the common electrode 107, and the protective layer Rubbing is smoothly performed on all of the overlapping regions 105, in particular, the overlapping regions of the pixel electrodes 106 and the protective layer 105 and the boundary regions of the common electrode 107 and the protective layer 105. Rubbing on the region overlapping with is made smoothly.

Accordingly, in the alignment layer 110, all of the overlapping regions of the pixel electrode 106, the common electrode 107, and the protective layer 105 are rubbed in the same direction, so that light leakage due to poor rubbing occurs. Therefore, the display quality of the liquid crystal panel is improved.

Hereinafter, a method of manufacturing a liquid crystal display device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 3A to 3J.

First, a first substrate (see 101 in FIG. 4A) in which a plurality of pixels are defined is prepared.

Next, as shown in FIG. 4A, a thin film transistor 104 is formed in each pixel on the first substrate 101.

That is, a gate electrode 104a is formed on the first substrate 101, a gate insulating film 104b is formed on the gate electrode 104a, and a semiconductor layer 104c is formed on the gate insulating film 104b. The source electrode 104d and the drain electrode 104e are formed on the semiconductor layer 104c. In this case, the gate line 102 may be simultaneously formed when the gate electrode 104a is formed, and the data line 103 may be simultaneously formed when the source electrode 104d is formed.

Next, as shown in FIG. 4B, a protective layer 105 is formed on the first substrate 101 on which the thin film transistor 104 is formed in each pixel.

Next, after forming the photoresist film 111 on the protective layer 105 as shown in Figure 4c, by performing photolithography (photolithography) using a mask 112 provided with a diffraction region (112b) Figure 4d A first photosensitive film pattern 121 is formed as shown in FIG.

In this case, the mask 112 includes a pixel electrode forming groove (see 105a of FIG. 4G), a common electrode forming groove (see 105b of FIG. 4G) and a pixel electrode connecting portion forming groove (see 105c of FIG. 4G) to be formed in a later step. The region corresponding to the diffraction region 112b is provided, and the exposure region 112a is provided in the region corresponding to the contact hole (see 109 of FIG. 4E) to be formed in a later step. Here, the mask 112 may be opposite to the exposed area and the non-exposed area depending on the type of photoresist.

Accordingly, in the first photoresist pattern 121, an area corresponding to the exposed area 112a of the mask 112 is completely removed, and an area corresponding to the diffraction area 112b of the mask 112 is removed by a predetermined thickness. Has a shape.

Next, the protective layer 105 is selectively removed using the first photoresist pattern 121 to form a contact hole 109 as shown in FIG. 4E.

Accordingly, the contact hole 109 exposes a part of the drain electrode 104e of the thin film transistor 104.

Next, during photolithography using the mask 112 in which the diffraction region 112b is provided in the first photoresist pattern 121, the photoresist was subjected to diffraction exposure corresponding to the diffraction region 112b of the mask 112. All of the regions are removed to form the second photosensitive film pattern 131 as shown in FIG. 4F.

Next, the protective layer 105 is selectively removed using the second photoresist pattern 131, and the pixel electrode forming groove 105a, the common electrode forming groove 105b, and the pixel electrode connecting portion as shown in FIG. 4G are removed. Forming grooves 105c are formed.

In this case, the pixel electrode connector forming groove 105c formed in each pixel is connected to the plurality of pixel electrode forming grooves 105a formed in the pixel.

The pixel electrode forming groove 105a, the common electrode forming groove 105b, and the pixel electrode connecting portion forming groove 105c may be formed to have a thickness smaller than that of the protective layer 105.

Next, as shown in FIG. 4H, on the first substrate 101 having the pixel electrode forming groove 105a, the common electrode forming groove 105b, and the pixel electrode connecting portion forming groove 105c in the protective layer 105. The conductive material layer 113 is formed.

In this case, the conductive material layer 113 may be made of a transparent conductive oxide or an opaque metal, and one example of the transparent conductive oxide is indium tin oxide (ITO).

Next, by removing all of the second photoresist layer 131, the conductive material layer 113 is selectively removed to thereby remove the pixel electrode 106, the common electrode 107, and the pixel electrode connection 108 as shown in FIG. 4I. To form.

In this case, the upper surface of the pixel electrode 106 and the upper surface of the common electrode 107 form a plane with an area between the pixel electrode 106 and the common electrode 107 in the upper surface of the protective layer 105, respectively. The upper surface of is positioned at the same height with respect to the upper surface of the first substrate (101).

Next, as illustrated in FIG. 4J, an alignment layer 110 is formed on the first substrate 101 on which the pixel electrode 106, the common electrode 107, and the pixel electrode connection unit 108 are formed.

The alignment layer 110 may be formed on the region where the pixel electrode 106 is formed, on the region where the common electrode 107 is formed, and on the region between the pixel electrode 106 and the common electrode 107. It is formed so as to be at a position corresponding to the same height with respect to the upper surface of the first substrate 101 without forming a step with each other.

The process of forming the alignment layer 110 may be performed using polyimide or the like on the first substrate 101 on which the pixel electrode 106, the common electrode 107, and the pixel electrode connection unit 108 are formed. After forming the polymer thin film is formed by rotating a rubbing roll on the polymer thin film to form a predetermined orientation direction.

As described above, the region in which the alignment layer 110 overlaps with the pixel electrode 106 and the common electrode 107 and the region overlapping with the region between the pixel electrode 106 and the common electrode 107 do not form a first step. When the upper surface of the substrate 101 is formed at the same height to form a plane, the pixel electrode 106, the common electrode 107, and the protective layer during the rubbing operation of the alignment layer 110 using a rubbing roll or the like. Rubbing is smoothly performed on all of the overlapping regions 105, in particular, the overlapping region of the boundary between the pixel electrode 106 and the passivation layer 105 and the boundary of the common electrode 107 and the passivation layer 105. Rubbing on the area overlapping with the area is made smoothly.

Accordingly, in the alignment layer 110, both the region overlapping with the pixel electrode 106 and the common electrode 107 and the region overlapping with the region between the pixel electrode 106 and the common electrode 107 are uniformly in the same direction. Will be rubbed.

Therefore, light leakage due to poor rubbing caused by the level difference of the alignment layer 110 does not occur, thereby improving display quality of the liquid crystal panel.

1 is a cross-sectional view showing a conventional general liquid crystal display device.

2 is a plan view showing a liquid crystal display according to a preferred embodiment of the present invention.

3 is a cross-sectional view taken along the line II ′ of FIG. 2.

4A to 4J are cross-sectional views illustrating steps of manufacturing the liquid crystal display of FIG. 3.

** Description of the symbols for the main parts of the drawings **

101: first substrate 102: gate line

103: data line 104: thin film transistor

105: protective layer 106: pixel electrode

107: common electrode 108: pixel electrode connection portion

109 contact hole 110 alignment layer

112: mask

Claims (9)

A substrate formed by crossing a gate line and a data line with each other; A thin film transistor formed at an area where the gate line and the data line of each pixel of the substrate cross each other and having a gate electrode, a source electrode, and a drain electrode; A protective layer formed on the substrate on which the thin film transistor is formed; A plurality of pixel electrode formation grooves and common electrode formation grooves formed in an alternating manner in substantially parallel to each of the passivation layers of each pixel, and formed from an upper surface of the passivation layer to a lower portion of the passivation layer; A pixel electrode formed in the pixel electrode forming groove of each pixel, the upper surface of which is in plan with the upper surface of the protective layer; And A common electrode formed in the common electrode forming groove of each pixel, and having an upper surface formed in plane with the upper surface of the protective layer; Liquid crystal display device comprising a. The liquid crystal display of claim 1, wherein the pixel electrode forming groove and the common electrode forming groove have a thickness smaller than that of the passivation layer. The method of claim 1, wherein the alignment layer is further formed on the protective layer, And an area overlapping with the pixel electrode, an area overlapping with the common electrode, and an area overlapping with the area between the pixel electrode and the common electrode in the alignment layer are formed at the same height with respect to the upper surface of the substrate. The display device of claim 1, wherein each pixel further includes a pixel electrode connection portion connected to a plurality of pixel electrodes, and the pixel electrode connection portion is connected to a drain electrode of the thin film transistor through a contact hole formed in a protective layer. And a pixel electrode connection groove forming groove in which the pixel electrode connection portion is formed in the passivation layer of each pixel. 5. The liquid crystal display device according to claim 4, wherein the pixel electrode connecting portion forming grooves in each pixel are formed to be connected to at least one of the plurality of pixel electrode forming grooves. Providing a substrate on which a plurality of pixels are defined, each pixel having a thin film transistor comprising a gate electrode, a source electrode, and a drain electrode; Forming a protective layer on the substrate on which the thin film transistor is formed; The protective layer is removed by a thickness equal to the thickness of the protective layer to form a contact hole exposing a part of the drain electrode of the thin film transistor, and the protective layer is removed by a thickness smaller than the thickness of the protective layer, thereby substantially in each pixel. Forming a plurality of pixel electrode forming grooves and common electrode forming grooves alternately arranged in parallel; Forming a pixel electrode in the pixel electrode forming groove and forming a common electrode in the common electrode forming groove, wherein the upper surface of the pixel electrode, the upper surface of the common electrode, and the upper surface of the protective layer form a plane together; And Forming an alignment layer on the substrate on which the pixel electrode and the common electrode are formed; Method of manufacturing a liquid crystal display device comprising a. The pixel electrode connection grooves of claim 6, wherein the pixel electrode connection grooves are formed together with the pixel electrode formation grooves. When the pixel electrode is formed in the pixel electrode formation groove, the pixel electrode connection portion is also formed in the pixel electrode connection formation groove. The method of claim 6, wherein the forming of the plurality of pixel electrode forming grooves and the common electrode forming grooves for each pixel, and the forming of the pixel electrode and the common electrode, Forming a photoresist film on the protective layer; The first photoresist film is formed by performing photolithography using a mask in which a diffraction region is provided in a region corresponding to a pixel electrode forming groove and a common electrode forming groove to be formed later, and an exposure region is provided in a region corresponding to a contact hole to be formed later. Forming a pattern; Selectively removing a protective layer using the first photosensitive film to form a contact hole; Removing a region of the first photoresist pattern corresponding to the diffraction region of the mask to form a second photoresist pattern; Selectively removing the passivation layer using the second photoresist pattern to form pixel electrode forming grooves and common electrode forming grooves; Forming a conductive material layer on the second photosensitive film; And Removing the second photoresist to form a pixel electrode and a common electrode; Method of manufacturing a liquid crystal display device comprising a. The method of claim 8, wherein the conductive material layer is formed of indium tin oxide (ITO).

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