KR20090098341A - Polycrystalline metal oxide nanobelt network based field effect transistor and fabrication method of the same - Google Patents

Abstract

A field effect transistor using a polycrystalline metal oxide semiconductor layer and a manufacturing method thereof are provided to improve electrical reliability and reactivity by using a thin metal-oxide layer as an active layer. A gate electrode(12), a gate insulating layer(13), a metal oxide semiconductor layer, a source electrode(15a) and a drain electrode(15b) are formed on a substrate(11). The metal oxide semiconductor layer has a poly-crystal nano belt structure or a poly-crystal nano belt network structure in which a nano wire network is compressed. The metal oxide semiconductor layer has the width of 0.5~3 micron and the thickness of 20 ~ 100 nm. The metal oxide semiconductor layer is made of the nano grain or the nano particle of 5 ~ 20 nm size. The metal oxide semiconductor layer includes ZnO. The metal oxide semiconductor layer includes SnO2.

Description

Field effect transistor using polycrystalline metal oxide semiconductor layer and its manufacturing method {Polycrystalline Metal Oxide Nanobelt Network Based Field Effect Transistor and Fabrication Method of the same}

The present invention relates to a field effect transistor using a polycrystalline metal oxide semiconductor layer and a method of manufacturing the same, and more particularly, to heat an individual composite nanowire or a composite nanowire network generated by spinning a mixed solution containing a polymer and a metal salt precursor. The present invention relates to a field effect transistor configured to form a thin metal oxide layer having a nanobelt structure or a nanobelt network (mat) structure by compression and heat treatment, and to utilize the thin metal oxide layer as an active layer and a method of manufacturing the same.

Recently, development of transistors using nanowires (nanowires, nanofibers) as semiconductor active layers has been actively conducted. Single crystal nanowire transistors are based on the characteristics of high electron mobility (determining how fast a transistor can operate and how much current it can carry), ring oscillators, memory devices Application to back is possible. In addition, these nanowire-based transistors are highly responsive to external stimuli (gas / biomolecules) and thus can be used as gas sensors, humidity sensors, UV detectors, and DNA sensors. This is because, unlike thin film or bulk transistors, the surface area / volume ratio is very large when using nanowires. Thus, fine surface interactions can be signaled, enabling detection of single molecules. In addition, the nanowire transistor is relatively easy to control the type (n-type / p-type) of the semiconductor relatively easily by controlling the doping and the composition ratio of the semiconductor.

In the production of such nanowires, various applications such as the case of using existing carbon nanotubes, metal semiconductor nanowires such as Si, and metal oxide-based nanowires are possible. In particular, metal oxide semiconductor nanowires such as ZnO, SnO ₂ and In ₂ O ₃ have been actively studied for various applications because they can be used as active layers of transistors [HT Ng et al, Nano Letters Vol 4, 1247-1252, 2004 (using single crystal ZnO); YW Heo et al, Applied Physics Letters Vol 85, 2274-2276, 2004 (using single crystal ZnO); F. Liu et al, Applied Physics Letters Vol. 86, 213101, 2005 (using single crystal In ₂ O ₃ ); SH Ju et al, Applied Physics Letters Vol 89, 193506, 2006 (using single crystal ZnO)].

Recently, in consideration of the low reproducibility, contact problems, and assembly problems of individual single crystal nanowire fabrication, studies using a network of nanowires instead of individual single crystal nanowires have been reported [EN Dattoli et al. , Nano Letters Vol 7, 2463-2469, 2007]. In this case, too, SnO ₂ single crystals are grown for a long time, and a network-based transistor is introduced. However, since the process temperature for manufacturing such a single crystal is obtained by heat treatment at a temperature of 900 ° C. or more in a furnace for about 1 hour [Nano Letters Vol 7, 2463-2469, 2007], it may be restricted in practical use. .

In addition, in relation to nanowire-based electronic devices, transistor-based logic circuits [Korean Patent No. 593257], multi-gate field effect transistors using round silicon nanowires [Korean Patent No. 593 969], nanowire-based sensors and transistors [ Although a number of patents have been introduced, such as US Patent Nos. 7129554 and 7301199, most of them are based on metal oxide semiconductors of single crystal Si nanowires, carbon nanotubes, or single crystals.

However, although many documents have introduced excellent features as mentioned above, the occurrence of large-scale market is not well occurring, but the process of manufacturing nanosensor material or nanosensor device is still present in view of reproducibility and assembly. Because it is very difficult at the stage.

In particular, various studies have been conducted to manufacture metal oxide-based nanowires, but in order to manufacture robust transistors, various problems such as reproducibility, contact issues, and assembly must be solved first. In addition, the growth temperature of nanowire is not high below 500 ℃, so it can be easily combined with semiconductor process, greatly reduce the production rate and production cost required for nanowire synthesis, and require a manufacturing process technology capable of mass production of large area. It is becoming.

Therefore, the present invention is invented to solve the above problems,

Firstly, an object of the present invention is to provide a field effect transistor using a metal oxide based nanobelt / nanobelt network having a polycrystalline structure composed of nanograins or nanoparticles and a method of manufacturing the same.

Second, by using a metal oxide nano belt / nano belt network having a polycrystalline structure as an active channel, an object of the present invention is to provide a transistor that is excellent in electrical stability, and the specific surface area of the active layer is increased to improve reactivity.

Third, an object of the present invention is to provide a transistor device having high electrical, mechanical, and thermal stability by improving adhesion between a metal oxide nanobelt / nanobelt network having a polycrystalline structure and a gate insulating film.

Fourth, an object of the present invention is to enable a transistor based on a metal oxide nanobelt / nanobelt network of a polycrystalline structure to be used in a gas sensor, a biosensor, a UV detector, or the like.

In order to achieve the above object, the present invention provides a field effect transistor comprising a substrate, a gate electrode, a gate insulating film, a metal oxide semiconductor layer, a source electrode and a drain electrode,

The metal oxide semiconductor layer,

The semiconductor layer includes a polycrystalline metal oxide layer comprising a thin metal oxide layer composed of nanograins or nanoparticles and having a polycrystalline nanobelt structure in which individual nanowires are compressed or a polycrystalline nanobelt network structure in which a nanowire network is compressed. A field effect transistor is provided.

In addition, the present invention is a method of manufacturing a field effect transistor comprising a substrate, a gate electrode, a gate insulating film, a metal oxide semiconductor layer, a source electrode and a drain electrode,

A gate insulating film is formed on the substrate on which the gate electrode is formed, and then a source electrode and a drain electrode are formed, and then a semiconductor layer having a polycrystalline nanobelt structure or a polycrystalline nanobelt network structure composed of nanograins or nanoparticles, or nanograins or nanoparticles is formed. After forming the semiconductor layer of the polycrystalline nano belt structure or nano belt network structure consisting of particles to form a source electrode and a drain electrode,

Forming the semiconductor layer of the polycrystalline nano belt structure or polycrystalline nano belt network structure,

Spinning a mixed solution comprising a polymer and a metal salt precursor to produce an individual composite nanowire or a composite nanowire network in which the polymer and the metal salt precursor are mixed;

Nanobeltting the polymer / metal salt composite nanowire or composite nanowire network by thermocompression or thermopressurization;

Then, the nanobelt is heat-treated to remove the polymer and oxidize the metal salt, thereby forming a metal oxide layer having a polycrystalline nanobelt structure in which individual composite nanowires are compressed, or a polycrystalline nanobelt network in which the composite nanowire network is compressed. Forming a metal oxide layer of a structure;

It provides a method for manufacturing a field effect transistor using a polycrystalline metal oxide semiconductor layer comprising a.

Accordingly, according to the field effect transistor using the polycrystalline metal oxide semiconductor layer of the present invention and a method for manufacturing the same, an individual composite nanowire (nanofiber) or composite nanowire produced by spinning a mixed solution containing a polymer and a metal salt precursor Thermal compression or thermal pressurization of the network followed by heat treatment to remove the polymer and oxidize the metal salt to form a thin metal oxide layer of nanobelt structure or nanobelt network (mat) structure, and the metal of the nanobelt structure or nanobelt network structure Since the oxide thin layer is configured to be used as an active layer (semiconductor layer), it is possible to provide a field effect transistor having excellent electrical stability and greatly increasing the specific surface area of the active layer.

In addition, by easily adjusting the type and mixing ratio of the metal salt used, it is possible to provide a transistor manufacturing process that can use the semiconductor layer of the nano belt or nano belt network structure of various metal oxides as the channel layer.

In addition, based on the transistor characteristics of the present invention having excellent electrical stability, it is possible to manufacture and apply a transistor-based sensor having excellent reactivity.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

First, a method of manufacturing a nanowire, a nanobelt and a nanobelt network according to the present invention will be described in detail.

In the present invention, the metal oxide nanobelt and the nanobelt network are manufactured by spinning a solution in which a metal salt precursor is dissolved in a polymer solution having a high viscosity by electrospinning or the like to produce a composite nanowire and belting it. A process, for example, thermocompression or thermopressing at a temperature higher than the glass transition temperature of the polymer used, and then heat treatment at a temperature of 400 ℃ or more. Here, the electrospinning may yield a nanowire structure in the form of individual nanowires or nanowire networks (where the nanowires are entangled in a network structure), and the electrospinning solution for obtaining such nanowires and nanowire networks may be obtained. The polymer is obtained by dissolving the polymer substrate and the metal salt precursor in a solvent such as water, ethanol, THF (Tetrahydrofuran), DMF (Dimethylformamide), DMAc (Dimethylacetamide), and toluene.

The mixed solution including the polymer and the metal salt precursor, that is, the electrospinning solution, preferably has a viscosity suitable for forming a nanowire to a nanowire network on the gate insulating film, that is, the gate insulating film formed on the patterned gate electrode during electrospinning. Thermosetting and thermoplastic resins may be used as the polymer. For example, at least one of olefin polymers such as polymethyl methacrylate (PMMA), polyvinylpyrrolidone (PVP), polyvinylacetate (PVAc), polyvinyl alcohol (PVA), polystyrene (PS) and the like can be selected. Can be.

As the metal salt, zinc salt (zinc chloride, zinc acetate, zinc sulfate, zinc nitrate, zinc bromide, etc.), indium salt (indium chloride, indium acetate, indium sulfate, indium nitrate, etc.), gallium salt (gallium chloride, gallium acetate, Gallium sulfate, gallium nitrate, and the like), tin salts (tin chloride, tin acetate, tin sulfate, tin nitrate, tin bromide, etc.), and the like, and salts selected from these may be used. Thus, the above-mentioned polymer and metal salts can be used to form the above-mentioned polymer / metal salt individual composite nanowires or composite nanowire networks on the gate insulating film.

The individual composite nanowires or composite nanowire networks thus formed are subjected to heat treatment to thermocompression / heat treatment to form thin metal oxide layers or nanobelts having individual nanobelt structures having a width of about 1 to 3 μm and a thickness of 20 to 50 nm. It is possible to manufacture a thin layer of nanobelt network structure forming a network structure. In the transistor according to the present invention, as the metal oxide semiconductor layer (active layer), it is preferable to manufacture a metal oxide thin layer of nanobelt or nanobelt network structure having a width of 0.5 to 5 μm and a thickness of 10 to 100 nm. More preferably, as a metal oxide semiconductor layer (activation layer), it is preferable to form a thin metal oxide layer having a nanobelt structure or a nanobelt network structure having a width of 1 to 3 μm and a thickness of 20 to 50 nm for smooth device operation. .

In the manufacturing process of the metal oxide semiconductor layer (active layer) of the transistor according to the present invention, by belting individual composite nanowires or composite nanowire networks only through heat treatment, the nanobelt structure or nanobelt network in which the polymer is removed and the metal salt is oxidized The semiconductor layer of the structure can be prepared [heat treatment without thermocompression bonding], and more preferably, the nanowire or nanowire network is made into a nanobelt structure through a thermocompression process, followed by heat treatment of the nanobelt, thereby removing polymers and metal salts. A semiconductor layer of this oxidized nanobelt structure or nanobelt network structure can be produced (heat treatment after thermocompression bonding).

Here, when the heat treatment process for manufacturing the semiconductor layer, the used polymers are decomposed and removed, and the metal salts are oxidized, and the nanobelt or nanobelt network structure of ZnO, SnO ₂ , In ₂ O ₃ , Ga ₂ O _3, etc. A thin metal oxide layer can be made.

Hereinafter, in the present specification, the individual composite nanowires formed by spinning a mixed solution containing a polymer and a metal salt are thermally compressed (or thermally pressurized) and then thermally treated to remove the polymer, and the individual composite nanowires form a belt. The compressed structure is referred to as a nano belt.

In addition, in the present specification, a composite nanowire network in which a composite nanowire forms a network structure by spinning a mixed solution containing a polymer and a metal salt, is thermally compressed (or thermopressed), and then heat treated, thereby removing the polymer and the composite na The structure in which the route network is compressed in the form of a belt and the whole nanobelt forms a network structure will be referred to as a nanobelt network or a nanobelt mat or simply a nanomat (hereinafter, referred to as a nanobelt network).

In short, the nanobelt is a nanostructure (which forms a thin layer) in which individual composite nanowires are pressed and heat-treated to form a belt, and the nanobelt network is entangled with a composite nanowire network (nanowires forming a network). ) Is a nanostructure (which forms a thin layer) in which a belt (each composite nanowire is belted) forms a network structure by thermal compression and heat treatment.

In addition, depending on the material, by simply heat-treating individual composite nanowires or composite nanowire networks without thermocompression bonding, the composite nanowires can spread sideways to form a belt structure. It is possible to form a thin metal oxide layer of a belt or belt network structure only by heat treatment, and such a thin metal oxide layer can be formed as a semiconductor layer of a transistor. Of course, at this time, the polymer is removed by the heat treatment and the metal salt is oxidized to form a thin metal oxide layer which is a desired semiconductor layer in the transistor.

The metal salt precursor mixed with the polymer substrate is adjusted to the equivalent ratio of the metal salt precursor to be used, such as the metal oxide of In _a Ga _b Zn _c Sn _d O _x (0 ≦ a, b, c, d), to form a new metal having a desired composition ratio. Oxides can be made and used. Any combination of the a, b, c, and d may be allowed. For example, InGaZnO ₄ , Zn ₂ SnO ₄ , In ₂ Zn ₃ O ₆ , ZnGa ₂ O ₄ , InGaO _3, and the like may be used, and the selection of the characteristic composition ratio is not limited. In the transistor of the present invention, the metal oxide semiconductor layer may be a thin metal oxide layer of nanobelt or nanobelt network structure composed of ZnO doped with at least one element of Al and Ga, or ZnRh ₂ O ₄ , SrCu ₂ O ₂ or It may be a nanobelt or a thin metal oxide layer of a nanobelt network structure composed of a p-type metal oxide of CuO. Of course, as long as it can form the nanobelt and nanobelt network of the metal oxide described above in the metal salt precursor is not limited to a specific precursor.

The polymer is brought to 8 to 15 wt% of the solvent volume and the amount of metal salt precursor is to be 10 to 25 wt% of the solvent volume. According to an embodiment of the present invention, acetic acid, which serves to promote evaporation of the solvent during electrospinning, is added to the polymer / metal salt precursor solution in the same molar amount as the metal salt precursor.

When the semiconductor layer is subjected to a thermocompression (or thermocompression) process, the nanowire or the nanowire network is melted to nanobelt as a whole, and the adhesion property with the gate insulating layer underneath is greatly improved. At this time, the polymer of the composite nanowire is melted in part or the whole by applying a pressure at a temperature higher than the glass transition temperature to increase the adhesive strength.

As such, the nanowire or nanowire network on the gate insulating film is formed into a belt structure through a thermocompression bonding process, and then the metal nanoparticles are oxidized while removing the polymer through the above heat treatment process to form a final nanobelt or nanobelt network structure. You can get it. The nanobelt and the nanobelt network obtained through the electrospinning technique have a polycrystalline structure, which is present in the form of fine nanograins or nanoparticles, thereby greatly increasing the surface area. Due to the expansion of the reaction area according to the increase in the surface area, it may have an advantage that the reactivity with the gas and the biomaterial may be greatly increased.

In the process of manufacturing the semiconductor layer, instead of thermocompression pressing at the same time applying heat, a thermopressing process of inducing melting of the polymer by pressurizing using compressed air having a temperature above the glass transition temperature of the polymer may be used.

Looking at the manufacturing process of the transistor constituting the polycrystalline nano belt and nano belt network (matte) including the nano-grain or nanoparticles of the present invention as a semiconductor layer in detail.

1A and 1B are cross-sectional views illustrating a structure of a field effect transistor 10 including a metal oxide nano belt and a metal oxide nano belt network according to an embodiment of the present invention. Reference numeral 11 denotes a substrate, reference numeral 12 denotes a gate electrode, reference numeral 13 denotes a gate insulating film, reference numeral 14a denotes a metal oxide nanobelt semiconductor layer, and reference numeral 14b denotes a metal oxide nanobelt network semiconductor layer, respectively. Indicates. Reference numeral 15a denotes a source electrode and 15b denotes a drain electrode.

In order of the substrate 11 / gate electrode 12 / gate insulating film 13 / polycrystalline metal oxide nano belt or nano belt network 14b / source electrode and drain electrode 15a, 15b according to an embodiment of the present invention In the case of a field effect transistor device having a stacked structure is manufactured through the following steps.

1) In order to form the gate electrode 12, a step of forming a thin film for the gate electrode layer on the substrate 11 and patterning is performed. An N ++ Si backgate can be used as in the embodiment of the present invention described below.

2) thereafter, the step of forming the gate insulating layer 13 on the gate electrode 12 formed as described above. In the present invention, a SiO ₂ insulating film having a thickness of 100 nm may be used.

3) Thereafter, the metal oxide nanobelt 14a or the metal oxide nanobelt network 14b is formed on the gate insulating layer 13 formed as described above, and then patterned. In the present invention, the nanobelt and the nanobelt network may be patterned using a shadow mask.

4) After the metal oxide nanobelt 14a or the metal oxide nanobelt network 14b is formed, the source electrode 15a and the drain electrode 15b are formed.

In the above process, it is possible to form the source electrode and the drain electrode, and then form the polycrystalline metal oxide nanobelt or polycrystalline metal oxide nanobelt network. That is, the field effect transistor device may be configured in a stacked structure of a substrate / gate electrode / gate insulating film / source electrode and drain electrode / polycrystalline metal oxide nanobelt or nanobelt network.

In the above process, the gate, source, and drain electrodes may be made of Al, Au, Cr, Ti, Pt, ITO (In doped SnO ₂ ), or the like.

A field effect transistor including a polycrystalline metal oxide nano belt and a metal oxide nano belt network formed according to an embodiment of the present invention as a semiconductor layer may be specifically manufactured according to the following procedure. In the following embodiments, the electrospinning method is used as a method of easily obtaining a composite nanowire or a composite nanowire network structure, but the present invention is not limited thereto. For example, melt-blown and flash spinning may be used. spinning, electrostatic melt-blown, etc. may be used.

Example 1: 4-component nano InGaZnO ₄ and InGaZnO belt for producing a field effect transistor using a ₄ nm belt network

As an embodiment of the present invention, a transistor using an InGaZnO ₄ nanobelt and an InGaZnO ₄ nanobelt network (matt) as a semiconductor layer includes an excess of polyvinyl acetate, indium chloride, gallium chloride, zinc acetate dihydrate, SiO ₂ gate insulating film, and impurities. A doped silicon wafer (substrate) was produced using an aluminum electrode.

First, 1.09 g (5 mmol) of zinc acetate dihydrate, 1.109 g (5 mmol) of indium chloride, and 0.88 g (5 mmol) of gallium chloride are dissolved in 7.5 g of DMF (Dimethylformamide). Then, 1.5 g of polyvinyl acetate (molecular weight: 1 million) is dissolved in 7.5 g of DMF, and the two solutions are mixed and stirred for 10 minutes. Then, 1 g of acetic acid was added to the solution, followed by stirring for 5 minutes.

The solution thus prepared is filled in a 20 ml syringe pump and slowly ejected (10 ml / min) to electrospinning (humidity: 30%, available voltage: 12.5 kV, ambient temperature: 31 ° C). By reaction, polyvinylacetate / indium chloride, gallium chloride, a zinc acetate dihydrate composite nanowire in solid form can be obtained.

The nanobelt can then be obtained using a few strands of these individual composite nanowires. That is, a few strands of the composite nanowires are placed on a substrate (n ++ Si / SiO ₂ ) on which a SiO ₂ thin film (which is a gate insulating film) is deposited at 100 nm on a silicon wafer over-doped with impurities, and the resultant is 500 to 800 ° C. InGaZnO ₄ nanobelt can be obtained by heat-treating and belting for 40 minutes at [heat treatment without thermocompression bonding].

After the mask is put on, the transistor may be configured by depositing 100 nm of aluminum using an e-beam evaporator to form a source electrode and a drain electrode.

Next, when fabricating an InGaZnO ₄ nanobelt network (matt) based transistor, 100 μl of polyvinylacetate / indium chloride, gallium chloride, and zinc acetate dihydrate composite nanowires were formed on a n ++ Si / SiO ₂ substrate as a network structure. After raising, press with a pressure of at least 0.1MPa at 120 ℃ using a lamination machine to make a nanobelt structure, and the resultant is heat treated at 500 to 800 ℃ for 40 minutes to obtain a nanobelt network structure. Heat treatment]. By masking and depositing 100nm of aluminum using an electron beam evaporator to form a source electrode and a drain electrode, an InGaZnO ₄ nanobelt network-based transistor can be made.

Example 2 Fabrication of Field Effect Transistor Using Three-Component Zn ₂ SnO ₄ Nanobelt and Zn ₂ SnO ₄ Nanobelt Network

As an embodiment of the present invention, a transistor using a Zn ₂ SnO ₄ nanobelt and a nanobelt network (matte) as a semiconductor layer includes a polyvinylacetate, zinc acetate, tin acetate, a SiO ₂ gate insulating film, a silicon wafer over-doped with impurities, It prepared using the aluminum electrode.

First, 1.77 g of tin acetate and 2.195 g of zinc acetate are dissolved in 7.5 g of DMF (dimethylformamide). Then, 1.5 g of polyvinyl acetate (molecular weight: 1 million) is dissolved in 7.5 g of DMF, and the two solutions are mixed and stirred for 10 minutes. Then, 1 g of acetic acid was added to the solution, followed by stirring for 5 minutes.

The solution thus prepared is filled in a 20 ml syringe and slowly ejected (10 ul / min) to electrospinning (humidity: 30%, available voltage: 10.1 kV, ambient temperature: 31 ° C). Polyvinylacetate / zinc acetate, tin acetate composite nanowires can be obtained.

The nanobelt can then be obtained using a few strands of these individual composite nanowires. That is, the composite nanowires are raised on a substrate (n ++ Si / SiO ₂ ) on which a SiO ₂ thin film is deposited at 100 nm on a silicon wafer over-doped with impurities, and the resultant is heat-treated at 500 to 900 ° C. for 40 minutes. By belting, ZnO ₂ SnO ₂ nanobelts can be obtained.

The transistor can be configured by putting a mask on it and depositing 100 nm of aluminum using an electron beam evaporator to form a source electrode and a drain electrode.

Next, when fabricating a Zn ₂ SnO ₄ nanobelt network (matte) based transistor, 100 μl of polyvinylacetate / zinc acetate and tin acetate composite nanowires were formed on a n ++ Si / SiO ₂ substrate and then raised in a network structure. The thermocompressor is pressed to a pressure of at least 0.1 MPa at 120 ° C. to form a nanobelt structure, and the resultant is heat-treated at 500 to 900 ° C. for 40 minutes to obtain a nanobelt network structure. A source / drain mask is deposited on the source / drain mask and 100 nm of aluminum is deposited using an electron beam evaporator to form a source electrode and a drain electrode to form a Zn ₂ SnO ₄ nanobelt network-based transistor.

Example 3 Fabrication of Field Effect Transistors Using ZnO Nanobelt and ZnO Nanobelt Network

As an embodiment of the present invention, a transistor using a ZnO nanobelt and a ZnO nanobelt network (matte) as a semiconductor layer includes a polyvinylacetate, zinc acetate dihydrate, SiO ₂ gate insulating film, and a silicon wafer (back gate electrode) overdoped with impurities. Used), aluminum source and drain electrode.

First, 3.285 g (15 mmol) of zinc acetate dihydrate is dissolved in 7.5 g of dimethylformamide (DMF). Then, 1.5 g of polyvinylacetate (molecular weight: 1 million) is dissolved in 7.5 g of DMF, and the two solutions are mixed and stirred for 10 minutes. Then, add 1 g of acetic acid to the solution and stir again for 5 minutes.

The solution thus prepared is filled into a 20 ml syringe, and slowly ejected (10 ul / min) by electrospinning (humidity: 30%, available voltage: 11 kV, ambient temperature: 31 ° C). Polyvinylacetate / zinc acetate dihydrate nanowires can be obtained.

The nanobelt can then be obtained using a few strands of these individual composite nanowires. That is, a few strands of the nanowires are deposited on a substrate (n ++ Si / SiO ₂ ) on which a SiO ₂ thin film is deposited at 100 nm on a silicon wafer over-doped with impurities, and the resultant is heat-treated at 550 ° C. for 40 minutes. The polymers deform and decompose while spreading over the gate insulating film, and after the final heat treatment, ZnO nanobelts can be obtained as shown in the lower part of FIG. 6.

The transistor can be configured by putting a mask on it and depositing 100 nm of aluminum using an electron beam evaporator to form a source electrode and a drain electrode. In some cases, a shadow mask may be used, or may be patterned through photolithography.

Next, in the fabrication of ZnO nanobelt network (matt) based transistors, 100 μl of polyvinylacetate / zinc acetate dihydrate nanowires were formed in a network structure on an n ++ Si / SiO ₂ substrate, and then raised to 120 ° C. using a thermocompressor. After pressing at a pressure of 0.1 MPa or more at, the resultant was heat-treated at 550 ° C. for 40 minutes to obtain a metal oxide semiconductor layer having a nanobelt network structure. In particular, it is possible to obtain the thickness of the semiconductor layer which is the easiest for the flow of carriers in the presence of an electric field in the presence of an electric field in the thermal compression process. ZnO nanobelt network-based transistors can be made by placing a source / drain mask and depositing 100 nm of aluminum using an electron beam evaporator to form source electrodes and drains.

Similar principles apply to the fabrication of the various metal oxide semiconductor nanobelts and nanobelt network based transistors described below.

Example 4 Fabrication of Field Effect Transistors Using In ₂ O ₃ Nano Belt and In ₂ O ₃ Nano Belt Network

In the present invention, In ₂ O ₃ nano-belts and In ₂ O ₃ nano belt network (mat), a transistor using a semiconductor layer, a polyvinyl acetate and chloride, indium, SiO ₂ gate insulation film, the impurity is over-doped silicon wafer, an aluminum electrode It was prepared using.

First, 3.327 g (15 mmol) of indium chloride is dissolved in 15 g of dimethylformamide (DMF). Thereafter, 1.5 g of polyvinylacetate (molecular weight: 1 million) is dissolved in an indium chloride / DMF solution. Add 1 g of acetic acid to this solution and stir again for 5 minutes.

The solution thus prepared is filled into a 20 ml syringe and slowly ejected (10 ml / min) by electrospinning (humidity: 30%, available voltage: 13 kV, ambient temperature: 31 ° C.). The polyvinylacetate / indium chloride nanowire of can be obtained.

The nanobelt can then be obtained using a few strands of these individual composite nanowires. That is, the nanowires, when the impurity is over the SiO ₂ film on the doped silicon wafer over 100nm deposition substrate (n ++ Si / SiO _2), oligonucleotide a few strands, this results in 550 ℃ 40 bungan heat treatment In ₂ O ₃ Nano belts can be obtained.

The transistor can be constructed by putting a mask on it and depositing 100 nm of aluminum using an electron beam evaporator to form a source / drain electrode.

Next, when fabricating an In ₂ O ₃ nanobelt network (matt) based transistor, 100 μl of polyvinylacetate / indium chloride nanowires were formed on a n ++ Si / SiO ₂ substrate as a network structure, and then, 120 was heated by a thermocompressor. After pressing at a pressure of 0.1 MPa or more at 占 폚, the resultant was heat-treated at 550 占 폚 for 40 minutes to obtain a nanobelt network structure. By masking and depositing 100nm of aluminum using an electron beam evaporator to form a source electrode and a drain electrode, an In ₂ O ₃ nanobelt network-based transistor can be made.

Example 5: Preparation of a field effect transistor using a SnO ₂ and SnO ₂ Nano Nano belt belt network

A transistor SnO ₂ and SnO ₂ Nano Nano belt belt network in the present invention using the semiconductor layer is a polyvinyl acetate with tin acetate, SiO ₂ gate insulation film, an impurity was prepared using a silicon wafer, an aluminum electrode doping excess.

First, 3 g of tin acetate is dissolved in 7.5 g of dimethylformamide (DMF). Then, 1.5 g of polyvinylacetate (molecular weight: 1 million) is dissolved in 7.5 g of DMF, and the two solutions are mixed and stirred for 10 minutes. Add 1 g of acetic acid to the solution and stir again for 5 minutes.

The solution thus prepared is filled into a 20 ml syringe and slowly ejected (10 ml / min) to electrospinning (humidity: 30%, usable voltage: 9.5 kV, ambient temperature: 31 ° C). Polyvinylacetate / tin acetate composite nanowires can be obtained.

The nanobelt can then be obtained using a few strands of these individual composite nanowires. That is, a few strands of the composite nanowires are placed on a substrate (n ++ Si / SiO ₂ ) on which a SiO ₂ thin film is deposited 100 nm on a silicon wafer over-doped with impurities, and the resultant is heat-treated at 550 ° C. for 40 minutes for SnO ₂ nano. You can get a belt.

The transistor can be configured by putting a mask on the film and depositing 100 nm of aluminum using an electron beam evaporator to form a source electrode and a drain electrode.

Next, in the production of SnO ₂ nanomats transistor, 100 μl of polyvinylacetate / tin acetate composite nanowires were formed on a n ++ Si / SiO ₂ substrate in a network structure, and then raised, 0.1MPa (0.05) at 120 ° C. using a thermocompressor. After pressing under a pressure of kgf / cm 2), the resultant is heat-treated at 550 ° C. for 40 minutes to obtain a nanobelt network structure. A source / drain mask can be put on it, and 100 nm of aluminum is deposited using an electron beam evaporator to form a source electrode and a drain electrode, thereby forming a SnO ₂ nanobelt network-based transistor.

Hereinafter, the characteristics of the field effect transistor including the nanobelt and the nanobelt network (mat) formed by using the electrospinning according to the present invention will be described based on specific results.

2A and 2B are typical scanning electron microscope (SEM) images shown after electrospinning of a polymer / metal salt composite nanowire. According to the type of metal salt precursor used in the polymer / metal salt composite nanowire network shown in FIG. 2A, various metal oxide nanobelt networks may be manufactured after heat treatment.

Figure 2a shows a metal salt precursor (tin acetate) / polyvinylacetate composite nanowire network prepared through Example 5, Figure 2b is a metal salt precursor (tin acetate) / polyvinylacetate composite nanowire network thermocompressor ( SEM photograph obtained after pressing by applying 0.1MPa (0.05kgf / cm 2) pressure at 120 ° C with lamination machine). It can be seen that in the thermocompression bonding, the polymer having a low glass transition temperature is partially or entirely melted to form a network connected to each other.

2A and 2B show a comparison of the belted state after thermocompression from the state before thermocompression in a two-component SnO ₂ / PVAc system. This phenomenon can be applied not only to two-component systems, but also to all systems such as three-component systems and four-component systems. 2A and 2B conceptually show that it is possible to nanobelt by thermocompressing a polymer / metal salt nanowire network.

Figure 3a is InGaZnO ₄ prepared through Example 1 SEM image of the nanobelt network. An indium-gallium-zink precursor (zinc acetate dihydrate, indium chloride, gallium chloride) / polyvinylacetate composite nanowire network was subjected to 100 μl on the gate insulating film by electrospinning, and then a lamination machine was used. Thermocompression is performed at higher glass transition temperatures than the polymer used. In this embodiment, the press was applied by applying a pressure of 0.1 MPa (0.05 kgf / ㎠) at 120 ℃. In this case, the composite nanowire having a diameter of 200 to 600 nm is nanobelt through thermal compression, the polymer is decomposed through high temperature heat treatment (400 to 800 ° C.), and the metal salt is oxidized, thereby InGaZnO ₄ nanobelt. It will form a network (mat).

In FIG. 3A, when 100 μl of the electrospinning and heat treatment were performed, the surface coverage of about 45% was confirmed. Therefore, the actual operating area of the semiconductor channel layer may be adjusted by adjusting the amount of electrospinning. In the case of the InGaZnO ₄ nanobelt network, which is heat-treated by thermal compression, the polycrystalline properties are also shown, and a semiconductor channel composed of nanograins or nanoparticles having a size of about 5 to 20 nm can be formed depending on the heat treatment temperature conditions. have.

In particular, Zn ₂ SnO ₄ nanobelt network, ZnO nanobelt network, In as shown in Figures 3b, 3c, 3d and 3e through the selection of the metal salt precursor used and the appropriate selection of the metal salt precursor and the polymer that melts well ₂ 0 ₃ nanobelt networks and SnO ₂ nanobelt networks can be prepared. The nanobelt networks of FIGS. 3B, 3C, 3D, and 3E are made through the nanobelt network manufacturing process of Examples 2, 3, 4, and 5, respectively.

FIG. 4A is an SEM image of InGaZnO ₄ nanobelts prepared in Example 1. FIG. (Zinc acetate dihydrate, gallium chloride, indium chloride) / polyvinylacetate When the individual nanowires are fabricated on the gate insulating film, the phenomenon of spreading on some gate insulating film due to the low glass transition temperature of the polyvinyl acetate is observed (Fig. 6). Reference). When the heat treatment is performed at a temperature of about 500 ° C., before the polymer is decomposed at a high temperature, the polymer is partially or completely melted during the temperature rising process, and the thickness of the belt is about 20 to 50 nm, and the width is as shown in the lower part of FIG. 6. It spreads wider than the original composite nanowires to form about 1 to 3 μm (in the present invention, this is referred to as nanobelt). In addition, it is also possible to make individual nanobelts through heat treatment after thermal compression and thermocompression on individual composite nanowires.

In FIG. 4a, it can be seen that individual InGaZnO ₄ nanobelts having a width of 1.2 μm and a thickness of 30 nm are formed. In particular, the InGaZnO ₄ nanobelts thus formed have a single crystal characteristic compared to the metal oxides produced by laser ablation method, VLS (Vapor-Liquid-Solid) process, and thermal evaporation method. There is a fundamental difference in that it is composed of a polycrystalline structure. Through this, excellent surface reactivity of the metal oxide semiconductor can be expected.

4B, 4C, 4D, and 4E are Zn ₂ SnO ₄ nanobelts, ZnO nanobelts, In ₂ O ₃ nanobelts, prepared through Examples 2, 3, 4, and 5, respectively. SEM and Confocal Microscopy images of SnO ₂ nanobelts.

The thickness and width of individual InGaZnO ₄ nanobelt, Zn ₂ SnO ₄ nanobelt, ZnO nanobelt, In ₂ O ₃ nanobelt, and SnO ₂ nanobelt can be adjusted depending on the concentration of metal salt precursor, electrospinning condition, and heat treatment condition. It is possible. Preferably, the thickness is 20 to 50 nm, and the width of the nano belt is about 1 to 3 μm, which is appropriate for optimal transistor characteristics.

The inventor of the present invention InGaZnO ₄ produced by thermal compression and heat treatment X-ray diffraction analysis was performed to confirm that the Zn ₂ SnO ₄ , ZnO, In ₂ O _3, and SnO ₂ nanobelt networks have a polycrystalline structure, and that the crystal phases are well formed.

Figure 5a is a graph showing the change in X-ray intensity according to the heat treatment temperature change of the InGaZnO ₄ nanobelt network, it can be seen that a new crystal phase appears according to the change in the heat treatment temperature. It can be seen that InGaZnO ₄ starts crystal formation at 700 ° C., and In ₂ O ₃ , Ga ₂ O ₃ , and ZnO are mixed as a composite when heat-treated at 500 ° C. and 600 ° C. Even when phases are mixed in this way, excellent semiconductor characteristics can be obtained. FIG. 5B is a graph showing the change of X-ray intensity according to the heat treatment temperature of Zn ₂ SnO ₄ nanobelt network. As compared with the crystal peaks of SnO ₂ and ZnO heat-treated at 500 ° C., new crystal phases change according to the heat treatment temperature. It can be seen that it appears. It can be seen that Zn ₂ SnO ₄ starts crystal formation at 800 ° C., and ZnO and SnO ₂ are mixed into a composite at 500 to 700 ° C. Even when the phases are mixed in this manner, excellent semiconductor characteristics can be obtained in the same manner as in InGaZnO ₄ . 5C, 5D and 5E show the X-ray diffraction results of the ZnO nanobelt network, In ₂ O ₃ nanobelt network and SnO ₂ nanobelt network, respectively. It can be seen that the ZnO nanobelt network, In ₂ O ₃ nanobelt network and SnO ₂ nanobelt network having a single-phase polycrystalline structure are well formed based on X-ray diffraction results.

FIG. 6 is a SEM photograph showing the process of nanobelt of zinc acetate dihydrate / polyvinylacetate composite nanowire obtained during the process of Example 3. FIG. When the individual nanowires are grown on the gate insulating film through electrospinning, partial melting occurs as shown in the middle figure (SEM image after cutting into FIB) due to the low glass transition temperature characteristic of PVAc. can see. In addition, in the heat treatment process of 400 ~ 800 ℃, when the temperature increase process is slowly occurs, additional melting of PVAc occurs, it can be seen that after the final heat treatment is nanobelt as shown in the lower portion of FIG. The lower part image of FIG. 6 shows an image of a plane cut through a focused ion beam (FIB). The nanobelt is capable of controlling the thickness and width by controlling the temperature increase rate, and it is also possible to easily prepare individual nanobelts by introducing a thermocompression and thermopressing process.

On the other hand, the present inventors fabricated a field effect transistor to prove that the metal oxide-based nanobelt / nanobelt network having a polycrystalline structure prepared through the embodiment has excellent characteristics as a semiconductor channel layer.

7A and 7B are graphs illustrating current-voltage characteristics of a field effect transistor using an InGaZnO ₄ nanobelt network (nanomat) manufactured according to Example 1 of the present invention as a semiconductor layer. FIG. 7A is a graph of the amount of current change according to the voltage difference between the source and the drain as the gate voltage of the InGaZnO ₄ nanobelt network heat-treated at 550 ° C. is increased. As the voltage of the gate electrode V _GS is increased, the current amount increases from the drain electrode to the source electrode due to the electric field effect. FIG. 7B is a graph showing a change amount of current I _DS of the drain and source electrodes according to the voltage change of the gate electrode V _GS with respect to the specific drain electrode voltage V _DS . The field effect electron mobility in the saturated region of InGaZnO ₄ nanobelt network is 1cm2 / Vs, the threshold voltage is -9V, the subthreshold voltage is 0.8V / decade, and the flashing ratio is 10 ⁶ . The on / off ratio 10 ⁶ is a condition required for the operation of an ideal transistor, and the field effect electron mobility is 1 cm 2 / Vs, which is comparable to that of amorphous silicon. In particular, the nanobelt network used in the present invention can obtain a high electric field mobility and flashing ratio characteristics, despite the polycrystalline network structure composed of nanograins or nanoparticles, such as gas sensor, biosensor and UV detector (detector) Excellent performance can be expected in applications. The gate insulating film used is a SiO ₂ film having a low dielectric constant, and thus the driving voltage is about 20 V. However, by changing the gate insulating film to a material having a high dielectric constant, a transistor operating at a low voltage can be realized.

8A and 8B are graphs illustrating current-voltage characteristics of a field effect transistor using a Zn ₂ SnO ₄ nanobelt network manufactured according to Example 2 of the present invention as a semiconductor layer. FIG. 8A is a graph of the current variation according to the voltage difference between the source and the drain as the gate voltage of the Zn ₂ SnO ₄ nanobelt network (nanomat) is increased. As the voltage of the gate electrode is increased, the current amount increases from the drain electrode to the source electrode due to the electric field effect. FIG. 8B is a graph showing changes in current of drain and source electrodes according to voltage changes of the gate electrode with respect to a specific drain electrode voltage. The field effect electron mobility in the saturated region of Zn ₂ SnO ₄ nanobelt network heat-treated at 800 ℃ is 0.01cm2 / Vs, the threshold voltage is -8V, the subthreshold voltage is 10V / decade, and the flashing ratio is It was 10 ³ . Although the field effect mobility value is set low as 0.08cm2 / Vs, it shows excellent saturation characteristics, so that the amount of source-drain current for noxious gases (NOx, CO, HC, SOx, etc.) in gas sensor applications By detecting the change in the amount of current according to the change and the gate voltage of the external gas, it is possible to realize excellent sensing characteristics even at low electron mobility.

9A and 9B are graphs illustrating current-voltage characteristics of a field effect transistor using a ZnO nanobelt network manufactured according to Example 3 of the present invention as a semiconductor layer. 9A is a graph of the amount of current change according to the voltage difference between the source and the drain as the gate voltage of the ZnO nanomat is increased. As the voltage of the gate electrode is increased, the current amount increases from the drain electrode to the source electrode due to the electric field effect. 9B is a graph illustrating changes in current of drain and source electrodes according to voltage changes of the gate electrode with respect to a specific drain electrode voltage. The field effect electron mobility in the ZnO nanobelt network saturation region was 0.015 cm 2 / Vs, the threshold voltage was -3V, the subthreshold voltage was 24.2V / decade, and the flashing ratio was 10 ³ . In particular, when using a nanobelt network, excellent current saturation characteristics can be obtained in the current-voltage characteristics of the nanobelt network-based field effect transistors as shown in the output curves of FIGS. 9A and 9B. It can be seen that the stability is greatly improved.

10A and 10B are graphs illustrating current-voltage characteristics of a field effect transistor using an In ₂ O ₃ nanobelt network manufactured according to Example 4 of the present invention as a semiconductor layer. FIG. 10A is a graph of the amount of current change according to the voltage difference between the source and the drain as the gate voltage of the In ₂ O ₃ nanobelt network is increased. As the voltage of the gate electrode is increased, the current amount increases from the drain electrode to the source electrode due to the electric field effect. FIG. 10B is a graph illustrating changes in current of drain and source electrodes according to voltage changes of the gate electrode with respect to a specific drain electrode voltage. The field effect electron mobility in the saturated region of In ₂ O ₃ nanobelt network is 3.0x10 ^-5 ㎠ / Vs and the threshold voltage is -13V. It can be expected that the improved characteristics according to the heat treatment conditions / atmosphere control of the In ₂ O ₃ nanobelt network semiconductor layer.

11A and 11B are graphs showing current-voltage characteristics of a field effect transistor using individual InGaZnO ₄ (IGZO) nanobelts manufactured according to Example 1 of the present invention as a semiconductor layer. FIG. 11A is a graph illustrating a change in current according to a voltage difference between a source and a drain as the gate voltage of the InGaZnO ₄ nanowire is increased. As the voltage of the gate electrode is increased, the current amount increases from the drain electrode to the source electrode due to the electric field effect. FIG. 11B is a graph showing changes in current of drain and source electrodes according to voltage changes of the gate electrode with respect to a specific drain electrode voltage. FIG. The field effect electron mobility in the saturation region of InGaZnO ₄ nanobelt is 0.1cm2 / Vs, the threshold voltage is 16V, the subthreshold voltage is 3V / decade, and the flashing ratio is 10 ⁴ . It can be seen that excellent current saturation characteristics and stable transistor device operation are achieved when using a four-component InGaZnO ₄ semiconductor layer. Even when the individual metal oxide nanobelt is used, the field effect electron mobility value is relatively low (0.1 cm 2 / Vs), but the electron mobility is high enough to detect gas in the transistor structure.

12A and 12B are graphs illustrating current-voltage characteristics of a field effect transistor using individual Zn ₂ SnO ₄ nanobelts manufactured according to Example 2 of the present invention as a semiconductor layer. 12A is a graph of the amount of current change according to the voltage difference between the source and the drain as the gate voltage is increased. As the voltage of the gate electrode is increased, the current amount increases from the drain electrode to the source electrode due to the electric field effect. 12B is a graph illustrating changes in current of drain and source electrodes according to voltage changes of the gate electrode with respect to a specific drain electrode voltage. The field effect electron mobility in the saturation region of Zn ₂ SnO ₄ nanowire was 0.02cm 2 / Vs, the threshold voltage was 11V, the subthreshold voltage was 14V / decade, and the flashing ratio was 10 ² .

13A and 13B are graphs illustrating current-voltage characteristics of a field effect transistor using individual ZnO nanobelts manufactured according to Example 3 of the present invention as a semiconductor layer. 13A is a graph of the amount of current change according to the voltage difference between the source and the drain as the gate voltage is increased. As the voltage of the gate electrode is increased, the current amount increases from the drain electrode to the source electrode due to the electric field effect. FIG. 13B is a graph illustrating changes in current of drain and source electrodes according to voltage changes of the gate electrode with respect to a specific drain electrode voltage. The field effect electron mobility in the saturation region of ZnO nanowire was 0.2cm2 / Vs, the threshold voltage was 17V, the subthreshold voltage was 4.6V / decade, and the flashing ratio was 5x10 ⁴ .

14A and 14B are graphs showing current-voltage characteristics of a field effect transistor using individual In ₂ O ₃ nanobelts manufactured according to Example 4 of the present invention as a semiconductor layer. FIG. 14A is a graph illustrating a change in current according to a voltage difference between a source and a drain as the gate voltage of the In ₂ O ₃ nanobelt increases. As the voltage of the gate electrode is increased, the current amount increases from the drain electrode to the source electrode due to the electric field effect. 14B is a graph showing changes in current of drain and source electrodes according to voltage changes of the gate electrode with respect to a specific drain electrode voltage. The field effect electron mobility in the saturated region of In ₂ O ₃ nanobelt is 6.0 × 10 ^-3 cm 2 / Vs, and the threshold voltage is -7V.

Up to now, the operation of a nanobelt-based transistor composed of a four-component system (InGaZnO ₄ ), a three-component system (Zn ₂ SnO ₄ ), and a two-component system (ZnO, In ₂ O ₃ ) has been described. Based on the transistor operating characteristics based on the present embodiment, if a nanobelt is formed by introducing a metal salt capable of forming SnO ₂ and Ga ₂ O ₃ based on ZnO and In ₂ O ₃ , the nano belt may be mixed with an appropriate polymer substrate. Nanobelt networks such as _a Ga _b Zn _c Sn _d O _x can also be constructed. At this time, by adjusting the equivalent ratio of the metal salt used, it is possible to make a new metal oxide of the desired composition ratio. Any combination between the a, b, c, and d may be allowed. For example, InGaZnO ₄ , Zn ₂ SnO ₄ , In ₂ Zn ₃ O ₆ , ZnGa ₂ O ₄ , InGaO _3, and the like may be used, and the selection of the characteristic composition ratio is not limited.

In order to confirm the applicability of SnO ₂ based transistors, not ZnO based SnO ₂ nanobelt or nanobelt network based transistors, the present invention was implemented.

15A and 15B are graphs showing current-voltage characteristics of a field effect transistor using an individual SnO ₂ nanobelt network prepared according to Example 5 of the present invention as a semiconductor layer. FIG. 15A is a graph illustrating changes in current of drain and source electrodes according to voltage changes of the gate electrode with respect to a specific drain electrode voltage. FIG. 15B is a graph showing a change in current according to a voltage difference between a source and a drain as the gate voltage of the SnO ₂ nanobelt network heat-treated at 550 ° C. is increased. As the voltage of the gate electrode is increased, the current amount increases from the drain electrode to the source electrode due to the electric field effect.

16A and 16B are graphs showing current-voltage characteristics of a field effect transistor using individual SnO ₂ nanobelts manufactured according to Example 5 of the present invention as a semiconductor layer. FIG. 16A is a graph illustrating a change in current according to a voltage difference between a source and a drain as the gate voltage of the SnO ₂ nanobelt is increased. As the voltage of the gate electrode is increased, the current amount increases from the drain electrode to the source electrode due to the electric field effect. FIG. 16B is a graph illustrating changes in current of drain and source electrodes according to voltage changes of the gate electrode with respect to a specific drain electrode voltage. The field effect electron mobility in the saturation region of SnO ₂ nanobelt is 0.1cm2 / Vs, the threshold voltage is 16V, the subthreshold voltage is 3V / decade, and the flashing ratio is 10 ⁴ .

In this way, the nano-belt or nano-belt network-type metal oxide semiconductor manufactured by electrospinning can be used for the field effect transistor, and the gate insulating film (SiO ₂ ) used in the present embodiment is replaced with a high dielectric constant insulating film. In this case, field effect transistors can be manufactured that operate at lower operating voltages. An insulating film of a high dielectric constant in this case, the _{HfO 2, (Ba, Sr)} TiO 3, Bi 1 .5 Zn 1 .0 Nb 1 .5 O 7, Al 2 O 3, SiN, SiON, ZrO 2, YO 2, Y there may be mentioned ₂ O ₃ or the like. In addition, the above-mentioned formation of the gate insulating film can be made by using a conventional semiconductor device manufacturing process. For example, reactive sputtering, chemical vapor deposition, CVD, pulsed laser deposition, atomic layer deposition, and the like can be given.

In addition, since the semiconductor layer manufactured according to the present invention has a polycrystalline nanobelt network property, the semiconductor layer may be applied as a high sensitivity sensor through a change in resistance sensed against an external stimulus (gas / biomolecule).

In the above, a specific preferred embodiment according to the present invention has been described. However, it is to be understood that the present invention is not limited to the above-described embodiments, and the above-described embodiments merely represent a part of various embodiments to which the principles of the present invention are applied. Those skilled in the art to which the present invention pertains may make various changes without departing from the spirit of the technical idea of the present invention described in the claims below.

1A and 1B are cross-sectional views illustrating a structure of a field effect transistor including a metal oxide semiconductor in the form of a nanowire and a nanowire network formed according to an embodiment of the present invention.

FIG. 2A is a scanning electron microscope (SEM) image of the polymer / metal salt composite nanowire network, showing a tin precursor / PVAc composite nanowire network.

FIG. 2B is a SEM photograph after thermocompression bonding of the tin precursor / PVAc composite nanowire network at a pressure of 0.1 MPa (0.05 kgf / cm 2) at 120 ° C. FIG.

3A is a SEM photograph of a polycrystalline InGaZnO ₄ nanobelt network prepared according to an embodiment of the present invention.

3B is an optical microscope photograph of a polycrystalline Zn ₂ SnO ₄ nanobelt network prepared according to an embodiment of the present invention.

3C is an optical micrograph of a polycrystalline zinc oxide (ZnO) nanobelt network prepared according to an embodiment of the invention.

3D is an optical micrograph of a polycrystalline In ₂ O ₃ nanobelt network prepared according to an embodiment of the present invention.

3E is an optical micrograph of a polycrystalline SnO ₂ nanobelt network prepared according to an embodiment of the present invention.

4A is a SEM photograph of a polycrystalline InGaZnO ₄ nanobelt prepared according to an embodiment of the present invention.

4B is an optical micrograph of a polycrystalline Zn ₂ SnO ₄ nanobelt prepared according to an embodiment of the present invention.

4c is a SEM photograph of a polycrystalline ZnO nanobelt prepared according to an embodiment of the present invention.

4D is an optical micrograph of a polycrystalline In ₂ O ₃ nanobelt prepared according to an embodiment of the present invention.

4E is an optical micrograph of a polycrystalline SnO ₂ nanobelt prepared according to an embodiment of the present invention.

FIG. 5A is a diagram illustrating X-ray diffraction results of a polycrystalline InGaZnO ₄ nanobelt network prepared according to an embodiment of the present invention, in which diffraction peaks taken while changing the heat treatment temperature from 500 ° C. to 800 ° C. are observed. .

FIG. 5B is a diagram illustrating X-ray diffraction results of a polycrystalline Zn ₂ SnO ₄ nanobelt network prepared according to an embodiment of the present invention, in which diffraction peaks taken while changing the heat treatment temperature from 500 ° C. to 900 ° C. are observed. X-ray diffraction results of ZnO and SnO ₂ nanobelt networks are shown together for reference.

5c is a diagram showing the X-ray diffraction results of the polycrystalline ZnO nanobelt network prepared according to the embodiment of the present invention.

5d is a diagram showing the X-ray diffraction results of the polycrystalline In ₂ O ₃ nanobelt network prepared according to the embodiment of the present invention.

Figure 5e is a diagram showing the X-ray diffraction results of the polycrystalline SnO ₂ nanobelt network prepared in accordance with an embodiment of the invention.

FIG. 6 is a SEM photograph of a process of nanobelt-forming a metal oxide (ZnO) semiconductor nanowire manufactured according to an embodiment of the present invention after heat treatment using FIB (Focused Ion Beam). This image shows the formation of ZnO nanobelt.

FIG. 7A is a diagram illustrating I _DS -V _DS (Output) current-voltage characteristics of a transistor manufactured using a polycrystalline InGaZnO ₄ nanobelt network prepared according to an embodiment of the present invention as an active layer.

FIG. 7B is a diagram showing I _DS -V _GS (Transfer) current-voltage characteristics of a transistor manufactured using a polycrystalline InGaZnO ₄ nanobelt network prepared according to an embodiment of the present invention as an active layer.

FIG. 8A illustrates I _DS -V _DS (Output) current-voltage characteristics of a transistor manufactured using a polycrystalline Zn ₂ SnO ₄ nanobelt network prepared according to an embodiment of the present invention as an active layer.

FIG. 8B is a diagram showing I _DS -V _GS (Transfer) current-voltage characteristics of a transistor prepared using a polycrystalline Zn ₂ SnO ₄ nanobelt network prepared according to an embodiment of the present invention as an active layer.

FIG. 9A is a diagram illustrating I _DS -V _DS (Output) current-voltage characteristics of a transistor manufactured using a polycrystalline ZnO nanobelt network prepared according to an embodiment of the present invention as an active layer.

FIG. 9B is a diagram showing I _DS -V _GS (Transfer) current-voltage characteristics of a transistor manufactured using a polycrystalline ZnO nanobelt network prepared according to an embodiment of the present invention as an active layer.

FIG. 10A illustrates I _DS -V _DS (Output) current-voltage characteristics of a transistor manufactured using a polycrystalline In ₂ O ₃ nanobelt network prepared through a thermocompression bonding process as an active layer according to an embodiment of the present invention.

FIG. 10B is a diagram illustrating I _DS -V _GS (Transfer) current-voltage characteristics of a transistor prepared using a polycrystalline In ₂ O ₃ nanobelt network prepared through a thermocompression bonding process as an active layer according to an embodiment of the present invention.

FIG. 11A illustrates I _DS -V _DS (Output) current-voltage characteristics of a transistor manufactured using a polycrystalline InGaZnO ₄ nanobelt manufactured as an active layer according to an embodiment of the present invention.

FIG. 11B is a diagram showing I _DS -V _GS (Transfer) current-voltage characteristics of a transistor manufactured using a polycrystalline InGaZnO ₄ nanobelt manufactured according to an embodiment of the present invention as an active layer.

12A is a diagram showing I _DS -V _DS (Output) current-voltage characteristics of a transistor manufactured using a polycrystalline Zn ₂ SnO ₄ nanobelt manufactured according to an embodiment of the present invention as an active layer.

12B is a diagram showing I _DS -V _GS (Transfer) current-voltage characteristics of a transistor manufactured using a polycrystalline Zn ₂ SnO ₄ nanobelt manufactured according to an embodiment of the present invention as an active layer.

FIG. 13A illustrates I _DS -V _DS (Output) current-voltage characteristics of a transistor manufactured using a polycrystalline ZnO nanobelt manufactured according to an embodiment of the present invention as an active layer.

FIG. 13B is a diagram showing I _DS -V _GS (Transfer) current-voltage characteristics of a transistor manufactured using a polycrystalline ZnO nanobelt manufactured according to an embodiment of the present invention as an active layer.

FIG. 14A illustrates I _DS -V _DS (Output) current-voltage characteristics of a transistor manufactured using a polycrystalline In ₂ O ₃ nanobelt manufactured according to an embodiment of the present invention as an active layer.

FIG. 14B is a diagram illustrating I _DS -V _GS (Transfer) current-voltage characteristics of a transistor manufactured using a polycrystalline In ₂ O ₃ nanobelt manufactured according to an embodiment of the present invention as an active layer. FIG.

FIG. 15A is a diagram illustrating I _DS -V _DS (Output) current-voltage characteristics of a transistor manufactured using a polycrystalline SnO ₂ nanobelt network prepared according to an embodiment of the present invention as an active layer.

FIG. 15B is a diagram illustrating I _DS -V _GS (Transfer) current-voltage characteristics of a transistor manufactured using a polycrystalline SnO ₂ nanobelt network prepared according to an embodiment of the present invention as an active layer.

FIG. 16A illustrates I _DS -V _DS (Output) current-voltage characteristics of a transistor manufactured using a polycrystalline SnO ₂ nanobelt network prepared according to an embodiment of the present invention as an active layer.

FIG. 16B is a diagram illustrating I _DS -V _GS (Transfer) current-voltage characteristics of a transistor manufactured using a polycrystalline SnO ₂ nanobelt network prepared according to an embodiment of the present invention as an active layer. FIG.

<Explanation of symbols for the main parts of the drawings>

10: field effect transistor

11: substrate

12: gate electrode

13: insulating film

14a: metal oxide semiconductor nano belt

14b: Metal Oxide Semiconductor Nanobelt Network

15a: source electrode

15b: drain electrode

Claims (30)

In the field effect transistor comprising a substrate, a gate electrode, a gate insulating film, a metal oxide semiconductor layer, a source electrode and a drain electrode, The metal oxide semiconductor layer, The semiconductor layer includes a polycrystalline metal oxide layer comprising a thin metal oxide layer composed of nanograins or nanoparticles and having a polycrystalline nanobelt structure in which individual nanowires are compressed or a polycrystalline nanobelt network structure in which a nanowire network is compressed. Field effect transistor. The method of claim 1, wherein the metal oxide semiconductor layer is a thin metal oxide layer of a nano belt structure or nano belt network structure having a width of 0.5 ~ 3 ㎛ and a thickness of 20 ~ 100 nm using a polycrystalline metal oxide semiconductor layer Field effect transistor. The method according to claim 1, wherein the metal oxide semiconductor layer is a thin metal oxide layer of the nano belt structure or nano belt network structure having a width of 1 to 3 ㎛ and a thickness of 20 to 50 nm using a polycrystalline metal oxide semiconductor layer Field effect transistor. The field effect using the polycrystalline metal oxide semiconductor layer of claim 1, wherein the metal oxide semiconductor layer is a thin metal oxide layer having a nanobelt structure or nanobelt network structure composed of nanograins or nanoparticles having a size of 5 to 20 nm. transistor. The field effect transistor according to claim 1, wherein the metal oxide semiconductor layer is a metal oxide thin layer having a nanobelt structure or a nanobelt network structure including ZnO. The field effect transistor using a polycrystalline metal oxide semiconductor layer according to claim 1, wherein the metal oxide semiconductor layer is a metal oxide thin layer having a nanobelt structure or a nanobelt network structure including SnO ₂ . The field effect transistor using a polycrystalline metal oxide semiconductor layer according to claim 1, wherein the metal oxide semiconductor layer is a metal oxide thin layer having a nanobelt structure or a nanobelt network structure including In ₂ O ₃ . The field effect transistor according to claim 1, wherein the metal oxide semiconductor layer is a metal oxide thin layer having a nanobelt structure or a nanobelt network structure including Zn ₂ SnO ₄ . The method according to claim 1, wherein the metal oxide semiconductor layer is a nanobelt structure or nanobelt network structure comprising In _a Ga _b Zn _c Sn _d O _x (0≤a, b, c, d), the equivalent ratio of the metal salt A field effect transistor using a polycrystalline metal oxide semiconductor layer, characterized in that formed by forming a metal oxide of a desired composition ratio. The method of claim 9, wherein the metal oxide semiconductor layer is one or two or more of InGaZnO ₄ , In ₂ Zn ₃ O ₆ , Zn ₂ SnO ₄ , ZnGa ₂ O ₄ , InGaO ₃ , In ₂ O ₃ and Ga ₂ O ₃ A field effect transistor using a polycrystalline metal oxide semiconductor layer, characterized in that the metal oxide thin layer of the nano belt structure or nano belt network structure comprising a metal oxide. The polycrystalline metal oxide semiconductor layer of claim 1, wherein the metal oxide semiconductor layer is a nanobelt structure or a thin metal oxide layer having a nanobelt network structure including ZnO doped with at least one of Al and Ga. Field effect transistor. The polycrystalline metal oxide of claim 1, wherein the metal oxide semiconductor layer is a nanobelt structure or a thin metal oxide layer having a nanobelt network structure composed of a p-type metal oxide of ZnRh ₂ O ₄ , SrCu ₂ O _2, or CuO. Field effect transistor using a semiconductor layer. The method according to claim 1, wherein the gate insulating film _{SiO 2, HfO 2, (Ba} , Sr) TiO 3, Bi 1 .5 Zn 1 .0 Nb 1 .5 O 7, Al 2 O 3, SiN, SiON, ZrO 2, A field effect transistor using a polycrystalline metal oxide semiconductor layer, characterized in that any one of YO ₂ and Y ₂ O ₃ . The field effect transistor of claim 1, wherein the gate electrode, the source electrode, and the drain electrode are Al, Au, Cr, Ti, Pt, or ITO (In doped SnO ₂ ) electrodes. The field effect transistor using a polycrystalline metal oxide semiconductor layer according to claim 1, wherein the substrate / gate electrode / gate insulating film / metal oxide semiconductor layer / source electrode and drain electrode are laminated in this order. The field effect transistor using a polycrystalline metal oxide semiconductor layer according to claim 1, wherein the substrate / gate electrode / gate insulating film / source electrode and drain electrode / metal oxide semiconductor layer are stacked in this order. In the method of manufacturing a field effect transistor comprising a substrate, a gate electrode, a gate insulating film, a metal oxide semiconductor layer, a source electrode and a drain electrode, A gate insulating film is formed on the substrate on which the gate electrode is formed, and then a source electrode and a drain electrode are formed, and then a semiconductor layer having a polycrystalline nanobelt structure or a polycrystalline nanobelt network structure composed of nanograins or nanoparticles, or nanograins or nanoparticles is formed. After forming the semiconductor layer of the polycrystalline nano belt structure or nano belt network structure consisting of particles to form a source electrode and a drain electrode, Forming the semiconductor layer of the polycrystalline nano belt structure or polycrystalline nano belt network structure, Spinning a mixed solution comprising a polymer and a metal salt precursor to produce an individual composite nanowire or a composite nanowire network in which the polymer and the metal salt precursor are mixed; Nanobeltting the polymer / metal salt composite nanowire or composite nanowire network by thermocompression or thermocompression; Thereafter, heat treatment is performed to remove the polymer and oxidize the metal salt, thereby forming a thin metal oxide layer of the polycrystalline nanobelt structure in which the individual composite nanowires are compressed, or a thin metal oxide layer of the polycrystalline nanobelt network structure in which the composite nanowire network is compressed. Making; Method of manufacturing a field effect transistor using a polycrystalline metal oxide semiconductor layer comprising a. The method according to claim 17, The metal salt precursor is ZnO, SnO ₂ , InGaZnO ₄ , Zn ₂ SnO ₄ , In ₂ Zn ₃ O ₆ , ZnGa ₂ O ₄ , InGaO ₃ , In ₂ O ₃ or Ga ₂ O ₃ through the heat treatment A precursor capable of constituting ZnO or a precursor capable of constituting ZnO doped with at least one of Al and Ga, or a p-type metal oxide of ZnRh ₂ O ₄ , SrCu ₂ O _2, or CuO A method for producing a field effect transistor using a polycrystalline metal oxide semiconductor layer, characterized in that the precursor. 19. The method of manufacturing a field effect transistor using a polycrystalline metal oxide semiconductor layer according to claim 18, wherein zinc acetate dihydrate is used as the metal salt precursor capable of forming ZnO. The method according to claim 18, wherein indium chloride is used as the metal salt precursor capable of constituting the In ₂ O ₃ . 19. The method of manufacturing a field effect transistor using a polycrystalline metal oxide semiconductor layer according to claim 18, wherein tin acetate is used as the metal salt precursor capable of forming SnO ₂ . 19. The method of claim 18, wherein zinc acetate and tin acetate are used as metal salt precursors that may form Zn ₂ SnO ₄ . 19. The method of manufacturing a field effect transistor using a polycrystalline metal oxide semiconductor layer according to claim 18, wherein indium chloride, gallium chloride and zinc acetate dihydrate are used as metal salt precursors that can form the InGaZnO ₄ . 18. The method of claim 17, wherein the polymer is polymethylmethacrylate (PMMA), polyvinylpyrrolidone (PVP), polyvinylacetate (PVAc), polyvinyl alcohol (PVA), polystyrene (PS) A method for producing a field effect transistor using a polycrystalline metal oxide semiconductor layer, characterized by using a compound or a mixture of two or more thereof. 18. The method of claim 17, wherein the thermocompression or thermocompression is performed by applying a pressure at a temperature equal to or higher than the glass transition temperature of the polymer used. The method of claim 25, wherein the polymer is polyvinylacetate and is applied by applying a pressure of at least 0.1 MPa (0.05 kgf / cm 2) at a temperature of 120 ° C. 27. . The method of claim 17, wherein the heat treatment is performed at a temperature of 400 ° C. to 800 ° C. 18. The method of claim 17, wherein the mixed solution comprising the polymer and the metal salt precursor is subjected to electrospinning, melt-blown, flash spinning or electrostaticmelt-blown. A method for manufacturing a field effect transistor using a polycrystalline metal oxide semiconductor layer, characterized in that the radiation by. The method of claim 17, wherein the mixed solution containing the polymer and the metal salt precursor is dissolved in a solvent selected from water, ethanol, THF (Tetrahydrofuran), DMF (dimethylformamide), DMAc (dimethylacetamide), toluene (Toluene) A method for producing a field effect transistor using a polycrystalline metal oxide semiconductor layer, which is obtained. The sensor element including the field effect transistor using the polycrystalline metal oxide semiconductor layer of any one of Claims 1-16.

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