KR20090098281A - Method for manufacturing the semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to prevent bowing on the top of the metal contact by forming a barrier layer on the side wall of a recess and performing etching using the barrier layer as mask. A first interlayer dielectric(220) is formed on the top of a semiconductor substrate(200) with a bit line(210). A second interlayer dielectric(240) is formed on the first interlayer dielectric. A recess is formed by etching the second interlayer dielectric. A barrier film(230) is formed on the side wall of the recess. A contact hole exposing the bit line is formed by etching the first and the second interlayer dielectric using the barrier layer as mask. A metal contact is formed by filling a metal layer in the contact hole.

Description

Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE}

The present invention relates to a method for manufacturing a semiconductor device. In particular, the present invention relates to a method of manufacturing a metal contact connecting a bit line and a metal wiring.

In general, a semiconductor device includes a plurality of unit devices therein. As semiconductor devices are highly integrated, various elements must be formed at a high density on a certain cell area, thereby decreasing the size of unit devices such as transistors and capacitors.

In particular, in semiconductor memory devices such as DRAM (Dynamic Random Access Memory), as the design rule decreases, the size of unit elements formed inside the cell gradually decreases, but in order to secure the capacity of the capacitor, the aspect ratio increases. Inevitably, this causes difficulties in forming the metal contact hole formed after the formation of the capacitor.

A typical example is a metal contact hole forming process for forming a metal line in a peripheral region after forming a bit line and forming a capacitor of a cell region in manufacturing a semiconductor memory device.

In the semiconductor device, when a capacitor is formed into a concave structure, a subsequent metal contact etching depth may increase, thereby causing a problem such as contact not-open.

In addition, the higher the density of deep metal contacts, the higher the aspect ratio, resulting in reduced photoresist selection, lower contact open capability, lower CD (bottom critical dimension), and minimal space due to profile bowing. Many problems arise, such as reduction. In particular, since the deep contact has a high etching target, bowing may occur on the oxide layer pattern, and the minimum space due to the bowing may be reduced, thereby increasing the hole diameter in the mask state.

1A and 1B are cross-sectional views illustrating a metal contact manufacturing method of a semiconductor device according to the prior art.

Referring to FIG. 1A, a first interlayer insulating layer 120 and an etch stop layer 130 are formed on the semiconductor substrate 100 provided with the bit line 110.

Here, the bit line 110 has a stacked structure of the bit line barrier layer 110a, the bit line metal layer 110b, and the bit line hard mask layer 110c. The bit line spacers 115 are included on both sides of the bit line 110.

Next, a second interlayer insulating layer 140 and a third interlayer insulating layer 150 are formed on the etch stop layer 130.

Here, the second interlayer insulating film 140 and the third interlayer insulating film 150 are formed of a PSG film and a PE-TEOS film, respectively.

Next, the contact hole 155 exposing the bit line 110 by sequentially etching the third interlayer insulating layer 150, the second interlayer insulating layer 140, the etch stop layer 130, and the first interlayer insulating layer 120. To form.

At this time, the height of the storage electrode of the cell region is determined according to the height of the first, second, and third interlayer insulating layers 120, 140, and 150, and the height of the interlayer insulating layer that is etched as the storage electrode height of the cell region increases. Will increase. Therefore, due to the high aspect ratio, there is a problem in that the contact hole not open phenomenon that the bit line 110 is not exposed such as 'A' due to insufficient etching margin of the contact hole 155.

Referring to FIG. 1B, the etching time is increased to expose the bit line metal layer 110b of the bit line 110 in order to prevent a contact hole sickle opening phenomenon such as 'A' of FIG. 1A.

Next, the barrier metal layer 160 is formed on the inner wall of the contact hole 155, and the contact hole 155 is filled with tungsten to form the metal contact 170.

Next, a metal wire 180 connected to the metal contact 170 is formed on the third interlayer insulating layer 150.

At this time, it is preferable to include any one selected from titanium (Ti), titanium nitride film (TiN), and a combination thereof, above and below the metal wire 180, respectively.

Here, when the etching time is increased to prevent the contact hole sickle opening phenomenon as shown in 'A' of FIG. 1A, the CD (critical dimension) of the contact hole is significantly increased compared to the designed CD, and thus, ' As shown in B ′, the upper portion of the metal contact 170 is excessively widened or bowing occurs, thereby reducing the overlap margin between the metal wire and the metal contact when forming the subsequent metal wire.

In the above-described method for manufacturing a semiconductor device according to the related art, as the size of the device decreases, the height of the storage electrode is continuously increased to secure an appropriate Cs, whereas the CD of the metal contact is reduced. Therefore, during the contact hole etching process for forming a metal contact, the etching margin is insufficient and a contact hole not open phenomenon occurs. In order to prevent this, the etching time is increased to prevent the sick opening. In this case, there is a problem in that the CD (Critical Dimension) of the contact hole is increased or the bowing occurs in the contact hole, so that an overlap margin between the metal wire and the metal contact is reduced during the subsequent process.

According to an embodiment of the present invention, a CD is formed by recessing an interlayer insulating layer in a region where a metal contact is to be formed, forming a barrier layer on the sidewall of the recess, and performing a contact hole etching process using the barrier layer as a mask. An object of the present invention is to provide a method of manufacturing a semiconductor device, which prevents the expansion and prevents bowing from occurring on the upper portion of the metal contact to improve device characteristics.

Method for manufacturing a semiconductor device according to the present invention

Forming a first interlayer insulating layer on the semiconductor substrate including the bit lines;

Forming a second interlayer insulating film on the first interlayer insulating film;

Etching the second interlayer insulating film to form a recess;

Forming a barrier layer on the sidewalls of the recesses;

Etching the second interlayer insulating layer and the first interlayer insulating layer using the barrier layer as a mask to form a contact hole exposing the bit line;

Filling a metal layer in the contact hole to form a metal contact;

And forming a metal wire connected to the metal contact on the second interlayer insulating layer.

The first interlayer insulating film and the second interlayer insulating film may be formed of any one selected from PSG, PE-TEOS, and a combination thereof, and the barrier film may be formed of a material having an etch selectivity different from that of the first and second interlayer insulating films. It is preferable, and it is formed more preferably with a nitride film.

The method may further include forming a barrier metal layer on the inner wall of the contact hole including the recess, wherein the barrier metal layer is formed of any one of titanium (Ti), titanium nitride (TiN), and a combination thereof.

The metal wire is formed of aluminum, and further includes any one layer selected from titanium, a titanium nitride film, and a combination thereof on the upper and lower portions of the metal wire.

In the method of manufacturing a semiconductor device according to the present invention, a metal layer is formed by recessing an interlayer insulating layer in a region where a metal contact is to be formed, forming a barrier layer on the sidewall of the recess, and performing a contact hole etching process using the barrier layer as a mask. The overlap margin due to misalignment between the metal wires can be improved, and the phenomenon in which the CD of the upper portion of the contact hole is expanded and the bowing phenomenon can be prevented during the contact hole etching process. In addition, there is an effect of preventing the contact hole sick open phenomenon due to the lack of etching margin between the center and the edge of the wafer to improve the characteristics of the device.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as being in scope.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

2A to 2F illustrate a method of manufacturing a semiconductor device according to the present invention, and after forming the bit line and the storage electrode of the cell region, a method of forming a metal contact connecting the bit line and the upper metal wiring of the peripheral circuit region to each other is shown. It is shown.

Referring to FIG. 2A, the first interlayer insulating layer 220 and the etch stop layer 230 are formed on the semiconductor substrate 200 provided with the bit line 210.

Here, the bit line 210 has a stacked structure of a bit line barrier layer 210a, a bit line metal layer 210b, and a bit line hard mask layer 210c. The bit line 210 includes bit line spacers 215 on both sides.

Next, the second interlayer insulating film 240 and the third interlayer insulating film 250 are formed on the etch stop layer 230, and the CMP process is performed to planarize the third interlayer insulating film 250.

Here, the second interlayer insulating film 240 and the third interlayer insulating film 250 are preferably formed of any one selected from PSG, PE-TEOS, and a combination thereof.

Next, a photoresist pattern (not shown) is formed on the third interlayer insulating layer 250 to open a hard mask layer (not shown) and a metal contact predetermined region. Next, the hard mask layer (not shown) is etched using the photoresist pattern (not shown) as a mask to form a hard mask pattern 255.

Referring to FIG. 2B, the recess 260 is formed by etching the upper side of the third interlayer insulating layer 250 using the hard mask pattern 255 as an etching mask. At this time, the recess 260 is preferably etched to a depth of 2000 ~ 3000Å.

2C and 2D, the barrier layer 270 is formed on the entire surface including the recess 260. In this case, the barrier layer 270 is formed on the inner wall of the recess 260 and the sidewalls and the upper portion of the hard mask pattern 255.

The barrier layer 270 may be formed of a material having a different etching selectivity from the first, second, and third interlayer insulating layers 220, 240, and 250, and more preferably, a nitride layer.

Next, the barrier layer 270 on the surface of the hard mask pattern 255 and the bottom of the recess 260 is removed by full etching, so that the barrier layer 270 is formed only on the sidewall of the hard mask pattern 255 and the sidewall of the recess 260. Let this be left.

In this case, the barrier layer 270 serves to protect the sidewall of the upper contact hole during the subsequent contact hole etching process, and the CD (Critical Dimension) above the contact hole is expanded during the subsequent cleaning process. It is preferable not to remove because it serves to prevent the.

Referring to FIG. 2E, the third interlayer insulating layer 250, the second interlayer insulating layer 240, and the etch stop layer 230 under the recess 260 using the hard mask pattern 255 and the barrier layer 270 as a mask. The first interlayer insulating layer 220 is sequentially etched to form a contact hole 280 that exposes the bit line 210. Hereinafter, the contact hole 280 means a recess 260.

In this case, the bit line hard mask layer 210c on the bit line 210 is etched, and the bit line conductive layer 210b is partially etched. That is, the bit line conductive layer 210b may be exposed by the contact hole 280.

Referring to FIG. 2F, the hard mask pattern 255 is removed, and the barrier metal layer 290 is formed on the inner wall of the contact hole 280. The barrier metal layer 290 may be formed of any one of titanium (Ti), titanium nitride (TiN), and a combination thereof.

Next, a metal layer is formed on the entire top including the contact hole 280 in which the barrier metal layer 290 is formed.

Next, an etch-back process is performed until the third interlayer insulating layer 250 is exposed to form a metal contact 295 embedded with a metal layer. Here, the metal layer is preferably tungsten.

Next, a metal wiring layer is formed on the third interlayer insulating layer 250 and then patterned to form a metal wiring 300 to be connected to the metal contact 295.

At this time, the metal wiring 300 is preferably formed of aluminum.

In addition, it is preferable to include any one selected from titanium (Ti), titanium nitride film (TiN), and combinations thereof, above and below the metal wire 300, respectively.

Next, an insulating film is formed over the entirety including the metal wiring 300 to isolate the metal wiring 300 from the outside.

1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

<Explanation of Signs of Major Parts of Drawings>

200: semiconductor substrate 210: bit line

220: first interlayer insulating film 230: etching prevention film

240: second interlayer insulating film 250: third interlayer insulating film

255: mask pattern 270: barrier film

280: contact hole 290: barrier metal layer

295 metal contact 300 metal wiring

Claims (9)

Forming a first interlayer insulating layer on the semiconductor substrate including the bit lines; Forming a second interlayer insulating film on the first interlayer insulating film; Etching the second interlayer insulating film to form a recess; Forming a barrier layer on the sidewalls of the recess; Etching the second interlayer insulating layer and the first interlayer insulating layer using the barrier layer as a mask to form a contact hole exposing the bit line; Filling a metal layer in the contact hole to form a metal contact; And Forming a metal wire connected to the metal contact on the second interlayer insulating layer Method of manufacturing a semiconductor device comprising a. The method of claim 1, And the first interlayer insulating film and the second interlayer insulating film are any one selected from PSG, PE-TEOS, and a combination thereof. The method of claim 1, The barrier layer may be formed of a material having a different etching selectivity from the first and second interlayer insulating layers. The method of claim 1, And the barrier film is formed of a nitride film. The method of claim 1, And forming a barrier metal layer on the inner wall of the contact hole including the recess. The method of claim 5, wherein The barrier metal layer is formed of any one of titanium (Ti), titanium nitride film (TiN) and a combination thereof. The method of claim 1, The metal layer is a manufacturing method of a semiconductor device, characterized in that tungsten. The method of claim 1, The metal wiring is formed of aluminum, the method of manufacturing a semiconductor device. The method of claim 1, The method of manufacturing a semiconductor device, characterized in that the upper and lower portions of the metal wiring further comprises any one selected from titanium, titanium nitride film and combinations thereof.

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