KR20090098176A - Method for manufacturing semiconductor device - Google Patents

Abstract

A manufacturing method of a semiconductor device is provided to reduce resistance of a buried bit line by forming the buried bit line through a polysilicon layer and an insulation film before forming a surround gate. A material film and an insulation film(104) for a bit line are formed on a top part of a semiconductor substrate(100). A first hole is formed by selectively etching the material film and the insulation film for the bit line. The first hole is filled with a vertical pillar(110). A surround gate(122) is formed in an outer side of the vertical pillar. A buried bit line(102a) is formed by patterning the material film for the bit line and the insulation film. The material film for the bit line is made of a polysilicon layer.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of reducing the resistance of a buried bit line by forming a buried bit line using a polysilicon layer and an insulating film before forming a surround gate. .

Recently, in the case of semiconductor devices such as DRAMs, a technology for increasing the density of transistors by placing more transistors in a limited area is required. For this purpose, a vertical transistor technology capable of putting a memory cell element in a small area has been proposed. Such vertical transistors provide a surrounding gate structure surrounding the vertical channel.

In order to form the surround electrode at 4F2, the channel region is selectively isotropically etched to make the channel region thinner than the source / drain region, thereby obtaining excellent device characteristics. As a result, vertical transistors can effectively use a limited area. On the other hand, vertical transistors are expected to be able to easily make smaller transistors, and are attracting attention as transistors in various fields as well as DRAM.

Although not shown in the drawings, a general vertical transistor forming method will be described below. First, a vertical pillar is formed on a semiconductor substrate, and a gate insulating layer is formed on the semiconductor substrate including the vertical pillar. Then, bit line impurity regions are formed in the semiconductor substrate between the vertical pillars. Next, a series of patterning processes, including gate polysilicon layer formation, are used to form a surround gate surrounding the vertical pillars. Next, an insulating film is formed between the surround gates, and the insulating film, the bit line impurity region, and a portion of the semiconductor substrate are selectively etched to form a buried bitline. A word line is then formed to electrically connect the surround gates.

However, since the conventional buried bit line is formed through an impurity implantation process, there is a problem in that data is lost when the data stored in the memory cell is transmitted due to an increase in resistance. In addition, when the impurity concentration is uneven, a resistance difference between buried bit lines may occur, resulting in an inconsistent operation timing of each memory cell. In addition, due to the impurity implanted from the vertical pillars, even though the subsequent insulating process is performed, the distance between the gate polysilicon layer is close and it is difficult to insulate the surround gates from each other. Can occur.

The present invention has the following object.

First, the buried bit line may be formed by using a polysilicon layer and an insulating layer before the surround gate is formed to reduce the resistance of the buried bit line.

Second, by forming a buried bit line with a uniform polysilicon layer instead of the impurity implantation process, the operation timing of each memory cell can be made constant.

Third, by forming an insulating film between the surround gate and the buried bit line, it is possible to prevent the occurrence of an electrical short between the surround gate and the buried bit line.

A method of manufacturing a semiconductor device according to the present invention includes forming a bit line material film and an insulating film on a semiconductor substrate; Selectively etching the bit line material layer and the insulating layer to form a first hole exposing the semiconductor substrate in a predetermined vertical filler region; Forming a vertical pillar filling the first hole; Forming a surround gate outside the vertical pillars; And patterning the insulating layer and the material layer for the bit line to form a separate buried bit line.

The bit line material film may be formed of a polysilicon layer, the insulating film may be formed of a nitride film, and the vertical pillar forming process may include a selective epitaxial layer of the semiconductor substrate exposed by the first hole as a seed layer. And further comprising forming a first mask layer over the insulating film, wherein the first mask layer is formed of an oxide film.

The method may further include forming a second mask layer on the first mask layer and the vertical pillar, forming the second mask layer using a nitride film, and forming the surround gate. Selectively etching a mask layer and the first mask layer to form a second hole exposing a portion of the vertical pillar; Forming spacers on the second mask layer and the exposed vertical pillar sidewalls; Etching the vertical pillars of the second hole bottom to form a recess; Forming a gate insulating film on the recess sidewalls; Forming a conductive layer filling the recess on the gate insulating layer; And etching the conductive layer using the spacers as an etch mask.

The spacer may be formed of a nitride film, the vertical pillar etching process may be performed by an isotropic etching method, the conductive layer may be formed of a polysilicon layer, and the buried bitline may be formed by the insulating film, Forming a first insulating layer on the round gate, the spacer, and the second mask layer; Filling the second hole by forming a second insulating film on the first insulating film; Planarization etching the second and first insulating layers until the second mask layer is exposed; And etching portions of the second and first insulating layers, the insulating layer, the bit line material layer, and the semiconductor substrate.

The present invention provides the following effects.

First, by forming the buried bit line using the polysilicon layer and the insulating layer before forming the surround gate, the resistance of the buried bit line is reduced.

Second, by forming the buried bit line with a uniform polysilicon layer instead of the impurity implantation process, the operation timing of each memory cell can be made constant.

Third, an insulating film is formed between the surround gate and the buried bit line, thereby providing an effect of preventing an electrical short between the surround gate and the buried bit line.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1 to 12 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 1, a bit line material layer 102, a first insulating layer 104, and a first mask layer 106 are formed on the semiconductor substrate 100. The bit line material film 102 may be formed of a polysilicon layer, the first insulating film 104 may be formed of a nitride film, and the first mask layer 106 may be formed of an oxide film.

Referring to FIG. 2, a first hole exposing the semiconductor substrate 100 in the vertical pillar predetermined region by selectively etching the first mask layer 106, the first insulating layer 104, and the bit line material layer 102. Form 108.

Referring to FIG. 3, an active region is defined by forming a vertical pillar 110 over the semiconductor substrate 100 using the semiconductor substrate 100 exposed by the first hole 108 as a seed layer. In this case, the vertical pillars 110 may be formed by a selective epitaxial growth method (SEG). Next, the vertical pillars 110 are flattened and etched until the first mask layer 106 is exposed.

Referring to FIG. 4, a second mask layer 112 is formed on the first mask layer 106 and the vertical pillars 110. Here, the second mask layer 112 is preferably formed of a nitride film.

Referring to FIG. 5, the second mask layer 112 and a portion of the first mask layer 106 are selectively etched to form a second hole 114 exposing the vertical pillars 110. At this time, the thickness of the first mask layer 106 to be etched is preferably adjusted according to the size of the subsequent surround gate. The etching process of the second and first mask layers 112 and 106 may be performed by an anisotropic etching method.

Referring to FIG. 6, a second insulating layer (not shown) is formed on the second mask layer 112 including the second hole 114, and the second insulating layer is selectively etched to vertically align the second mask layer 112. The spacer 116 is formed on the sidewalls of the mold pillar 110. Here, the second insulating film is preferably formed of a nitride film, and serves as an etch stop film in a subsequent isotropic etching process. In addition, the etching process of the second insulating layer is preferably performed by an etch back method.

Referring to FIG. 7, the recess 118 is formed by etching the first mask layer 106 and the vertical pillars 110 at the bottom of the second hole 114 until the first insulating layer 104 is exposed. . Here, the etching process of the first mask layer 106 and the vertical filler 110 is preferably performed by an isotropic etching method. In this case, the first insulating layer 104 is not etched due to the difference in etching selectivity from the first mask layer 106.

Referring to FIG. 8, a gate insulating layer 120 is formed on sidewalls of the recess 118. The gate insulating layer 120 may be formed by a method selected from among thermal oxidation, chemical-vapor-deposition, and chemical oxide methods.

9, the recess 118 is filled by forming a conductive layer (not shown) on the gate insulating layer 120 and the vertical pillars 110. Here, the conductive layer is preferably formed of a polysilicon layer. Next, the conductive layer is etched using the second mask layer 112 as an etch mask to form a surround gate 122 surrounding the vertical pillars 110.

Referring to FIG. 10, a third insulating layer 124 is formed on the first insulating layer 104, the surround gate 122, the spacer 116, and the second mask layer 112. Here, the third insulating film 124 is formed of a nitride film, and serves as a protective film for protecting the surround gate 122 in subsequent processes.

Referring to FIG. 11, a fourth insulating film 126 is formed on the third insulating film 124 to fill the gaps between the surround gates 122, and the fourth insulating film (until the second mask layer 112 is exposed). 126) is planarized etched. Here, the planarization process of the fourth insulating layer 126 may be performed by a chemical mechanical polishing (CMP) method or an etch back method.

Referring to FIG. 12, portions of the fourth insulating layer 126, the first insulating layer 104, the bit line material layer 102, and the semiconductor substrate 100 are etched to form separate buried bit lines 102a. .

In other words, the present invention can reduce the resistance of the buried bit line formed by the impurity implantation by forming the material layer 102 for the bit line before forming the surround gate 122. In addition, since the buried bit line 102a is formed of a uniform polysilicon layer, a resistance difference does not occur between the buried bit lines 102a, and thus an operation timing of each cell may be constant. In addition, the surround gate 122 and the buried bit line 102a may be electrically insulated by the first insulating layer 104.

1 to 12 are cross-sectional views showing a method for manufacturing a semiconductor device according to the present invention.

Claims (13)

Forming a material layer and an insulating film for the bit line on the semiconductor substrate; Selectively etching the bit line material layer and the insulating layer to form a first hole exposing the semiconductor substrate in a predetermined vertical filler region; Forming a vertical pillar filling the first hole; Forming a surround gate outside the vertical pillars; And Patterning the insulating layer and the material layer for the bit line to form a separate buried bit line Method of manufacturing a semiconductor device comprising a. The method of claim 1, wherein the bit line material layer is formed of a polysilicon layer. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is formed of a nitride film. The method of claim 1, wherein the vertical pillar forming process is performed by a selective epitaxial growth method using the semiconductor substrate exposed by the first hole as a seed layer. The method of claim 1, further comprising forming a first mask layer on the insulating layer. The method of claim 5, wherein the first mask layer is formed of an oxide film. The method of claim 5, further comprising forming a second mask layer on the first mask layer and the vertical pillars. 8. The method of claim 7, wherein the second mask layer is formed of a nitride film. The method of claim 7, wherein the surround gate forming step Selectively etching the second mask layer and the first mask layer to form a second hole exposing a portion of the vertical pillar; Forming spacers on the second mask layer and the exposed vertical pillar sidewalls; Etching the vertical pillars of the second hole bottom to form a recess; Forming a gate insulating film on the recess sidewalls; Forming a conductive layer filling the recess on the gate insulating layer; And Etching the conductive layer using the spacers as an etch mask Method of manufacturing a semiconductor device comprising a. 10. The method of claim 9, wherein the spacer is formed of a nitride film. The method of claim 9, wherein the vertical pillar etching process is performed by an isotropic etching method. 10. The method of claim 9, wherein the conductive layer is formed of a polysilicon layer. 10. The method of claim 9, wherein the buried bitline forming step is Forming a first insulating film on the insulating film, the surround gate, the spacer, and the second mask layer; Filling the second hole by forming a second insulating film on the first insulating film; Planarization etching the second and first insulating layers until the second mask layer is exposed; And Etching portions of the second and first insulating layers, the insulating layer, the bit line material layer, and the semiconductor substrate Method of manufacturing a semiconductor device comprising a.

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