KR20090098172A - Method for forming photo mask - Google Patents

Abstract

A manufacturing method of an exposure mask is provided to minimize a pattern defect on a wafer by detecting a weak spot in advance through an RDR(Restricted Design Rule) and a PWM(Process Window Model). A target pattern layout corresponding to a desired circuit is designed(S10). A weak spot of the target pattern layout is detected through an RDR and a PWM(S14). The target pattern layout of the weak spot detected through the RDR and the PWM is changed. A database about the target pattern layout of the changed weak spot is generated(S16). An OPC(Optical Proximity Correction) is performed about the target pattern layout(S18). An MBV(Model Based Verification) is performed through the database(S20).

Description

Exposure mask manufacturing method {Method for forming photo mask}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, since a weak point is detected in advance by using a restricted design rule (RDR) and a process window model (PWM), modification can be made at the circuit design stage to increase the number of times the mask is manufactured. It can reduce and minimize pattern defects on the wafer, and save verification time by performing MBV (Model Based Verification) only on the database corresponding to the weak point.

In general, a lithography process is a process of performing exposure and development after applying a photoresist on a wafer, and is performed before an etching process or an ion implantation process requiring a mask.

As semiconductor devices become more integrated, the size and pitch of the patterns that make up the circuit are decreasing, so that during processing, the photolithography technology refines the mask design to properly control the amount of light emitted through the mask. The company has overcome the technical limitations of semiconductor device manufacturing by developing new photosensitizers, developing scanners using high numerical aperture lenses, and developing modified masks. .

On the other hand, the most widely used UV lasers currently use KrF light sources with a wavelength of 248 nm, but the light source is converted to shorter wavelengths of EUV, including ArF with a wavelength of 193 nm and F2 laser with a wavelength of 157 nm. It is becoming.

However, as the degree of integration of semiconductor devices increases, the size of the pattern formed on the mask approaches the wavelength of the light source, and as a result, the influence of light diffraction and interference increases in lithography technology.

Since the optical system of the exposure apparatus acts as a low pass filter, the pattern formed on the wafer appears in a distorted form in the pattern defined in the mask pattern.

In particular, an optical proximity effect (OPE) in which a corner portion of the pattern is distorted in a round shape is generated.

As a technique for overcoming the optical proximity effect, optical proximity correction (hereinafter referred to as OPC) that intentionally deforms the shape of the mask pattern and corrects the pattern distortion is used. Such OPC uses methods of adding or removing small patterns of less than resolution to a mask pattern formed on a mask. For example, line end treatment is a method of adding a corner serif pattern or a hammer pattern to overcome the problem that the line end becomes round in shape, and insertion of scattering bars Bars are a method of adding a sub-resolution scattering bar of sub-resolution at the periphery of a target pattern in order to minimize the change in the line width of the pattern according to the pattern density.

In addition, the OPC program is based on a rule-based method that refines the layout of the lithography engineer's experience into several rules according to the approach and model-based correction of the layout using a mathematical model of the lithography system. It is divided into model based methods.

The general OPC method designs the target pattern layout of a desired circuit, checks for abnormalities of the layout through Design Rule Check (DRC), and performs OPC if there is no abnormality in the layout. After improving the pattern transfer fidelity, a large number of biases are obtained based on the Layer Versus Layer (LVL) and at least two space widths according to the line threshold size, and the optimum bias amount is obtained from these bias amounts. OPC checks for abnormalities through the Optical Rule Check (ORC) step that checks the pattern shape. Next, the expected weak point is detected through MBV (Model Based Verification) and the mask is finally manufactured. At this time, the MBV verification is a full chip based verification, there is a problem that takes a lot of time because the verification to the unnecessary area is verified that no abnormality.

In other words, after performing the OPC with the design database file, the MBV is used to verify the area where the pattern defect may occur on the wafer when the OPC-implemented database file is manufactured with the actual mask and exposed. At this time, since the cell region of the database file is a portion of which a simple pattern is repeated, the cell region of the database file is excluded when verifying the MBV. However, as semiconductor devices become smaller, patterns become smaller, the number of patterns in the peripheral circuit area increases, and the complexity becomes more complicated. Therefore, the MBV verification except for the cell area consumes a lot of time. In addition, when correcting a portion where a pattern defect occurs on a wafer and remanufacturing a mask, there is a problem in that resource waste is repeatedly generated because it is repeatedly verified to an unmodified portion having no problem with the pattern.

An object of the present invention is to provide a method of manufacturing an exposure mask that can reduce the number of manufacturing of the mask, minimize pattern defects on the wafer, and save verification time by performing MBV only on the database corresponding to the weak point. It is done.

The exposure mask manufacturing method according to the present invention

Designing a target pattern layout corresponding to a desired circuit;

Detecting a weak point of the target pattern layout using a restricted design rule (RDR) and a process window model (PWM);

Changing the target pattern layout of the weak point detected via the RDR and the PWM;

Creating a database of the modified vulnerabilities;

Performing Optical Proximity Correction (OPC) on the target pattern layout;

Performing model based verification (MBV) using the database; And

Fabricating an exposure mask using the MBV results.

The method may further include performing a Layer Versus Layer (LVL) and an Optical Rule Check (ORC) on the result of performing the OPC.

The RDR detects the weak point in the core area, the PWM detects the weak point in the peripheral circuit area,

The PWM uses a model considering the focus margin, energy variation and mask error,

And performing a design rule check (DRC) to be performed in parallel with the step of detecting a weak point using the restricted design rule (RDR) and the process window model (PWM). .

The present invention detects the weak spots using RDR and PWD in advance, so that modifications can be made at the circuit design stage, thereby reducing the number of fabrication of the mask, minimizing pattern defects on the wafer, and only a database corresponding to the weak spots. By performing MBV, it is possible to save verification time.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the spirit of the present invention is thoroughly and completely disclosed, and the spirit of the present invention to those skilled in the art will be fully delivered. Also, like reference numerals denote like elements throughout the specification.

1 is a flowchart illustrating a method of manufacturing an exposure mask according to the present invention.

The target pattern layout corresponding to the desired circuit is designed (S10), and the abnormality of the target pattern layout is checked through a design rule check (hereinafter referred to as DRC) (S12).

In addition, the core area detects a weak point using a Restricted Design Rule (RDR), and the peripheral circuit area detects a weak point using a Process Window Model (PWM). (S14). Here, since the bit line sense amplifier or the sub word line driver in the core region is composed of simple repetitive patterns, the RDR can effectively detect the weak point. The circuit region is composed of random patterns, so the RDR is composed of data extracted from the one-dimensional (Dimension) pattern, so it is difficult to infer the trend of the 1.5-dimensional and two-dimensional patterns of the peripheral circuit region. Difficult to do Thus, the peripheral circuit area detects a weak point using PWM using a model that takes into account focus margin, energy variation and mask error.

Subsequently, the target pattern layout of the weak spots detected through RDR and PWM is changed, and a database for the weak spots is generated (S16).

In addition, to improve optical resolution and pattern transfer fidelity, OPC (Optical Proximity Correction) is performed on the target pattern layout (S18), Layer Versus Layer (LVL) and each line threshold A plurality of biases are obtained based on at least two space widths according to size, and an ORC (Optical Rule Check) for checking a pattern shape having an optimal bias amount from these bias amounts is performed to check for abnormalities in the OPC.

Next, MBV (Model Based Verification) is performed using a database of weak points detected through RDR and PWM (S20).

Therefore, since the verification of the target pattern layout area having no verified abnormality is omitted and only the weak point of the core area and the peripheral circuit area detected by RDR and PWM is performed, the verification can be performed efficiently and without time. .

Thereafter, an exposure mask is finally manufactured using the MBV result (S22).

As described above, the present invention detects a weak point using RDR and PWD in advance, so that modification can be made at the circuit design stage, thereby reducing the number of manufacturing of the mask, minimizing pattern defects on the wafer, and responding to the weak point. It can save verification time by performing MBV only for the database.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1 is a flowchart illustrating a method of manufacturing an exposure mask according to the present invention.

<Description of Signs for Main Parts of Drawings>

S10: Layout Design

S12: DRC

S14: Detecting Vulnerability Using RDR and PWM

S16: Change Vulnerability Layout and Create Database for Vulnerability

S18: OPC

S20: MBV using database

S22: making an exposure mask

Claims (5)

Designing a target pattern layout corresponding to a desired circuit; Detecting a weak point of the target pattern layout using a restricted design rule (RDR) and a process window model (PWM); Changing the target pattern layout of the weak point detected via the RDR and the PWM; Creating a database of the target pattern layout of the modified weak points; Performing Optical Proximity Correction (OPC) on the target pattern layout; Performing model based verification (MBV) using the database; And And manufacturing an exposure mask using the MBV result. The method of claim 1, And performing a Layer Versus Layer (LVL) and an Optical Rule Check (ORC) on the result of performing the OPC. The method of claim 1, And the RDR detects the weak point in the core area and the PWM detects the weak point in the peripheral circuit area. The method of claim 3, wherein The PWM is a method of manufacturing an exposure mask, characterized in that using the model in consideration of the focus margin (energy variation) and the mask error (mask error). The method of claim 1, And performing a design rule check (DRC) performed in parallel with the step of detecting a weak point using the restricted design rule (RDR) and the process window model (PWM). Method of making an exposure mask.

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