KR20090096866A - Non volatile memory device and method of operating the same - Google Patents

Abstract

A nonvolatile memory device and an operation method thereof are provided to correct an error by reading and programming inputted data without a separate error correction circuit. A plurality of memory cell arrays(310) includes a plurality of memory cells for storing data. A plurality of bit decision parts(350) counts the number of first bits and the number of second bits according to a read result of a repeatedly programmed data when a programmed data is read. A plurality of bit decision parts determines a plurality of bits as an output data according to a count result. A control part(380) counts the number of first bits and the number of second bits according to a read result of a repeatedly programmed data when a programmed data is read. The control part determines a plurality of data as an output data according to a count result.

Description

Nonvolatile memory device and method of operation

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the operation of a nonvolatile memory device, and more particularly, to a nonvolatile memory device capable of reducing a read error of stored data without a separate error correction circuit and a method of operating the same.

Flash memory, which is a nonvolatile memory, is generally classified into a NAND flash memory and a NOR flash memory. NOR flash memory has a good random access time characteristic because memory cells are independently connected to bit lines and word lines, whereas NAND flash memory has a plurality of memory cells connected in series so that one contact per cell string is provided. Since only requires, it has excellent characteristics in terms of integration degree. Therefore, a NAND structure is mainly used for highly integrated flash memory.

Well known NAND flash memory devices include memory cell arrays, row decoders, and page buffers. The memory cell array includes a plurality of word lines extending along rows and a plurality of bit lines extending along columns and a plurality of cell strings corresponding to the bit lines, respectively.

1 is a block diagram illustrating a configuration of a general memory device.

Referring to FIG. 1, the memory device 100 includes a memory device 110 for storing data and a controller 120 for controlling an operation of the memory device 110 according to an external input command.

The memory device 110 includes a separate controller, like a flash memory device, and includes memory cells for storing data and peripheral circuits for data storage and reading operations.

The controller 120 transfers data to the memory device 110 or corrects data output from the memory device 110 by a command from a system in which the memory device 100 is mounted and operated. Control operation such as transfer to

The controller 120 corrects an error of the input data, including error checking and correction (ECC) for error correction (121), and transmits the error to the memory device 110 or reads the data read from the memory device 110. Correct the error and deliver the system.

FIG. 2 is a flowchart illustrating an operation of the data input / output method of FIG. 1.

Referring to FIG. 2, when data to be stored in the system is input (S201), error correction of data input from the ECC 121 of the controller 120 is performed (S203). In this case, the error correction is to correct an error in the input process.

The error corrected data in step S203 is transferred to the memory device 110 and stored in the memory cell of the memory device 110 (S205). At this time, the process of storing data in the memory cell is performed by a program operation of a general flash memory device.

When data stored in the memory device 110 is subsequently read by a read command in step S205 (S207), the memory device 110 reads the data stored in the memory cell by a read operation of internal circuits (S209). The read data is transferred to the controller 120.

The ECC 121 of the controller 120 performs error correction on the data transferred from the memory device 110 (S211). The error correction is to correct an error caused by a memory cell failing or a read margin insufficient when the memory device 110 is read.

The controller 120 transmits the read data on which the error correction is completed to the external system (S213).

2 is a process of correcting a read data error in the memory device 110 with the help of the ECC 121 provided by the controller 120. Therefore, the ECC 121 of the controller 120 is necessary. In order to perform error correction without the help of the ECC 121 of the controller 120, the memory device 110 must include a circuit for an ECC function for error correction in the memory device 110.

Accordingly, an aspect of the present invention is to provide a nonvolatile memory device and an operation method thereof capable of correcting a data error without a separate error correction circuit.

Nonvolatile memory device according to a feature of the present invention,

A control unit which controls to program the data repeatedly a set number of times; And a plurality of bit determinations for counting the number of first bits and second bits according to the read result of the repeatedly programmed data when reading the programmed data, and determining the plurality of bits as output data according to the count result. Contains wealth.

The multi-bit determination unit may output a read error when the number of first bits and second bits is the same as the count result.

The repetitive programming is characterized in that the same data is programmed in a memory cell in which column addresses are consecutive for a set number of times.

The reading of the repeatedly programmed data and determining the plurality of bits may include classifying the memory cells having the column address consecutive as many times as the set number of times, and determining the number of bits using the data read from each group of memory cells. It is characterized by performing.

Nonvolatile memory device according to another aspect of the present invention,

A memory cell array comprising a plurality of memory cells for data storage; Program data is repeatedly programmed a predetermined number of times to be programmed in the memory cells, and when reading the programmed data, the number of first bits and second bits is counted according to a read result of the repeatedly programmed data, and the count And a controller for determining a plurality of data as output data according to the result.

The control unit may output a read error when the number of the first bit and the second bit is the same as the count result.

The controller may be configured to control the same data to be programmed in a memory cell in which column addresses are consecutive for a set number of times.

The determining of the plurality of bits by the controller may include classifying the memory cells having the column address consecutive as many times as the set number of times, and performing the determination of the number of bits using data read from the memory cells of each group. .

Method of operating a nonvolatile memory device according to a feature of the present invention,

Programming a particular bit into the first through Nth memory cells; Reading the first to Nth memory cells and counting each number of first and second bits; And outputting a plurality of bits as a result of the counting.

The programming of the first to Nth memory cells may include programming the bits to the first to Nth memory cells in the same manner, and the first to Nth memory cells have column addresses.

The counting of the first bit and the second bit may include counting the number of the first bit and counting the number of the second bit according to a result of reading the first to Nth memory cells. .

When the number of the first bit and the number of the second bit are the same, the read error is determined.

If it is determined that the read error, the first to N-th memory cell is read again, and the number of the first bit and the second bit is counted.

If it is determined that the read error, the data read error information is output.

As described above, the nonvolatile memory device and its operation method according to the present invention allow to correct an error by programming and reading input data many times without a separate circuit for error correction.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

3 is a block diagram of a flash memory device according to an embodiment of the present invention.

Referring to FIG. 3, the flash memory device 300 may include a memory cell array 310, a page buffer unit 320, a Y decoder 3330, an input / output controller 340, and a majority bit determination unit 350. And an X decoder 360, a voltage providing unit 370, and a control unit 380.

The memory cell array 310 includes a plurality of cell strings in which memory cells for data storage are connected in series, and each cell string is connected to a bit line BL. In addition, the gates of the memory cells are connected to the word line WL in a direction orthogonal to the bit line.

The page buffer 320 includes a plurality of page buffers PBs connected to bit lines of the memory cell array 310. Each page buffer PB temporarily stores data to be programmed in a selected memory cell. The data is transferred to a memory cell through a bit line, or data stored in the memory cell is read and stored.

The Y decoder 330 provides an input / output path between the page buffer PB of the page buffer unit 320 and the input / output controller 340 according to the input address. The input / output controller 340 repeatedly provides data input by the control of the controller 380 to the page buffer unit 320 through the Y decoder 330. For example, if the set number is four times, the input / output controller 380 repeats the data input from the outside four times to the page buffer unit 320 so that the same data is programmed in four columns.

In addition, when the input / output controller 340 reads the data stored in the memory cell array 310, the input / output controller 340 provides the read data to the multiple bit determiner 350, and provides data according to the determination of the multiple bit determiner 350. Output

The plurality of bit determination unit 350 divides the read data provided from the input / output control unit 360 into the same data group unit according to the column address, and determines a large number of data from each group and outputs the data through the input / output control unit 340. Let's do it.

If the set number of times is four times, the multi-bit determination unit 350 divides the data groups into four column units, such as the first to fourth column addresses and the fifth to eighth column addresses, and in each data group. The data to be read is determined to be one of '1' or '0', and the data having a large number is determined as data of the corresponding group.

The X decoder 360 selects a word line of the memory cell array 310 according to an input address. The voltage provider 370 generates an operating voltage to be provided to a word line connected by the X decoder 360 under the control of the controller 380.

The controller 380 may be configured to input the same input data to the memory cell array a predetermined number of times and control the multiple bit determiner 350 to determine and output multiple bits of the read data. Control the blocks. In this case, the controller 380 may include the same function as the multiple bit determiner 350. That is, it may be implemented by including it in the operation algorithm of the controller 380 without providing a separate multiple bit determination unit 350.

When data is programmed into the flash memory device 300 as described above, the data to be programmed for the data input signal is input as follows.

4A is a timing diagram of data input during programming according to an exemplary embodiment of the present invention.

Referring to FIG. 4A, the program data input according to the data input control signal / WE is repeatedly input the same data four times according to a preset number of times. The control to input the same data four times causes the input / output controller 340 to repeatedly input the data received four times under the control of the controller 380, and the input data is stored in the page buffer through the Y decoder 330. To be provided to the unit 320.

As described above, when repeatedly reading the programmed data four times, the repeatedly programmed data is counted as '1' data and '0' data, and the read data is determined as a large number. If the number of the '1' data and the '0' data is the same, the read error is determined.

4B is a timing diagram of data output when data is read according to an exemplary embodiment of the present invention.

Referring to FIG. 4B, data read by the page buffer unit 320 by the data read control signal / RE is transferred to the input / output controller 340 through the Y decoder 330.

As shown in FIG. 4B, there may be data of a memory cell in which an error occurs between data normally output and data actually read. That is, when the programmed data is '101', since each data is programmed in the same four memory cells and programmed as '11110000111', the read data should be '1111000111' if it is normally read. However, the data actually read out due to the read error is '110101000111'.

The actual read data is transferred to the multiple bit determiner 350, and the multiple bit determiner divides the groups into four groups, and then determines a large number of '101' in each group as output data and outputs the same as the output data. ), And the input / output controller 340 outputs data of '101' according to the determination of the multi-bit determination unit 350.

Therefore, even if there are bits in which an error occurs, the probability of error occurrence can be reduced by outputting a plurality of occupied bits. Reducing the probability of error occurs as the number of repetitive programming increases.

5 is an operation flowchart of a multiple bit determination method according to an exemplary embodiment of the present invention.

The multiple bit determiner 350 divides each column address into group units according to the number of repetitive programs set by the controller 380 to classify the repeatedly programmed data group. The multi-bit determination operation as shown in FIG. 5 is performed on the data group of each group.

The multi-bit determination operation for one group will be described with reference to FIG. 5. First, the multi-bit determination unit defines N, K, L, and M for initialization (S501). N is an order of column addresses, K is the number of '1' data, L is the number of '0' data, and M is the number of repetitive programs set by the controller 380. In an embodiment of the present invention, M becomes '4'. In the initialization operation, N = 1, L = 0, and K = 0.

Since N is 1 by the initial operation, when the first column data is received from the input / output controller 340 (S503), it is determined whether the first column data is '1' (S505). As a result of the determination in step S505, if the first column data is '1', the number of '1' data is counted (S507) and K = 1.

If the first column data is not '1', the number of '0' data is counted (S509), and L = 1.

It is then determined whether the current column data is the set number of times (S511). That is, when N and M become the same number, it can be determined that M column data has been read.

If N = M, then increase N by one to perform steps S503 to S509. If N = M, it is checked whether K, the number of '1' data, is larger than M / 2 (S515). Check if the number of '1' data is greater than half among all data. If K, the number of '1' data, is larger than M / 2, the majority bit determination unit 350 determines to output the '1' data (S517).

However, if K, the number of '1' data is not larger than M / 2, it is checked whether L, the number of '0' data, is larger than M / 2 (S519). If L, the number of '0' data, is greater than M / 2, the majority bit determination unit 350 determines to output '0' data (S521).

However, if both of the steps S515 and S519 are not satisfied, it means that the number of '1' data and the number of '0' data are the same, so it is determined as a count error (S523). If it is determined that the count error, it can be treated as a read error and output a read error message to the outside. Alternatively, multi-bit determination may be performed by reading corresponding column data.

The input / output controller 340 outputs the data determined by the multiple bit determination unit 350 to the outside as output data.

The above process is performed for all column addresses, and the same process is performed for each group divided according to the number of repetitive programs set by the controller 380.

The operation of FIG. 5 will be described with reference to the actual output data of FIG. 4B as an example.

First, N = 1, K = 0, L = 0, M = 4 is initialized (S501).

Subsequently, according to the actual read data of FIG. 4B, the majority bit determination unit 350 receives the first column data as '1' (S503), counts the number of '1' data, and becomes K = 1 (S507). ). Since N is not M (S511), N is changed to 2 (S513).

The majority bit determination unit 350 receives '1' as the second data (S503), counts the number of '1' data, and K = 2 (S507). In this manner, steps S503 to S509 are repeated, where N = 4, K = 3 and L = 1. Since N = M, step S515 is performed. Since M = 4, M / 2 = 2 and K = 3, it is determined by step S515 that '1' data is output (S517).

Similarly, after the initialization (S501), the next four data are also subjected to the same multi-bit determination operation so that the output data is determined as '0'. This operation minimizes read errors.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.

1 is a block diagram illustrating a configuration of a general memory device.

FIG. 2 is a flowchart illustrating an operation of the data input / output method of FIG. 1.

3 is a block diagram of a flash memory device according to an embodiment of the present invention.

4A is a data input timing diagram during programming according to an exemplary embodiment of the present invention.

4B is a timing diagram of data output when data is read according to an exemplary embodiment of the present invention.

5 is an operation flowchart of a multiple bit determination method according to an exemplary embodiment of the present invention.

* Brief description of the main parts of the drawings *

300: flash memory device 310: memory cell array

320: page buffer unit 330: Y decoder

340: input and output control unit 350: multiple bit determination unit

360: X decoder 370: voltage providing unit

380 control unit

Claims (14)

A control unit which controls to program the data repeatedly a set number of times; And When reading the programmed data, a multi-bit determination unit which counts the number of the first bit and the second bit according to the read result of the repeatedly programmed data, and determines the plurality of bits as output data according to the count result. ; Nonvolatile memory device comprising a. The method of claim 1, The plurality of bit determination unit, And outputting a read error when the number of the first bit and the second bit is the same as the count result. The method of claim 1, The repetitive programming, A nonvolatile memory device, characterized in that the same data is programmed in a memory cell in which column addresses are consecutive for a set number of times. The method of claim 1, Reading the repeatedly programmed data and determining a plurality of bits, And classifying the memory cells having consecutive column addresses as a set number of times into groups, and performing a plurality of bit determination using data read from the memory cells of each group. A memory cell array comprising a plurality of memory cells for data storage; Program data is repeatedly programmed a predetermined number of times to be programmed in the memory cells, and when reading the programmed data, the number of first bits and second bits is counted according to a read result of the repeatedly programmed data, and the count And a controller configured to determine a plurality of data as output data according to the result. The method of claim 5, The control unit, And outputting a read error when the number of the first bit and the second bit is the same as the count result. The method of claim 5, The control unit, A nonvolatile memory device, characterized in that the same data is programmed in a memory cell in which column addresses are consecutive for a set number of times. The method of claim 5, The control unit determines a plurality of bits, And classifying the memory cells having consecutive column addresses as a set number of times into groups, and performing a plurality of bit determination using data read from the memory cells of each group. Programming a particular bit into the first through Nth memory cells; Reading the first to Nth memory cells and counting each number of first and second bits; And Outputting a plurality of bits as a result of the counting Method of operating a nonvolatile memory device comprising a. The method of claim 9, Programming in the first to Nth memory cells, And programming the bits to the first to Nth memory cells in the same manner, wherein the first to Nth memory cells have column addresses. The method of claim 9, Counting of the first bit and the second bit, And counting the number of the first bits and counting the number of the second bits according to a result of reading the first to Nth memory cells. The method of claim 11, And determining that the read error is the same as the number of the first bit and the number of the second bit. The method of claim 12, If it is determined that the read error, the first to N-th memory cell is read again, and the number of the first bit and the second bit is counted. The method of claim 12, And when it is determined that the read error is found, outputting data read error information.

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