KR20090089237A - Data transmitter and method thereof - Google Patents

Abstract

A data transmission circuit and a transmitting method thereof are provided to reduce jitter in a data receiving terminal by controlling an amount of delay of the data according to the mode. A data transmission circuit includes at least two transmission lines, a mode sensing unit(201), and a delay controller(203). The transmit line transmits the data. The mode sensing unit senses the mode according to the signal interference characteristic between the transmission lines. The delay controller controls an amount of delay of the data in response to the mode. A direction of the level transition of the data is the same in an even mode. The direction of the level transition of the data is different in an odd mode. The data is not transited in a static mode.

Description

DATA TRANSMITTER AND METHOD THEREOF {DATA TRANSMITTER AND METHOD THEREOF}

The present invention relates to a data transmission circuit, and more particularly, to a data transmission circuit capable of compensating for a difference in data transmission rate due to crosstalk noise between data.

When data is transmitted at high speed using a microstrip or data transmission line of a PCB board, jitter occurs due to the effect of crosstalk noise. Crosstalk noise refers to noise generated when signals on different transmission lines affect other lines by electrical coupling such as electrostatic coupling and electronic coupling. When multiple transmission lines exist in parallel and data passing through the transmission lines respectively transitions from high level to low level or from low level to high level, the difference in transmission speed is caused by mutual inductance and mutual capacitance, that is, crosstalk noise. Occurs.

1 is a diagram illustrating a conventional data transmission circuit.

As shown in the figure, when two transmission lines line1 and line2 exist in parallel, crosstalk noise due to the transition of data data1 and data2 passing through the transmission lines line1 and line2 and the transition direction Under the influence of the data (data1, data2) is delayed by each different delay amount to reach the data receiving end. The difference in the delay amount generated here is according to the following [Equation 1].

Here, Tde is a transmission time when the transition directions of the data (data1, data2) are the same, and Tdo is a transmission time when the data (data1, data2) are transitioned in the opposite direction. Ls is its inductance, Lm is the mutual inductance, Cm is the mutual capacitance, and Ct is its sum of its capacitance and mutual capacitance.

As shown in the figure, if any of the data (data1, data2) does not have a transition, the data (data1, data2) is not affected by crosstalk noise. However, when data data1 and data2 transition in the same direction or in the opposite direction, data data1 and data2 are affected by crosstalk noise. When data (data1, data2) transitions in the same direction, the transmission time of the data (data1, data2) is the longest, and when data (data1, data2) transitions in the opposite direction, the transmission time of the data (data1, data2) is the shortest .

That is, according to the prior art, crosstalk noise is generated between the data (data1, data2) by the transition of the data (data1, data2) and the transition direction, so that the data (data1, data2) has a difference in the delay amount and the data receiving end. To reach. This causes jitter at the data receiving end. In addition, this reduces the time margin of the data (data1, data2) has a problem of limiting the high-speed signal transmission.

The present invention has been proposed to solve the above problems, and an object thereof is to provide a data transmission circuit capable of reducing jitter caused by signal interference characteristics between transmission lines for transmitting data.

In order to achieve the above object, a data transmission circuit includes at least two transmission lines for transmitting data; A mode detecting unit detecting a mode according to a signal interference characteristic between the transmission lines; And a delay controller for adjusting the delay amount of the data in response to the mode.

In addition, to achieve the above object, a data transmission circuit includes three lines of transmission lines for transmitting data; A mode detecting unit detecting first and second modes between adjacent transmission lines according to signal interference characteristics between the transmission lines; And a delay adjuster configured to delay the data by using a clock delayed in response to the first and second modes.

In addition, to achieve the above object, a data transmission circuit includes a plurality of first input lines for receiving data; A plurality of second input lines for receiving data; A first transmission line through which data of the plurality of first input lines is transmitted; A second transmission line through which data of the plurality of second input lines is transmitted; A mode detecting unit detecting a mode according to the signal interference characteristics between the transmission lines; And a parallel-to-serial converter for adjusting the delay amount of the data in response to the mode, and sequentially selecting and outputting data of the plurality of input lines to the transmission line.

In addition, to achieve the above object, a data transmission method includes an input step of receiving the data through at least two transmission lines for transmitting data; A mode sensing step of sensing a mode according to signal interference characteristics between the transmission lines; And a delay adjustment step of adjusting a delay amount of the data transmitted in response to the mode detection result.

According to the present invention, the data transmission circuit can sense the characteristics of signal interference between transmission lines for transmitting data to reduce jitter generated at the data receiving end and secure time margins of the data to improve high-speed signal transmission characteristics.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

2 is a block diagram of a data transmission circuit according to a first embodiment of the present invention.

As shown in the figure, the present invention includes at least two transmission lines line_1 to line_n for transmitting data d1 to dn; A mode detecting unit 201 detecting a mode according to signal interference characteristics between transmission lines line_1 to line_n; And a delay adjusting unit 203 for adjusting the delay amount Dd of the data d1 to dn in response to the mode.

The mode detecting unit 201 compares data d1 to dn transmitted to adjacent transmission lines among the transmission lines line_1 to line_n. As discussed in the related art, a difference occurs in the transmission time of data d1 to dn according to signal interference characteristics due to crosstalk noise between transmission lines line_1 to line_n. Accordingly, the mode detecting unit 201 detects whether the data d1 through dn passing through the adjacent transmission line, the transition direction, and the like, and outputs three modes according to the signal interference characteristics.

The three modes include an even mode with the same level transition direction between data d1 to dn, an odd mode with a different level transition direction between data d1 to dn, and data d1 through dn. There is a static mode in which one of the data d1 to dn does not transition. In the even mode, the data d1 to dn are delayed the most, and in the odd mode, the data d1 to dn are delayed the least.

Since a difference occurs in the delay amount Dd of the data d1 to dn depending on the mode during data d1 to dn transmission, the delay adjusting unit 203 may be in an even mode or a static mode. ), The delay amount Dd is increased in the order of the odd mode to output the data d1 to dn. That is, the delay adjusting unit 203 outputs the data d1 to dn by reducing the delay amount Dd most in the even mode, and maximizes the delay amount Dd in the odd mode. It increments and outputs data d1-dn. Therefore, the difference between the arrival times of the data d1 to dn according to the mode can be reduced at the receiving end of the final data d1 to dn.

In summary, the data transmission circuit according to an embodiment of the present invention detects the level transition and direction of the data (d1 to dn) transmitted through the transmission lines (line_1 to line_n) and outputs a mode corresponding thereto. do. In addition, by adjusting the delay amount Dd in response to the mode, data d1 to dn are transmitted to compensate for the difference in arrival time due to signal interference, thereby reducing jitter at the data receiving end, thereby achieving the object of the present invention.

3 is a configuration diagram of a data transmission circuit according to a second embodiment of the present invention. In particular, it is a block diagram of a data transmission circuit having two transmission lines.

Two lines of transmission lines line1 and line2 for transmitting data d1 and d2 as shown in the figure; A mode detecting unit 301 for detecting a mode according to signal interference characteristics between transmission lines line1 and line2; And a delay adjusting unit 303 for adjusting the delay amount Dd of the data d1 and d2 by using the clock clk delayed in response to the detection result of the mode detecting unit 301.

The mode detecting unit 301 receives data d1 and d2 from two adjacent transmission lines line1 and line2 to determine whether the mode is an even mode, an odd mode, or a static mode. do. Transitions of the data d1 and d2 are sensed by storing the transmitted data d1_before and d2_before and comparing the data with the data to be transmitted d1_after and d2_after.

Referring to FIG. 4, the mode detector 301 stores the data d1_before and d2_before immediately before the data d1_after and d2_after to be transmitted, and transmits the data d1_after, a transition detecting unit 401 which detects a level transition of data d1 and d2 by comparing with d2_after; And a transition comparing unit 403 for outputting a mode between the data d1 and d2 in response to the detection result of the transition detecting unit 401.

The transition detecting unit 401 detects a level transition of data d1 and d2 passing through each of the two lines. 4 shows a transition detecting unit 401 for detecting a level transition of data d1 of the first line line1.

The flip-flop 405 of the transition detecting unit 401 triggers data d1_before and d2_before transmitted to the rising edge of the clock clk and stores the data until the next rising edge of the clock clk. The output value of the inverted flip-flop 405 and the data to be transmitted (d1_after, d2_after) are input to the NAND gate 407 to output the rising signal rise_1, and the output value d1_before and the inverted data to be transmitted are the NAND gate 409. ) To output the polling signal fall_1.

If the level transition occurs from the low level to the high level, the rising signal rise_1 is enabled from the high level. If the level transition occurs from the high level to the low level, the falling signal fall_1 is enabled from the high level. If the level transition does not occur, both the rising signal rise_1 and the falling signal fall_1 are disabled to the low level.

The transition detection unit 401 which detects the level transition of the data d2 of the second line line2 also outputs the rising signal rise_2 and the falling signal fall_2 in the same configuration.

The transition comparison unit 403 receives the rising signals rise_1 and rise_2 and the falling signals fall_1 and fall_2 of each of the two lines line1 and line2 and outputs a mode. The mode is represented as 2 bits.

 The rising signals rise_1 and rise_2 of the transition detection unit 401 according to the data d1 and d2 of each of the two lines line1 and line2 are all enabled at a high level, or the falling signals fall_1 and fall_2 are both at a high level. When enabled, the transition comparison unit 403 enables the even signal evne to a high level. This is the even mode.

When the rising signals rise_1 and rise_2 and the falling signals fall_1 and fall_2 of the transition detection unit 401 according to the data d1 and d2 of each of the two lines line1 and line2 are enabled one by one, the transition comparison unit is performed. 403 enables the odd signal odd to a high level. This is the odd mode.

When both the rising signals rise_1 and rise_2 and the falling signals fall_1 and fall_2 of the transition detection unit 401 are disabled at the low level, the transition comparison unit 403 may generate both the even signal and the odd signal odd. Disable at low level, this is the static mode.

3 again, the delay adjusting unit 303 includes first and second delay adjusting means 317 and 319 for delaying the data d1 and d2 of the first and second lines line1 and line2, respectively. . Each of the first and second delay adjusting means (317, 319) includes delay means (305, 311) for adjusting the delay amount (Dd) of the clock (clk) in response to a mode; And output means 307, 313 for outputting the data d1, d2 in synchronization with the delayed clocks clk_d1, clk_d2.

Delay means 305 and 311 delay the clock clk most in the odd mode and least clock clk in the even mode.

Delay means 305 and 311 will be described with reference to FIG. The delay means 305 of the first delay adjustment means 317 and the delay means 311 of the second delay adjustment means 319 have the same configuration, and the delay means 305 of the first delay adjustment means 317 in FIG. Explain the center.

The delay means 305 receiving the clock clk delays the clock clk in response to the mode. In this case, the delay unit 305 may include one or more delayed cells 501 connected in series. When 16 delay cells 501 are connected in series as shown in FIG. Clocks cd0 to cd15 can be obtained. That is, as the number of delay cells 501 passed by the clock clk increases, the delay amount Dd increases.

The reason why one or more delay cells 501 are configured is to prepare for a larger difference in delay amount Dd between modes when the transmission line is considerably long or the signal interference is severe. The signal selector 503 selects one of the 16 clocks cd0 to cd15 having different delay amounts Dd in response to the selection signal length_sel, and outputs it to the output means 307. In addition, the structure of the delay cell 501 is mentioned later in FIG.

The mode may also be delayed using the delay cell 505 to ensure a margin between the mode and the delayed clocks clk_d1 and clk_d2. At this time, in order to simplify the circuit configuration, the delay cell 505 for delaying the mode may use the static mode delay amount Dd.

3, the output means 307, 313 outputs the data d1, d2 in synchronization with the delayed clocks clk_d1, clk_d2, and according to the mode, the delay amount Dd of the data d1, d2. Adjust.

On the other hand, the delay adjusting unit 303 delays the data (d1, d2) in response to the mode to secure the margin between the data (d1, d2) and the delayed clock (clk_d1, clk_d2) output means (307, It may further include a replica means (309, 315) output to 313.

In addition, the data transmission circuit of FIG. 3 may compensate for the delay in the mode sensing process by simultaneously outputting the mode and the data d1 and d2 to the clock clk.

6A is a timing diagram of a data transmission circuit according to the prior art, and FIG. 6B is a timing diagram of a data transmission circuit according to an embodiment of the present invention.

In the conventional case, as shown in FIG. 6A, in the odd mode in which the data d1 and d2 have the same transition direction, the data arrives at the earliest (d1, d2) and reaches the fastest (t = tdo). In the static mode, in the middle mode (t = t _ds ), and in the even mode in which the transition directions of the data d1 and d2 are different, the data d1 and d2 reach the slowest. A time difference of up to 2Δt occurs between the data d1 and d2 that are reached by (t = t _de ).

However, in the data transmission circuit according to the present invention, as shown in FIG. 6B, when the data d1 and d2 are transmitted, the data transmission circuit differs from the delay amount Dd by the time difference (Δt) at the data receiving end. Output Therefore, in the even mode, the data is sent as fast as Δt, and in the odd mode, as late as Δt, the arrival time (t = t _ds ) of the data (d1, d2) at the data receiving end. By reducing the difference, you can reduce jitter.

FIG. 7A is an eye diagram illustrating an output signal of a data transmission circuit and a reception signal of a data receiver according to the prior art, and FIG. 7B is an output diagram of an output signal and a data receiver of a data transmission circuit according to an embodiment of the present invention. An eye diagram representing a received signal.

Conventional data transmission circuits transmit data at the same time regardless of the mode. Therefore, as shown in FIG. 7A, the jitter (98ps) of the received signal at the data receiving end is greater than the jitter (18ps) of the output signal of the data transmission circuit due to the difference in the transmission time according to the mode when the data passes the transmission line. Big.

However, the data transmission circuit according to the present invention adjusts the delay amount Dd in the even mode the least and the delay amount Dd in the odd mode the most according to the mode. . Therefore, as illustrated in FIG. 7B, the jitter (77ps) is large in the output signal of the data transmission circuit, but the jitter (40ps) is reduced in the reception signal of the data reception terminal, and the reception signal of the data reception terminal is more than when using the conventional data transmission circuit. Jitter is improved.

As a result, when the data transmission circuit according to the present invention is applied to the conventional data transmission circuit, the jitter of the received signal is improved.

8 is a configuration diagram of a data transmission circuit according to a third embodiment of the present invention. In particular, it is a block diagram of a data transmission circuit having three transmission lines.

As shown in the figure, the present invention includes three lines of transmission lines line1, line2, and line3 for transmitting data d1, d2, and d3; A mode sensing unit 801 for detecting first and second modes between the adjacent transmission lines (mode_1, mode_2) according to signal interference characteristics between transmission lines (line1, line2, and line3); And a delay controller 803 for delaying data d1, d2, and d3 by using a clock clk delayed in response to the first and second modes mode_1 and mode_2.

The mode detecting unit 801 includes: first mode detecting means 805 for comparing data of the first line line1 and the second line line2 among the three lines line1, line2, and line3; And second mode sensing means 807 for comparing the data d1, d2, d3 of the second line line2 and the third line line3 among the three lines line1, line2, and line3.

The delay adjusting unit 803 includes delay signal generating means 815 for outputting a delay signal according to the delay amount Dd in response to the first and second modes mode_1 and mode_2; Delay means 823, 825, and 827 for adjusting the delay amount Dd of the clock clk in response to the delay signal; And output means 829, 831, 833 for outputting the data d1, d2, d3 in synchronization with the delayed clocks clk_d1, clk_d2, clk_d3.

Unlike the case where the transmission line is two lines, the data transmission circuit having three transmission lines further includes a delay signal generating unit 815. The reason is that among the three lines (line1, line2, line3), the middle transmission line (line2) is affected by the signal interference from the transmission lines (line1, line3) and the transmission lines (1). Because everyone receives.

In more detail, the first line line1 and the third line line3 have the three modes mentioned above under the influence of the signal interference of the second line line2. However, the second line (line2) is affected by the signal interference of the first line (line1) and the third line (line3), so that the five modes (1) in the relationship between the first line (line1) and the third line (line3) mode).

The five modes are the first mode (mode_1) and the second mode (mode_2) both in the odd mode (odd mode), both the first mode (mode_1) and the second mode (mode_2) is even mode (even) mode, when only one of the first mode (mode_1) or the second mode (mode_2) is the even mode, only one of the first mode (mode_1) or the second mode (mode_2) is in the odd mode. If the first mode (mode_1) or the second mode (mode_2) are both static mode or one of the first mode (mode_1) and the second mode (mode_2) is even mode and the other Is the odd mode.

The more the even mode, the more the data d1, d2, d3 is delayed. The more the odd mode, the more the data d1, d2, d3 is delayed. Therefore, the delay adjusting unit 803 decreases the delay amount Dd as the even mode increases, and increases the delay amount Dd as the odd mode increases.

The five modes cannot be represented as two-bit signals. Therefore, the delay signal generating unit 815 outputs a 3-bit delay signal in response to the first and second modes mode_1 and mode_2 of the mode detection unit 801.

The delay signal generating means 815 includes a first delay signal generator 817 for outputting a first delay signal delay_1 in response to the first mode mode_1; A second delay signal generator 819 outputting a second delay signal delay_2 in response to the first and second modes mode_1 and mode_2; And a third delay signal generator 821 outputting a third delay signal delay_3 in response to the second mode mode_2.

The data transmission circuit of FIG. 8 has the same operation principle as the data transmission circuit of FIG. However, the delay signal generating means 815 is further included.

The delay controller 803 responds to the data d1 and d2 in response to the first and second modes mode_1 and mode_2 to secure a margin between the data d1, d2 and d3 and the delayed clocks clk_d1, clk_d2 and clk_d3. It may further include a replica means (835, 837, 839) for delaying d3) to output to the output means (829, 831, 833).

In addition, the data transmission circuit of FIG. 8 may compensate for the delay in the mode sensing process by simultaneously outputting the modes mode_1 and mode_2 and the data d1, d2 and d3 to the clock clk. At this time, the sense amplifier for amplifying the data (d1, d2, d3) may be included.

9 is a detailed block diagram of the delay signal generating unit 815 of FIG.

The delay signal generating unit 815 generates a 3-bit delay signal in response to the first and second modes mode_1 and mode_2. The second delay signal generator 819 receives the first and second modes mode_1 and mode_2. However, the first and third delay signal generators 817 and 821 receive only one mode from the mode detector 801 and receive a static mode from the other mode.

As mentioned above, the mode is represented as two bits, and the first mode mode_1 input to the delay signal generating unit 815 in FIG. 9 is the first even signal even1 and the first odd signal odd1. The second mode (mode_2) input to the delay signal generating means 815 includes a second even signal even2 and a second odd signal odd2.

In the relationship with the second line line2, the modes of the first line line1 and the third line line3, that is, the first and second modes mode_1 and mode_2 are both even modes. The case will be described by way of example. In this case, the first even signal even1 is enabled at a high level and the first odd signal odd1 is disabled at a low level. In addition, the second even signal even2 is enabled at a high level and the second odd signal odd2 is disabled at a low level.

Accordingly, since the output of the NOR gate 901 receiving the first even signal even1 and the second even signal even2 is at a low level, the bit2 signal is at a high level.

In addition, since the output of the NAND gate 903 receiving the first even signal even1 and the second even signal even2 is at a low level, the bit1 signal is at a high level.

In addition, since the outputs of the NAND gate 905 receiving the inverted second even signal even2b and the NAND gates 907, 909, and 911 receiving the inverted first even signal even1b are high level, the bit0 signal is high. Become a level.

Therefore, when the first and second modes mode_1 and mode_2 are both modes, the second delay signal delay_2 is 111. Where bit2 represents the value of the most significant bit and bit0 represents the value of the least significant bit.

Meanwhile, in the other four modes, the second delay signal generator 819 also outputs the third delay signal delay_2 of 3 bits. When both the first and second modes mode_1 and mode_2 are in the odd mode, the second delay signal delay_2 is 011, and only one of the first and second modes mode_1 and mode_2 is even mode. When the second delay signal delay_2 is 110, when only one of the first and second modes mode_1 and mode_2 is the odd mode, the second delay signal delay_2 is 100, and the first and second modes the second delayed signal when both mode_1 and mode_2 are in static mode or when one of the first and second modes is even mode and the other is in odd mode (delay_2) is 101.

The first delay signal delay_1 and the third delay signal delay_3 corresponding to the even mode, the static mode, and the odd mode may include the first and third delay signal generators 817, 821) and 110, 101, and 100.

FIG. 10 is a detailed configuration diagram of a delay cell constituting the delay means 823, 825, and 827 of FIG. 8.

As discussed above, the delay means 823, 825, and 827 of FIG. 8 include delay cells as in the delay stages 305 and 311 of FIG. 3. The delay means 823, 825, and 827 of Fig. 8 have the same configuration.

The delay cells of the delay means 823, 825, and 827 adjust the delay amount Dd by varying the driving force according to the number of transistors turned on in response to the delay signal and the size of the transistors. Therefore, the more the transistor is turned on, the larger the driving force is, so the delay amount Dd is reduced. Even when the number of the turned-on transistors is the same, the delay amount Dd is reduced when the large transistor is turned on.

The size of the first transistor T1 and the second transistor T2 corresponding to the most significant bit of the delay signal is the same, and the third transistor T3 and the fourth corresponding to the middle bit of the delay signal are the same. The size of the transistor T4 is the same. The size of the fifth transistor T5 and the sixth transistor T6 corresponding to the least significant bit of the delay signal is the same.

For example, if the size ratio of the first and second transistors T1 and T2 to the third and fourth transistors T3 and T4 and the fifth and sixth transistors T5 and T6 is 4: 2: 1, then the first and second transistors are used. The sizes of T1 and T2 are the largest and the sizes of the fifth and sixth transistors T5 and T6 are the smallest.

Therefore, when only one of the first and second modes mode_1 and mode_2 is an even mode, both the first and second modes mode_1 and mode_2 are either static modes or the first and second modes. When one of the modes (mode_1, mode_2) is an even mode and the other is an odd mode, the NMOS transistor and the PMOS transistor are turned on two by one, but the third and fourth transistors T3 and T4 are turned on. In the first case, the driving force of the transistor is larger than the second case in which the fifth and sixth transistors T5 and T6 are turned on, and thus the delay amount Dd is smaller.

The delay means 305 and 311 of FIG. 3 may also include transistors that are responsive to each mode and have different sizes, similar to the delay means 823, 825 and 827 of FIG. 8.

Meanwhile, the data transmission circuits of FIGS. 3 and 8 include parallel-serial conversion means instead of output means in the delay control unit so that data can be sequentially inputted after being input through a plurality of input lines. do.

11 is a configuration diagram of a data transmission circuit according to a fourth embodiment of the present invention. In particular, it is a configuration diagram of a data transmission circuit in which a transmission line for receiving data d1, d2, d3 through a plurality of input lines is three lines.

As shown in the figure, the data transmission circuit of FIG. 11 includes a plurality of first input lines line1 [3: 0] for receiving data d1 [3: 0]; A plurality of second input lines line2 [3: 0] for receiving data d2 [3: 0]; A plurality of third input lines line3 [3: 0] for receiving data d3 [3: 0]; A first transmission line line1 through which data d1 [3: 0] of the plurality of first input lines line1 [3: 0] are transmitted; A second transmission line through which data d2 [3: 0] of the plurality of second input lines line2 [3: 0] are transmitted; A third transmission line line3 through which data d3 [3: 0] of the plurality of third input lines line3 [3: 0] are transmitted; A mode sensing unit 1101 for detecting first and second modes mode_1 and mode_2 according to signal interference characteristics between transmission lines line1, line2 and line3; And adjusting the delay amount Dd of the data d1, d2, and d3 in response to the first and second modes mode_1 and mode_2, and controlling the plurality of input lines line1 [3: 0] and line2 [3: 0. ], line3 [3: 0]) to select the data (d1 [3: 0], d2 [3: 0], d3 [3: 0]) in sequence and output them to the transmission lines (line1, line2, line3) A serial converter 1103.

Unlike in FIG. 8, the data transmission circuit of FIG. 11 has four input lines (line1 [3: 0], line2 [3: 0], and line3 [3: 0) for each of three transmission lines (line1, line2, and line3). ), And each of the data (d1, d2, d3) transmitted to the three transmission lines (line1, line2, line3) is input to four input lines (line1 [3: 0], line2 [3: 0], input in parallel from line3 [3: 0]). That is, four input lines correspond to one transmission line, and input lines (line1 [3: 0], line2 [3: 0], and line3 [3: 0) corresponding to each of the transmission lines (line1, line2, and line3). ]) Each number is the same. Therefore, the number of input lines line1 [3: 0], line2 [3: 0], and line3 [3: 0] is an integer multiple of the number of transmission lines line1, line2, and line3.

In addition, the parallel-to-serial converter 1103 includes a plurality of delayed clocks clk_d1 [3: 0], clk_d2 [3: 0], and clk_d3 [3: 0] as components corresponding to the delay controller 803 of FIG. 8. Data input from a plurality of input lines (line1 [3: 0], line2 [3: 0], line3 [3: 0]) using d1 [3: 0], d2 [3: 0], d3 [3: 0]) is sequentially selected and output to the transmission lines (line1, line2, and line3) via the output driver.

On the other hand, the mode detection unit 1101 is a plurality of input lines (line1 [3: 0], line2 [3: 0], line3 [3: 0]) according to signal interference characteristics between transmission lines line1, line2, and line3. First and second modes (mode_1, mode_2) are sensed from. Therefore, if the data patterns of FIGS. 8 and 11 are the same, the first and second modes mode_1 and mode_2 of FIGS. 8 and 11 are the same.

The parallel-to-serial converting section 1103 includes parallel-to-serial converting means 1105, 1107, and 1109 instead of output means, and the parallel-to-serial converting means 1105, 1107 and 1109 include a plurality of input lines line1 [3: 0. multiple clocks with delayed data (d1 [3: 0], d2 [3: 0], d3 [3: 0]) input in parallel from each of], line2 [3: 0], line3 [3: 0]) The basic operation principle is the same as that of the delay control unit 803 of FIG. 8 except for synchronizing to (clk_d1 [3: 0], clk_d2 [3: 0], clk_d3 [3: 0]) and outputting them sequentially. do.

As a result, the output signal of the data transmission circuit of FIG. 8 and the output signal of the data transmission circuit of FIG. 10 are the same.

Meanwhile, unlike the mode sensing unit 801 of FIG. 8, the mode sensing unit 1101 of FIG. 11 does not include a flip-flop. This is because the data transmission circuit of FIG. 11 sequentially processes data inputted in parallel through four paths, thereby detecting a mode without storing the transmitted data.

The data transmission circuit of FIG. 3 may also be configured to include parallel-serial conversion means to receive data in parallel through a plurality of input lines and output the data in series. In addition, the number of the path may vary depending on the design.

Although the above has been described by the apparatus point of view of the present invention, the operation of each component constituting the data transmission circuit according to the present invention can be easily understood from the process point of view. Therefore, the operation of each component constituting the data transmission circuit of the present invention can be understood as each step of configuring the data transmission method according to the principles of the present invention. Hereinafter, a data transmission method will be described with reference to FIGS. 2 to 11.

Referring to FIG. 2, the data transmission method may further include: an input step of receiving data d1 to dn through at least two transmission lines line_1 to line_n for transmitting data d1 to dn; A mode sensing step of sensing a mode according to signal interference characteristics between transmission lines line_1 to line_n; And a delay adjusting step of adjusting the delay amount Dd of the data d1 to dn transmitted in response to the mode detection result.

The mode has three modes, i.e., the same level transition direction between the data d1 to dn, and the level transition direction between the data d1 to dn, depending on the signal interference characteristics. It includes an odd mode and a static mode that does not transition even one of the data d1 to dn.

In the even mode, the delay amount Dd is the largest, and in the odd mode, the delay amount Dd is the smallest. That is, in the even mode, the data d1 to dn are delayed most frequently, and in the odd mode, the data d1 to dn are delayed the least.

The mode sensing step outputs an even mode, an odd mode, and a static mode by comparing data d1 to dn transmitted from adjacent transmission lines among the transmission lines.

The delay adjustment step may reduce the jitter of the data (d1 to dn) received at the data receiving end by delaying and outputting the data (d1 to dn) according to each mode (mode) can achieve the object of the present invention.

3 to 11, the data transmission method may be understood as each step of configuring the data transmission method according to each configuration when there are a plurality of transmission lines.

Although the present invention has been described by means of limited embodiments and drawings, the present invention is not limited thereto and is intended to be equivalent to the technical idea and claims of the present invention by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible.

1 is a view showing a conventional data transmission circuit,

2 is a block diagram of a data transmission circuit according to a first embodiment of the present invention;

3 is a block diagram of a data transmission circuit according to a second embodiment of the present invention;

4 is a detailed configuration diagram of the mode detection unit of FIG. 3;

5 is a detailed configuration diagram of the delay unit of FIG. 3;

6A is a timing diagram of a data transmission circuit according to the prior art;

6B is a timing diagram of a data transmission circuit according to an embodiment of the present invention;

7A is an eye diagram illustrating an output signal of a data transmission circuit and a reception signal of a data receiver according to the related art;

7B is an eye diagram illustrating an output signal of a data transmission circuit and a reception signal of a data reception terminal according to an embodiment of the present invention;

8 is a configuration diagram of a data transmission circuit according to a third embodiment of the present invention;

9 is a detailed configuration diagram of a delay signal generating means of FIG. 8;

10 is a detailed configuration diagram of a delay cell constituting the delay unit of FIG. 8;

11 is a configuration diagram of a data transmission circuit according to a fourth embodiment of the present invention.

Claims (23)

At least two transmission lines for transmitting data; A mode detecting unit detecting a mode according to a signal interference characteristic between the transmission lines; And A delay adjusting unit for adjusting a delay amount of the data in response to the mode Data transmission circuit comprising a. The method of claim 1, The mode is, Even mode in which the level transition direction between the data is the same, Aud mode in which the level transition direction between the data is different, and a static mode that does not transition even one of the data. Data transmission circuit comprising a. The method of claim 2, The delay control unit, The delay amount is increased in the order of the even mode, the static mode, the odd mode Data transmission circuit. The method of claim 1, The mode detection unit, Comparing the data transmitted to the adjacent transmission line among the transmission line Data transmission circuit. The method of claim 1, The delay control unit, Delay means for adjusting a delay amount of the clock in response to the mode; And Output means for outputting the data in synchronization with the delayed clock Data transmission circuit comprising a. The method of claim 5, The delay means, One or more delay cells connected in series Including; Select one of a plurality of delayed clocks passing through the one or more delay cells in response to a selection signal; Data transmission circuit. The method of claim 5, The delay control unit, Delaying the data in response to the mode to secure a margin between the data and the delayed clock Data transmission circuit. The method of claim 5, The data transmission circuit, And outputting the mode and the data in synchronization with the clock. Data transmission circuit. A three-line transmission line for transmitting data; A mode detecting unit detecting first and second modes between adjacent transmission lines according to signal interference characteristics between the transmission lines; And A delay adjuster for adjusting a delay amount of the data in response to the first and second modes Data transmission circuit comprising a. The method of claim 9, The mode detection unit, First mode sensing means for comparing the data of the first line and the second line of the three lines to output the first mode; And Second mode detecting means for outputting the second mode by comparing data of a second line and a third line of the three lines; Data transmission circuit comprising a. The method of claim 10, The delay control unit, Delay signal generating means for outputting a delay signal according to a delay amount in response to the first and second modes; Delay means for adjusting a delay amount of a clock in response to the delay signal; And Output means for outputting the data in synchronization with a delayed clock Data transmission circuit comprising a. The method of claim 11, The delay signal generating means, Outputting a first delay signal in response to the first mode A first delay signal generator; Outputting a second delay signal in response to the first and second modes A second delay signal generator; And Outputting a third delay signal in response to the second mode 3rd delay signal generator Data transmission circuit comprising a. The method of claim 11, The delay means, One or more delay cells connected in series Including; Select one of a plurality of delayed clocks passing through the one or more delay cells in response to a selection signal; Data transmission circuit. The method of claim 11, The delay control unit, Delaying the data in response to the first and second modes to ensure a margin between the data and the delayed clock; Data transmission circuit. The method of claim 9, The data transmission circuit, And outputting the first and second modes and the data in synchronization with the clock. Data transmission circuit. A plurality of first input lines for receiving data; A plurality of second input lines for receiving data; A first transmission line through which data of the plurality of first input lines is transmitted; A second transmission line through which data of the plurality of second input lines is transmitted; A mode detecting unit detecting a mode according to the signal interference characteristics between the transmission lines; And A parallel-to-serial converter for adjusting a delay amount of the data in response to the mode and sequentially selecting data of the plurality of input lines and outputting the data to the transmission line Data transmission circuit comprising a. The method of claim 16, The data transmission circuit A plurality of third input lines for receiving data; And A third transmission line through which data of the plurality of third input lines is transmitted Data transmission circuit further comprising. The method of claim 17, The mode detection unit, A transition detecting unit for detecting a level shift of the data to be transmitted by comparing the data to be transmitted immediately before the data to be transmitted to the transmission line and the data to be transmitted; And A transition comparison unit outputting the first and second modes between the data to be transmitted in response to the detection result of the transition detection unit; Data transmission circuit comprising a. The method of claim 17, The parallel-serial converter Delay signal generating means for outputting a delay signal according to a delay amount in response to the mode; Delay means for adjusting delay amounts of a plurality of clocks in response to the delay signals; And Parallel-to-serial converting means for sequentially selecting and outputting data of the plurality of input lines in synchronization with the delayed plurality of clocks Data transmission circuit comprising a. An input step of receiving the data through at least two transmission lines for transmitting data; A mode sensing step of sensing a mode according to signal interference characteristics between the transmission lines; And A delay adjustment step of adjusting a delay amount of the data transmitted in response to the mode detection result Data transmission method comprising a. The method of claim 19, The mode is, Even mode in which the level transition direction between the data is the same, Aud mode in which the level transition direction between the data is different, and a static mode that does not transition even one of the data. Data transmission method comprising a. The method of claim 20, The delay amount is the largest in the even mode, and the delay amount is the smallest in the odd mode. Data transmission method. The method of claim 19, The mode detection step, And comparing the data transmitted to adjacent transmission lines among the transmission lines. Data transmission method.

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