KR20090088109A - Delay line in dll circuit - Google Patents

Abstract

A delay line of a DLL circuit is provided to perform a delay operation about a low frequency clock through unit delay parts of low number by setting a different delay time in a plurality of unit delay parts. A delay line of a DLL circuit includes a first delay part(10) and a second delay part(20). The first delay part includes a plurality of unit delay parts which is serially connected. The second delay part includes a plurality of unit delay parts which is serially connected, and is serially connected to the first delay part. A delay amount of the unit delay parts included in the first delay part is larger than a delay amount of the unit delay parts included in the second delay part. The first delay part receives a partial bit among delay control signals of multi-bit. The second delay part receives a rest bit among the delay control signals of multi-bit.

Description

Delay line in DLL circuit

The present invention relates to a delay locked loop (DLL) circuit, and more particularly, to a delay line of a DLL circuit.

Typically, DLL circuits are used to provide an internal clock that is time-phased relative to a reference clock obtained by converting an external clock. The DLL circuit is used to solve the problem that the internal clock utilized in the semiconductor integrated circuit is delayed through the clock buffer and the transmission line, thereby causing a phase difference with the external clock, thereby increasing the output data access time. The DLL circuit performs a function of controlling the phase of the internal clock to be a predetermined time ahead of the external clock in order to increase the effective data output interval.

The DLL circuit has a feedback loop structure, and a delay line for generating a delay clock by delaying a reference clock transmitted from a clock input buffer in response to a delay control signal, and delay elements existing in an output path of the delay clock. A replica delayer for generating a feedback clock by delaying the delayed clock with a delay modeled by a delay amount of the delayed amount; a phase sensing unit configured to generate a phase sensing signal by comparing and detecting a phase of the reference clock and the feedback clock; And a delay controller configured to generate the delay control signal in response to the phase detection signal.

The delay line may include a plurality of unit delays connected in series, and determine a delay time with respect to the reference clock according to the number of unit delays of the delay control signal, which is implemented as a plurality of digital signals. However, each of the unit delays included in the delay line had the same amount of delay. Therefore, when the input reference clock is a low frequency, a situation in which more delay time may be provided than in the case of a high frequency may occur, and thus, a large number of unit delay units have to be provided. As a result, the area occupied by the delay line was not small, which caused a reduction in the area margin of the DLL circuit seeking high integration. In addition, there was a technical limitation that it is not easy to reduce the time required for the delay lock operation of the DLL circuit.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and there is a technical problem to provide a delay line of a DLL circuit which reduces the occupied area and improves the area efficiency.

In addition, another object of the present invention is to provide a delay line of a DLL circuit that reduces the time required to complete a delay lock and more efficiently supports a high speed operation of a semiconductor integrated circuit.

Delay line of the DLL circuit according to an embodiment of the present invention for achieving the above technical problem, the first delay unit having a plurality of unit delay connected in series; And a second delay unit having a plurality of unit delay units connected in series and connected in series with the first delay unit, wherein the plurality of unit delay units provided in the first delay unit include: Each of the plurality of unit delay units provided has a larger delay amount.

In addition, the delay line of the DLL circuit according to another embodiment of the present invention includes a plurality of serially connected unit delayer for delaying the reference clock in response to each bit of the delay control signal of the plurality of bits to output a delay clock, Each of the plurality of unit delay units has a different delay amount, and a smaller unit delay unit is closer to the output terminal of the delay clock.

Delay line of the DLL circuit of the present invention, by setting a differential delay time to a plurality of unit delay, it is possible to perform a delay operation for a low frequency clock with only a small number of unit delay delay to reduce the occupied area have.

In addition, the delay line of the DLL circuit of the present invention has the effect of reducing the time required for the completion of the delay fixing to support the high speed operation of the semiconductor integrated circuit more efficiently.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a block diagram showing the configuration of a delay line of a DLL circuit according to an embodiment of the present invention.

As shown, the delay line of the DLL circuit according to an embodiment of the present invention includes a first delay unit 10 and a second delay unit 20.

The first delay unit 10 includes n unit delay units UD1 <1: n> connected in series, and the second delay unit 20 includes m unit delay units UD2 <1: m connected in series. >). At this time, the first delay unit 10 and the second delay unit 20 are connected in series. That is, the n-th unit delay unit UD1 <n> of the first delay unit 10 and the first unit delay unit UD2 <1> of the second delay unit 20 are connected in series. .

A total of n + m unit delays UD1 <1: n> and UD2 <1: m> provided in the first delay unit 10 and the second delay unit 20 are n + m bits, respectively. It operates in response to each bit of the delay control signal dlycnt <1: n + m>. In this case, it is preferable that the delay control signal dlycnt <1: n + m> of the n + m bit includes one signal having a logic value of '1'. The delay path of the reference clock (clk_ref) is set through one unit delay unit to which a bit having a logic value of '1' is input among the n + m bit delay control signals dlycnt <1: n + m>. The phase of the delay clock clk_dly is determined according to the length of the delay path.

By the above-described configuration, the second delay unit 20 operates regardless of the frequency of the reference clock clk_ref. However, the first delay unit 10 operates only when the frequency of the reference clock clk_ref is lower than or equal to a predetermined frequency, that is, when a low frequency clock is input. This is because, if the frequency of the reference clock clk_ref is less than or equal to the predetermined frequency, the range of delay time that the delay line gives to the reference clock clk_ref is widened. Conventionally, the unit delayers UD1 <1: n> included in the first delay unit 10 that operate only when the low frequency clock is input as described above also include the unit delay units provided in the second delay unit 20. It has the same delay amount as (UD2 <1: m>). Therefore, when the reference clock clk_ref is cursed, a large number of unit delay units should be provided in order to provide a delay amount close to one period of the reference clock clk_ref.

However, in the present invention, the unit delay units UD1 <1: n> provided in the first delay unit 10 are unit delay units UD2 <1: m> provided in the second delay unit 20. Has a larger delay than. Therefore, when the reference clock (clk_ref) is a low frequency clock and a large delay time needs to be provided, the delay lock operation may be performed by changing the delay time in larger units, and thus the time until the delay lock operation is completed. That is, the locking time is shortened. In addition, since the normal operation is possible even if the first delay unit 10 includes only a smaller number of unit delayers, the area occupied by the delay line is reduced.

In the above description, the delay time of each unit delay unit UD1 <1: n> in the first delay unit 10 and the unit delay units UD2 <1: m> in the second delay unit 20 are described above. Explained that the delay time is different. However, it can be seen that all the unit delays UD1 <1: n> and UD2 <1: m> included in the delay line each have a differential delay amount. At this time, it is preferable that the unit delayers closer to the output terminal of the delay clock clk_dly among the unit delayers UD1 <1: n> and UD2 <1: m> have a smaller delay amount. Even in this case, when a low frequency clock is input, the delay lock operation may be performed while changing the delay time in larger units.

FIG. 2 is a configuration diagram of the unit delay unit shown in FIG. 1, and since the n + m unit delay units UD1 <1: n> and UD2 <1: m> are configured in the same form, any one unit The description of the delay unit UD1 <i> is shown to replace the description of the remaining unit delay unit.

As illustrated, the unit delay unit UD1 <i> may include a first NAND gate ND1 that receives a corresponding bit dlycnt <i> and the reference clock clk_ref among the delay control signals; A second NAND gate ND2 that receives the output signal of the first NAND gate ND1 and the output signal of the previous unit delay unit UD1 <i-1>; A third NAND gate ND3 receiving the output signal of the second NAND gate ND2 and an external supply power supply VDD; And a resistor element R for delaying the third NAND gate ND3 by a predetermined time.

Although not illustrated, the unit delay unit UD1 <1> provided at the front end of the n + m unit delay units UD1 <1: n> and UD2 <1: m> may have a unit in front of it. Since there is no output signal of the retarder, it is preferable to receive the external power supply VDD instead.

Further, the unit delay unit UD2 <m> provided at the rearmost end of the n + m unit delay units UD1 <1: n> and UD2 <1: m> may be configured to receive the delay clock clk_dly. Will print.

The resistance element R is provided so that each unit delay unit has a predetermined delay time, and as described above, the resistance element R is designed to have a differential resistance value in each delay unit unit or in each unit delay unit. Such a configuration of the unit delay unit allows the delay line to complete the delay fixing operation faster than the delay operation for the low frequency clock, and can have fewer unit delay units.

3A and 3B are timing diagrams for explaining the operation of the delay line of the DLL circuit shown in FIG.

FIG. 3A illustrates a process of changing the phase of the delayed clock clk_dly when the reference clock clk_ref is a high frequency clock, and FIG. 3B illustrates the delayed clock when the reference clock clk_ref is a low frequency clock. A process of changing the phase of (clk_dly) is shown.

The delay line generates the delay clock clk_dly by changing the delay value in a relatively small unit when the reference clock clk_ref is a high frequency clock. On the other hand, when the reference clock clk_ref is a low frequency clock, the delay line generates the delay clock clk_dly by changing the delay value in a relatively large unit.

As such, the delay line may perform a faster delay operation when the reference clock clk_ref is a low frequency clock. This results in only a smaller number of unit delays in the delay line.

As described above, the delay line of the DLL circuit of the present invention includes a unit delayers having a large delay value in an area that operates only when a low frequency clock is input, and an area that operates regardless of the frequency of an input clock. Has unit delays with small delay values. With this arrangement, it is possible to support a reduced locking time at the time of input of the low frequency clock. In addition, since it is possible to perform a normal operation even with only a relatively small unit delay compared to the prior art, there is an advantage that can support the high integration implementation of the semiconductor integrated circuit. In addition, by having only a small number of unit delays, it is possible to reduce the current consumed by the delay line and further improve the power efficiency of the entire DLL circuit.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a block diagram showing the configuration of a delay line of a DLL circuit according to an embodiment of the present invention;

2 is a configuration diagram of a unit delay unit shown in FIG. 1;

3A and 3B are timing diagrams for explaining the operation of the delay line of the DLL circuit shown in FIG.

<Description of the symbols for the main parts of the drawings>

10: first delay unit 20: second delay unit

Claims (8)

A first delay unit having a plurality of unit delay units connected in series; And And a second delay unit having a plurality of unit delay units connected in series and connected in series with the first delay unit. The delay lines of the DLL (Delay Locked Loop) circuit, characterized in that each of the plurality of unit delay units provided in the first delay unit has a larger delay than the plurality of unit delay units provided in the second delay unit. . The method of claim 1, The first delay unit receives a part of bits of the delay control signal of the plurality of bits, the second delay unit receives the remaining bits of the delay control signal of the plurality of bits, and responds to a logic value of the delay control signal of the plurality of bits. The delay line of the DLL circuit, characterized in that the delay path is set through any one of the unit delay units provided in the first and second delay units. The method of claim 2, Each of the plurality of unit delayers, A first NAND gate configured to receive a corresponding bit of the delay control signal and the reference clock; A second NAND gate receiving the output signal of the first NAND gate and the output signal of the unit delay unit of the previous stage; A third NAND gate configured to receive an output signal of the second NAND gate and an external supply power; And A resistance element for delaying the output signal of the third NAND gate by a predetermined time; Delay line of the DLL circuit comprising a. The method of claim 3, wherein And the unit delay unit provided in the first delay unit and the unit delay unit provided in the second delay unit include the resistance elements having different resistance values. A plurality of serially connected unit delayers for delaying a reference clock in response to each bit of the plurality of bits of the delay control signal and outputting a delayed clock; And each of the plurality of unit delay units has a different delay amount and a smaller delay unit is closer to an output terminal of the delay clock. The method of claim 5, wherein Each of the plurality of unit delayers receives one bit of a plurality of bit delay control signals, and a delay path through any one of the plurality of unit delayers is set in response to a logic value of the plurality of bit delay control signals. Delay line of a DLL circuit, characterized in that. The method of claim 5, wherein Each of the plurality of unit delayers, A first NAND gate configured to receive a corresponding bit of the delay control signal and the reference clock; A second NAND gate receiving the output signal of the first NAND gate and the output signal of the unit delay unit of the previous stage; A third NAND gate configured to receive an output signal of the second NAND gate and an external supply power; And A resistance element for delaying the output signal of the third NAND gate by a predetermined time; Delay line of the DLL circuit comprising a. The method of claim 7, wherein And the plurality of unit delay units include the resistance elements having different resistance values.

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