KR20090084168A - Image sensor and fabricating method thereof - Google Patents

Abstract

An image sensor and a manufacturing method thereof are provided to improve the electric charge accumulation ability by forming the effective potential barrier. An isolation insulating layer(121) is formed within a substrate. A separation impurity region(122a) of the first conductivity type is formed under the isolation insulating layer into multilayer. An impurity region(122b) of the second conductive type is formed with multilayer within the substrate. The deep well of the first conductivity type is formed within the substrate. The separation impurity region formed with multilayer contacts to the deep well. The impurity of the first conductivity type is ion-implanted into the substrate at the plurality of times. The separation impurity region of multilayer is formed in the isolation insulating layer.

Description

Image sensor and manufacturing method thereof

The present invention relates to an image sensor and a method of manufacturing the same, and more particularly, to a MOS image sensor and a method of manufacturing the same.

An image sensor converts an optical image into an electrical signal. Recently, with the development of the computer industry and the communication industry, the demand for improved image sensors in various fields such as digital cameras, camcorders, personal communication systems (PCS), gaming devices, security cameras, medical micro cameras, robots, etc. is increasing. have.

The MOS image sensor is simple to drive and can be implemented by various scanning methods. In addition, since the signal processing circuit can be integrated on a single chip, the product can be miniaturized, and the MOS process technology can be used interchangeably to reduce the manufacturing cost. Its low power consumption makes it easy to apply to products with limited battery capacity. Therefore, the use of the MOS image sensor is rapidly increasing as technology is developed and high resolution is realized.

However, in order to satisfy the increased resolution, as the degree of integration of pixels increases, the volume of a photoelectric conversion element, such as a photodiode per unit pixel, becomes smaller, resulting in a lower sensitivity.

In addition, as the density of pixels increases, the distance between pixels gets closer, and crosstalk occurs frequently between adjacent pixels. Pixel-to-pixel crosstalk is reflected light 6a formed by reflecting light incident through a microlens and / or a color filter (not shown) on the upper or side surfaces of the metal wires M1, M2, and M3 as shown in FIG. 1. The adjacent photo, not the photodiode 4, in which incident light is to be accumulated by the refractive light 6b formed by refracting at the surface of the non-uniform film or the multilayer structure composed of the interlayer insulating films 5a, 5b, and 5c having different refractive indices. Optical crosstalk A transmitted to the diode 4 and another hole pair (EHP) formed outside the depletion region of the photoelectric conversion element 2 by the long wavelength incident light 7 are adjacent to each other by diffusion. It can be divided into electrical crosstalk (B) delivered to the diode (2).

When crosstalk occurs, the resolution of the black and white image sensor may be lowered, which may cause distortion of the image. In addition, in the case of a color image sensor using a color filter array (CFA) of red, green, and blue, there is a possibility of crosstalk due to red incident light having a long wavelength. Large, and may result in tint defects.

However, as shown in FIG. 1, separation between the photodiodes 4 and prevention of electrical crosstalk are made by a separation insulating film (for example, STI) 3a and a p-type isolation impurity region 3b. Can be. By the way, the isolation impurity region 3b is formed by ion implantation. Therefore, the isolation impurity region 3b is not formed deep enough, so the isolation impurity region 3b does not sufficiently perform the function of the electrical crosstalk barrier.

An object of the present invention is to provide an image sensor with reduced crosstalk and increased sensitivity.

Another object of the present invention is to provide a method of manufacturing an image sensor having reduced crosstalk and increased sensitivity.

Problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

One aspect of the image sensor of the present invention for achieving the above technical problem is a substrate, a separation insulating film formed in the substrate, a separation impurity region of the first conductivity type formed in multiple layers under the separation insulating film, and a second conductive formed in the substrate in multiple layers It includes a photodiode including an impurity region of the type.

One aspect of the manufacturing method of the image sensor of the present invention for achieving the above another technical problem is to form a separation insulating film in the substrate, a plurality of ion-implanted impurities of the first conductivity type in the substrate, to separate the multilayer of the insulating insulating film An impurity region is formed, and a second conductive type of impurity is ion implanted into the substrate a plurality of times to form a photodiode including a multilayer impurity region.

Other specific details of the invention are included in the detailed description and drawings.

Other specific details of the invention are included in the detailed description and drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Thus, in some embodiments, well known process steps, well known device structures and well known techniques are not described in detail in order to avoid obscuring the present invention.

Like reference numerals refer to like elements throughout the specification. ″ And / or ″ includes each and all combinations of one or more of the items mentioned. As used herein, including and / or comprising the components, steps, operations and / or elements mentioned exclude the presence or addition of one or more other components, steps, operations and / or elements. I never do that. In addition, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

Hereinafter, for convenience of description, the description will be made using the MOS image sensor. However, the present invention can also be applied to other image sensors such as charge coupled devices (CCDs). In addition, in the following MOS image sensor, an active pixel sensor (APS) array is configured with four shared pixels, in which four photoelectric conversion elements share a read element, as a unit pixel. It is not limited. For example, a shared pixel in which two photoelectric conversion elements share a read element, and a single pixel in which adjacent photoelectric conversion elements do not share a read element may be used as a unit pixel.

In addition, the unit pixel includes a photoelectric conversion element, a floating diffusion region (hereinafter referred to as FD) for reading out charges accumulated in the photoelectric conversion element, and a plurality of reading elements. The read element may include a select element, a drive element, and a reset element. As the photoelectric conversion element, a photo transistor, a photo gate, a photodiode (hereinafter referred to as PD), a pinned photodiode (hereinafter referred to as PPD), or a combination thereof may be applied. In the case of MOS image sensors, PD or PPD is mainly used. Hereinafter, if the photoelectric conversion element can be implemented as a PD or a PPD, it is described as a PD, and specifically, these are referred to separately when the PPD is illustrated.

2 is an equivalent circuit diagram of an APS array unit of a 4-shared pixel image sensor according to some embodiments of the inventive concept.

Referring to FIG. 2, the quadruple pixel P includes four PDs 11a, 11b, 11c, and 11d. Four PDs 11a, 11b, 11c, and 11d absorb incident light and accumulate charge corresponding to the amount of light. Four PDs 11a, 11b, 11c, 11d are coupled with respective charge transfer elements 15a, 15b, 15c, 15d which transfer the accumulated charge to FD 13. The floating diffusion region 13 is made of a first FD 13a shared by two PDs 11a and 11b and a second electrically shared with the first FD 13a and shared by two other PDs 11c and 11d. 2 FD 13b. Since the parasitic capacitances of the first FD 13a and the parasitic capacitances of the second FD 13b are connected in series, the overall parasitic capacitance of the FD 13 can be minimized so that a sufficient amount of charge is transferred to the drive element 17. Can be used as a driving voltage.

In the four shared pixels P, four PDs 11a, 11b, 11c, and 11d share the drive element 17, the reset element 18, and the selection element 19.

The drive element 17 illustrated as a source follower amplifier amplifies a change in the electrical potential of the FD 13 that receives the charge accumulated in each PD 11a, 11b, 11c, 11d and sends it to the output line Vout. Output

The reset element 18 periodically resets the FD 13 to a reference value. The reset element 18 may consist of one MOS transistor driven by a bias provided by a reset line RX (i) applying a predetermined bias. When the reset element 18 is turned on by a bias provided by the reset line RX (i), a predetermined electrical potential provided to the drain of the reset element 18, for example, a power supply voltage VDD, is applied to the FD 13. Is passed to.

The selection element 19 serves to select four shared pixels P to be read out in units of rows. The selection element 19 may consist of one MOS transistor driven by a bias provided by the row select line SEL (i). When the selection element 19 is turned on by the bias provided by the row select line SEL (i), a predetermined electrical potential provided to the drain of the selection element 19, for example, a power supply voltage VDD, is driven by the drive element (i. 17) to the drain region.

Transmission lines TX (i) a, TX (i) b, TX (i) c, TX (i) d) and reset elements 18 for applying a bias to the charge transfer elements 15a, 15b, 15c, and 15d. The reset line RX (i) for applying a bias to and the row selection line SEL (i) for applying a bias to the selection element 19 may be arranged to extend substantially parallel to each other in the row direction.

The layout of the APS array portion of the 4-shared pixel image sensor in accordance with embodiments of the present invention is illustrated in FIG. 3.

Referring to FIG. 3, an APS array unit of a 4-shared pixel image sensor according to some embodiments of the present invention may include a first active A1 in which two PDs PD1 and PD2 sharing a first FD FD1 are formed. And second active (A2) pairs on which two PDs (PD3, PD4) sharing a second FD (FD2) are formed are arranged in a matrix form in a repeating unit, and each of the first and second active pairs A1 and A2. The APS array unit is made in such a way that two independent read element actives, third and fourth actives A3 and A4, are assigned. That is, the first to fourth actives A1, A2, A3, and A4 constitute unit active of the four shared pixels.

The first active A1 is a one axis merged dual lobes type active, and the second active A2 is a no axis merged dual lobes type active.

Specifically, in the first active A1, a dual lobe active a is merged into one axis active b through the connection active c. The dual lobe active a faces in the column direction about the axis active b. Thus, uniaxially merged dual lobe actives are substantially similar in appearance to the hypocotyls of young dicotyledonous plants and to a dual cotyledon branched from the hypocotyls. The dual lobe active a is an active in which two PDs PD1 and PD2 are formed, and the connection active c is a first FD FD1 active.

In the second active A2, dual lobe actives a are merged into one through the connection active c without an axis. The dual lobe actives a face in the column direction. Thus, the shaftless merged dual-lobed active is substantially similar in appearance to a dual cotyledon of young dicotyledonous plants. The dual lobe active a is an active in which two PDs are formed, and the connection active c is a second FD (FD2) active.

In the axis active b, it may be advantageous in view of the efficiency of the wiring that the reset gate RG is arranged to form the reset element. Since the reset element functions to periodically reset the floating diffusion region FD, it may be advantageous to form the junction of the floating diffusion region FD and the reset element as one in terms of minimizing the wiring. However, the element formed in the axis active b is not limited to the reset element. The dummy gate DG having substantially the same shape as the reset gate RG may be arranged in the connection portion and the adjacent region of the second active A2 for repeatability of the arrangement. One read element is formed in each of the third active A3 and the fourth active A4. When the reset element is formed in the axis active b, a drive element may be formed in the third active A3 and a selection element may be formed in the fourth active A4. Therefore, the source follower gate SFG of the drive device may be disposed in the third active A3, and the select gate RSG of the select device may be disposed in the fourth active A4. However, the selection element may be formed in the third active A3 or the drive element may be formed in the fourth active A4 depending on how the wiring is formed.

4 is a cross-sectional view illustrating an example embodiment of a 4-shared pixel image sensor formed according to the circuit diagrams and layouts shown in FIGS. 2 and 3. 4 is a cross-sectional view taken along line IV-IV 'of FIG. 3.

Referring to FIG. 4, the isolation region 120 used in the APS array unit includes a separation insulating layer (eg, STI) 121 and p-type isolation impurity regions 122a, 122b, and 122c formed in multiple layers. . The isolation region 120 is not only an isolation region for separating the PD and the PD, but also serves as an electrical crosstalk barrier.

Also, a PD formed of n-type impurity regions formed in multiple layers may be formed in the PD active (a) of the APS array unit. Specifically, FIG. 4 illustrates a PPD including a first conductivity type, for example, a p-type impurity region 143 and a lower second conductivity type, for example, an n-type impurity regions 141a, 141b, and 141c. PPDs are commonly implemented in APS array designs because of the benefits of dark current and therefore noise reduction.

In the isolation region 120, the p-type isolation impurity regions 122a, 122b, and 122c are formed in multiple layers, and the n-type impurity regions 141a, 141b, and 141c are formed in multiple layers in the PD.

As the pixel density increases, the size of the PD active (a) decreases. Therefore, to maximize the volume of the PD, the depth of the PD must be deep. If the n-type impurity regions 141a, 141b, and 141c are formed in multiple layers, the depth of the PD can be deepened to maximize the volume of the PD and can easily adjust the potential profile of the PD. In other words, the pool portion (ie, the portion where charges are collected) of the potential profile of the PD can be disposed close to the channel region of the charge transfer element. This arrangement facilitates transfer of charges accumulated in the PD to the floating diffusion region. Thus, it is possible to maximize the volume of the PD and increase the sensitivity.

In addition, as the depth of the PD becomes deeper, the depth of the separation region 120 must also be deepened to separate between the PD and the PD. Therefore, in FIG. 4, the p-type isolation impurity regions 122a, 122b, and 122c are formed in multiple layers to control the depth of the isolation region 120. By making the depth of the isolation region 120 deep enough, it is possible to reduce electrical crosstalk and blooming shapes.

Meanwhile, when the isolation region 120 contacts the p-type deep well 103, a closed electrical crosstalk barrier may be completed in most regions. More specifically, the p-type isolation impurity region 122c formed at the bottom layer may contact the p-type deep well 103. The p-type deep well 103 is spaced apart from the surface of the substrate 100 to represent a first conductivity type (p-type) impurity layer formed in the substrate 100, specifically, the p-type epi layer 101b. The p-type deep well 103 forms a potential barrier to prevent EHP generated from the substrate 101a or the p-type epitaxial layer 101b from thermally diffusing into the PPD and to increase recombination of electrons and holes. It is an electrical crosstalk barrier that reduces electrical crosstalk by random drift of electrons. Therefore, when the bottom of the isolation region 120 contacts the p-type deep well 103, a minimum closed electrical crosstalk barrier may be formed.

In FIG. 4, the n-type impurity regions 141a, 141b, and 141c of the PD are formed into three layers, and the p-type isolation impurity regions 122a, 122b and 122c of the isolation region 120 are formed into three layers. Although shown in figure, it can also be comprised, for example by 2 layers, 4 layers, etc. according to process conditions.

4 illustrates a case in which the substrate 100 includes a p-type bulk substrate 101a and a p-type epitaxial layer 101b thereon. For convenience of the formation process, the p-type epi layer 101b may be formed to have a thickness of 3 to 5㎛. When the p-type epi layer 101b is used, the dopant concentration of the p-type epi layer 101b and the p-type deep well 103 may be controlled to form an effective potential barrier, thereby improving charge accumulation capability.

In FIG. 4, reference numeral 160 denotes a silicon oxide film and / or transparent resin filled in the light transmitting part, 170 denotes a planarization layer, 180 denotes a color filter, and 190 denotes a microlens. Although the wiring layers M1, M2, and M3 are illustrated in three layers in the drawing, two layers may be formed depending on the image sensor.

A readout element may be formed in the APS array unit, and a CMOS element, a resistor, a capacitor, etc., formed simultaneously with the readout element may be formed in the peripheral circuit unit, and they may be implemented in various forms well known to those skilled in the art, so that the present invention is not obscured. For the sake of brevity, descriptions thereof are omitted without giving individual reference numerals.

5A through 5C are intermediate diagrams for describing a method of manufacturing the 4-shared pixel image sensor of FIG. 4.

Referring to FIG. 5A, a separation insulating layer 121 is formed in the substrate 100 on which the p-type deep well 103 is formed. Subsequently, p-type impurities are implanted into the substrate 100 to form a p-type isolation impurity region 122a under the isolation insulating layer 121.

Referring to FIG. 5B, two p-type isolation impurity regions 122b and 122c are further formed by ion implanting the p-type impurity under the p-type isolation impurity region 122a. The isolation impurity regions 121a, 121b, and 121c may be formed to contact the deep well 103.

Referring to FIG. 5C, three n-type impurity regions 141a, 141b, and 141c are formed in the PD active a by implanting n-type impurities into the substrate 100.

6 is an intermediate step diagram for explaining another method of manufacturing the quadruple pixel image sensor of the present invention. In the above-described manufacturing method (FIGS. 5A-5C), the steps of FIG. 6 can be entered instead of the steps of FIG. 5B.

That is, referring to FIG. 6, two p-type isolation impurity regions 122b and 122c may be formed by implanting p-type impurities into the entire APS array unit (ie, may be formed in a blank manner). . Although it may vary according to process conditions, for example, p-type impurities may be ion-implanted only in the entire APS array unit, or p-type impurities may be ion-implanted in the entire APS array unit and the entire peripheral circuit unit.

Although not described with reference to the drawings, the p-type isolation impurity region (122a in FIG. 5A) may also be formed by ion implantation of p-type impurities into the entire APS array portion.

That is, all of the p-type isolation impurity regions 122a, 122b, and 122c may be formed only below the isolation insulating film 121 using a mask, and all of the p-type isolation impurity regions 122a, 122b, and 122c may be formed blank. Alternatively, only a part of the p-type isolation impurity regions 122a, 122b, and 122c may be formed as blank.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

1 is a cross-sectional view of a conventional image sensor.

2 is an equivalent circuit diagram of an APS array unit of a 4-shared pixel image sensor according to example embodiments.

3 is a layout of an APS array unit of a 4-shared pixel image sensor according to example embodiments.

4 is a cross-sectional view illustrating an example embodiment of a 4-shared pixel image sensor formed according to the circuit diagrams and layouts shown in FIGS. 2 and 3.

5A through 5C are intermediate diagrams for describing a method of manufacturing the 4-shared pixel image sensor of FIG. 4.

FIG. 6 is an intermediate view illustrating another method of manufacturing the 4-shared pixel image sensor of FIG. 4.

(Explanation of symbols for the main parts of the drawing)

120: isolation region 121: isolation insulating film

122a, 122b, 122c: separation impurity region

141a, 141b, and 141c: n-type impurity region of the photodiode

Claims (4)

Board; A separation insulating film formed in the substrate; A separation impurity region of a first conductivity type formed under the isolation insulating layer in a multilayer manner; And And a photodiode including a second conductivity type impurity region formed in multiple layers in the substrate. The method of claim 1, Further comprising a deep well of the first conductivity type formed in the substrate, And an isolation impurity region formed in the multilayer contacting the deep well. Forming a separation insulating film in the substrate, A plurality of ion-implanted impurities are implanted into the substrate a plurality of times to form a plurality of isolation impurity regions under the isolation insulating film, And ion implanting a plurality of second conductivity type impurities into the substrate to form a photodiode including a multilayer impurity region. The method of claim 3, wherein Further comprising a deep well of the first conductivity type formed in the substrate, The multi-layered impurity region is formed in contact with the deep well.

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