KR100664863B1 - Cmos image sensor with improved integration and method for fabrication thereof - Google Patents

Abstract

The present invention is to provide a structure and a manufacturing method of a CMOS image sensor that can increase the integration and resolution at the same time, for this purpose, the present invention generates an image for three colors having a relationship of λ 1> λ 2> λ 3 A CMOS image sensor comprising: a first photodiode for generating an image of a color corresponding to λ 1; A second photodiode disposed on the first photodiode and generating an image of a color corresponding to λ2; And a third photodiode disposed on the second photodiode and configured to generate an image having a color corresponding to λ 3.

The present invention also provides a method for manufacturing a CMOS image sensor.

CMOS image sensor, photodiode, laminated structure, silicon layer.

Description

CMOS image sensor with improved density and its manufacturing method {CMOS IMAGE SENSOR WITH IMPROVED INTEGRATION AND METHOD FOR FABRICATION THEREOF}             

1 is a circuit diagram illustrating a unit pixel of a CMOS image sensor including four transistors in one unit pixel.

2 is a plan view schematically illustrating a CMOS image sensor having the structure of FIG.

3 is a plan view showing an arrangement of a minimum unit pixel for including all three colors;

4 is a plan view of a CMOS image sensor showing three unit pixels having four transistors and one photodiode as unit pixels according to an embodiment of the present invention;

5A to 5F are cross-sectional views illustrating an image sensor manufacturing process according to an embodiment of the present invention.

6 is a cross-sectional view of a CMOS image sensor showing three unit pixels according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100 substrate 101 device isolation film

102 gate insulating film 103 gate conductive film

104: n1-region 105: spacer

106a, 106b, 106c: Source / drain junction 107: P10 region

108: first insulating film 109: first silicon layer

110: second insulating film 111: n2- region

112: P20 region 113, 118: impurity region

114: second silicon layer 115: third insulating film

116: n3-zone 117: P30 zone

119: fifth insulating film 120a to 120d: metal contact

121a to 121c: Metal line 122: Protective insulating film

123: insulating film for planarization 124: microlens

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS image sensor, and in particular, by arranging planarly to share photodiodes arranged in a stacked structure to receive light of three different wavelengths in three transistor groups constituting a unit pixel, high integration and high image quality The present invention relates to a CMOS image sensor and a method of manufacturing the same.

An image sensor is a semiconductor device that converts an optical image into an electrical signal. An image sensor is a charge coupled device (CCD) and a CMOS (Complementary MOS) image sensor. Is made of.

A CCD is a device in which individual metal oxide semiconductor (MOS) capacitors are arranged so close to each other that charge carriers are stored and transported in the capacitor.

On the other hand, the CMOS image sensor includes a transistor for driving one photodiode and three or four unit pixels in one unit pixel by applying a semiconductor CMOS process. CMOS image sensor uses CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits, makes MOS transistors to drive as many pixels, and uses them sequentially to output Is a device that adopts a switching method for detecting.

In manufacturing such various image sensors, efforts are being made to increase the photo sensitivity of the image sensor, and one of them is a light collecting technology. For example, a CMOS image sensor is composed of a photodiode for detecting light and a portion of a CMOS logic circuit for processing the detected light into an electrical signal to make data, and in order to increase the light sensitivity, the area of the photodiode in the total image sensor area ( Efforts are being made to increase this, usually referred to as "fill factor."

1 is a circuit diagram illustrating a unit pixel of a CMOS image sensor including four transistors in one unit pixel.

In the unit pixel illustrated in FIG. 1, a sub-micron CMOS epi process is applied to increase sensitivity and reduce cross talk effects between unit pixels.

Referring to FIG. 1, a unit pixel of an image sensor may have a structure of PNP, PNPN, etc., and receives a light to form an electron-hole pair, ie, a photogenerated charge, as much as the photodiode PD. And transfer the photocharges accumulated by the turn-on operation of the transfer transistor Tx and the transfer transistor Tx to transfer the photocharges accumulated in the photodiode to the floating diffusion node FD according to the turn-on operation. The floating diffusion node FD received, the reset transistor Rx for resetting the floating diffusion node FD to the power supply voltage VDD level according to the reset signal, and the photocharge transferred from the floating diffusion node FD. The amount of turn-on varies according to the corresponding electric signal. Accordingly, the drive transistor Dx outputs an electric signal proportional to the amount of photocharge, and the drive transistor Dx is turned on under the control of the select signal. To And a select transistor Sx for outputting a signal of a unit pixel output through the unit pixel.

For example, the gate of the select transistor Sx is controlled by a low select signal, and outputs a signal of a unit pixel to the column line Col through its source terminal.

As can be seen from the above structure, one unit pixel includes four transistors and one photodiode. (In some cases, three transistors and one photodiode may be included.)

FIG. 2 is a plan view schematically illustrating a CMOS image sensor having the structure of FIG. 1.

Referring to FIG. 2, the active region ACT is arranged to be extended in a line form after bending 90 ° to the left from the square photodiode PD region, and the photodiode PD in the square region of the active region ACT. Is formed. The transfer transistor Tx having the source / drain, the reset transistor Rx, the drive transistor Dx, and the select transistor Sx in the active region ACT are arranged at regular intervals. Therefore, one unit pixel has four transistors and one photodiode in a planar quadrilateral shape (or polygonal shape).

In FIG. 2, only the gate forming the active region ACT and four transistors in a unit pixel under one color filter passing only light in a specific wavelength range is illustrated. However, source / drain junctions, metal contacts, Metal lines and via contacts should be included.

As such, one unit pixel uses a single color filter to obtain a single color image.

3 is a plan view illustrating an arrangement of a minimum unit pixel to include all three colors.

Referring to FIG. 3, a first pixel U / C1 for obtaining an image of a red (R) color, and second and third pixels U / C2 and U / C3 for an image of a green (G) color are obtained. ) And a fourth pixel (U / C4) for obtaining an image of a blue (B) color are arranged in a structure of 2 * 2, and each unit pixel includes four transistors and one photodiode.

As shown in FIG. 3, only one image of one color is obtained in one pixel, and three colors of the pixel are obtained by interpolating using data of unit pixels of another neighboring color.

Therefore, at least three (3 to 9) unit pixels are required for the image sensor to electrically convert an image for all visible light regions, that is, natural colors.

This is currently the biggest weakness in terms of the density and resolution of CMOS image sensors.

The present invention proposed to solve the problems of the prior art as described above, the object of the present invention is to provide a structure and a manufacturing method of a CMOS image sensor that can increase the integration and resolution at the same time.

In order to achieve the above object, the present invention is a CMOS image sensor for generating an image for three colors having a relationship of λ1> λ2> λ3, the first photo for generating an image of a color corresponding to λ1 diode; A second photodiode disposed on the first photodiode and generating an image of a color corresponding to λ2; And a third photodiode disposed on the second photodiode and configured to generate an image having a color corresponding to λ 3.

In addition, in order to achieve the above object, the present invention is formed on a silicon substrate of the first conductivity type in a CMOS image sensor for generating an image for three colors having a relationship of λ1> λ2> λ3, a first photodiode for generating a color image of λ1; A plurality of transistors formed on the substrate; A first silicon layer of a first conductivity type formed on the first photodiode; A second photodiode formed on the first silicon layer and configured to generate a color image of λ2; A second silicon layer of a first conductivity type formed on the second photodiode; And a third photodiode formed on the second silicon layer, the third photodiode for generating a color image of λ3.

In addition, in order to achieve the above object, the present invention provides a CMOS image sensor manufacturing method for generating an image for three colors having a relationship of λ1> λ2> λ3. Forming a first photodiode for color image generation; Forming a first insulating film on an entire surface of the first photodiode; Forming a plurality of transistors on the first insulating layer; Forming a second insulating layer on the entire surface where the plurality of transistors are formed to be thicker than the thickness of the sum of the second photodiode and the third photodiode; Selectively etching the second insulating layer to expose at least an upper portion of the first photodiode; Forming a first silicon layer of a first conductivity type in a predetermined thickness in the exposed region; Forming a second photodiode on the first silicon layer; Forming a third insulating film on the second photodiode; Forming a second silicon layer of a first conductivity type on the third insulating layer at a predetermined thickness; And it provides a CMOS image sensor manufacturing method comprising the step of forming a third photodiode on the second silicon layer.

According to the present invention, photodiodes are arranged in a stacked structure so that three unit pixels are put together in a plane, and each transistor is disposed on the same plane as the lowermost photodiode.

This is based on the fact that each wavelength (R, G, B) of visible light varies in light efficiency depending on the depth of silicon. The present invention is designed to convert the photodiode in response to each wavelength in three in the vertical direction to be converted electrically. Compared to the conventional method in which four pixels in the horizontal direction electrically react to each wavelength using each color filter, the present invention vertically arranges three photodiodes so that visible light is not used without using a color filter. By enabling the generation of electrical signals in accordance with the depth of the, the integration degree of the CMOS image sensor is increased by two to three times.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

4 is a plan view of a CMOS image sensor showing three unit pixels having four transistors and one photodiode as unit pixels according to an embodiment of the present invention.

Here, three colors, for example, RGB or YMgCy, are described as RGB as the three primary colors of light, and have a relationship of λ 1 (R)> λ 2 (G)> λ 3 (B).

Referring to FIG. 4, a first photodiode PD1 for generating an image of a color corresponding to λ1 is disposed at a lowermost portion, and an image of a color corresponding to λ2 is generated on an upper portion of the first photodiode PD1. A second photodiode PD2 is disposed, and a third photodiode PD3 for generating an image of a color corresponding to λ3 is disposed above the second photodiode PD2.

The first transfer transistor Tx1, the first reset transistor Rx1, the first drive transistor Dx1, and the first select transistor Sx1 to form the unit pixel with the first photodiode PD1 are connected to the first photodiode. It is integrated on the same plane as PD1).

In addition, the second transfer transistor Tx2, the second reset transistor Rx2, the second drive transistor Dx2, and the second select transistor Sx2 for forming the unit pixel with the second photodiode PD2 are connected to the first photodiode. It is integrated on the same plane as the diode PD1, and has a third transfer transistor Tx3, a third reset transistor Rx3, a third drive transistor Dx3 for forming a unit pixel with the third photodiode PD3, and The third select transistor Sx3 is integrated on the same plane as the first photodiode PD1.

On the other hand, in the case of a structure having three transistors (reset transistor, drive transistor, select transistor) in one unit pixel, each of the transistors Tx1, Tx2, and Tx3 will be omitted.

That is, all transistors that handle electrons formed by receiving light from each of the photodiodes PD1 to PD3 are formed on the silicon substrate like the first grape diode PD1.

Therefore, when the silicon substrate is a P-type conductive type and all the transistors are NMOS transistors, the second photodiode PD2 and the third photodiode DP3 are respectively the source and the second transistor Tx2. The source of the three transfer transistor Tx3 is connected through a metal contact.

The reason why the three photodiodes of PD1 to PD3 are arranged vertically is that color filters are used because the light in each wavelength band coming in through the microlenses generates electron-hole pairs at different depths in the silicon. This is because electrical signals for different wavelengths (λ1 (R)> λ2 (G)> λ3 (B)) can be detected with each of the photodiodes PD1 to PD3.

In more detail, the light of blue (B) wavelength (λ3) is absorbed within about 500 mW from the surface of the silicon substrate to generate an electron-hole pair, and the light of the green (G) wavelength (λ2) is 500 mW. The light of wavelength? 1 of the red (R) series produces a electron-hole pair at a depth of 1000 mW to 2 m.

Accordingly, light having a short wavelength λ 3, such as blue B, is detected as an electrical signal at the third photodiode PD3 located on the uppermost layer from the silicon substrate, and light having a medium wavelength λ 2 such as green G is detected. Is detected by the second photodiode DP2 positioned in the middle layer, and the decorative light having a long wavelength λ1 such as red (R) is detected by the first photodiode PD1 positioned at the bottom.

At this time, the third photodiode PD3 and the second photodiode PD2 have a thickness of 400 kPa to 600 kPa, respectively, and the first photodiode PD1 has a thickness of 15000 kPa to 20000 kPa. On the other hand, the above thickness is not the thickness of the actual photodiode but the thickness including the intervening layer.

A thin insulating film is disposed between the first photodiode PD1 and the second photodiode PD2 and between the second photodiode PD2 and the third photodiode PD3 to isolate each photodiode. This insulating film should have a thickness of 50 kPa to 300 kPa and be excellent in light transmitting properties.

6 is a cross-sectional view of a CMOS image sensor showing three unit pixels according to an embodiment of the present invention.

Here, three colors, for example, RGB or YMgCy, are described as RGB as the three primary colors of light, and have a relationship of λ 1 (R)> λ 2 (G)> λ 3 (B).

Referring to FIG. 6, a silicon substrate 100 having a structure in which a high concentration P-type (P ++) region and a P-type epi layer (P-epi) thereon is stacked is provided, and the substrate 100 has a locally STI ( A device isolation film 101 having a shallow trench isolation structure is formed, and a first photodiode PD1 is formed on the silicon substrate 100 to generate a color image having the longest wavelength λ1.

A gate insulating layer 102 is formed on the substrate 100, and a gate conductive layer 103 is patterned on the gate insulating layer 102 to form gates of the first and second transfer transistors Tx1 and Tx2.

The gate insulating layer 102 not only serves as a gate insulating layer but also isolates the second photodiode PD1 and the second photodiode DP2 from each other. Therefore, the gate insulating film 102 uses an oxide-based material having high light transmittance and has a thickness of 50 kPa to 300 kPa.

The first photodiode PD1 is aligned on one side of the gate conductive film 103 and is formed by the deep ion implantation (N-type impurity region 104, hereinafter referred to as n1-region) and the spacer 105 by shallow ion implantation. P-type impurity region 107 (hereinafter referred to as P10 region) formed on the n1-region 104 so as to be aligned with the?

When four transistors are included in one unit pixel, as illustrated in the plan view of FIG. 4, a first transfer transistor Tx1 and a first reset transistor Rx1 for forming a unit pixel with the first photodiode PD1. And the first drive transistor Dx1 and the first select transistor Sx1 will be integrated on the same plane as the first photodiode PD1, and a second transfer transistor for forming a unit pixel with the second photodiode PD2. Tx2, the second reset transistor Rx2, the second drive transistor Dx2, and the second select transistor Sx2 will be integrated on the same plane as the first photodiode PD1, and the third photodiode PD3. ) And the third transfer transistor Tx3, the third reset transistor Rx3, the third drive transistor Dx3, and the third select transistor Sx3 are coplanar with the first photodiode PD1 to form a unit pixel. Will be integrated in.

On the other hand, in the case of a structure having three transistors (reset transistor, drive transistor, select transistor) in one unit pixel, each of the transistors Tx1, Tx2, and Tx3 will be omitted.

In addition, the second photodiode PD and the third photodiode PD formed on the upper portion are connected to the transistors of the corresponding unit pixels through the metal contacts 120a to 120d, respectively.

Here, reference numeral 106a denotes a source of the first transfer transistor Tx1, that is, a first floating sensing node, and reference numeral 106b denotes a source of a second transfer transistor Tx2, that is, a second floating sensing node. And reference numeral 106c denotes a drain of the second transfer transistor Tx2.

The first insulating layer 108 is formed on the entire surface where the plurality of transistors are formed. As the first insulating film 108, a silicon oxide film-based insulating film is used, and it is to prevent silicon from being formed in regions other than the second and second photodiodes PD2 and PD3 are formed during subsequent silicon formation. .

In addition, the first insulating layer 108 should be thicker than the thicknesses of the second photodiode PD and the third photodiode PD.

A P-type first silicon layer 109 having a predetermined thickness, for example, 500 mW to 2000 mW is formed in an area where the first insulating film 108 is etched and opened, and a color image of lambda 2 is generated in the first silicon layer 109. The second photodiode PD2 is formed.

The second photodiode PD2 is formed on the N-type impurity region 111 (hereinafter referred to as n2-region) formed by deep ion implantation and the first silicon layer 109 on the n2-region 111 by shallow ion implantation. It is formed of a P-type impurity region 112 (hereinafter referred to as P20 region).

The first silicon layer 109 such that the impurity region 113 for transferring the photocharge generated from the second photodiode PD2 to the source 106b of the second transfer transistor Tx2 is in contact with the n2-region 111. ) Is formed.

A second insulating film 110 is formed on the P20 region 112 of the second photodiode PD2 to isolate the first photodiode PD1 and the second photodiode PD2. The second insulating film 110 is formed of an oxide-based material having high light transmittance and has a thickness of 50 kPa to 300 kPa.

A second silicon layer 114 having a predetermined thickness, for example, 500 mW to 2000 mW, is formed on the second insulating film 110 in a region where the first insulating film 108 is etched and opened, and the second silicon layer 114 is formed. ) Is formed with a third photodiode PD3 for generating a color image of [lambda] 3.

The third photodiode PD3 is formed on the n-type impurity region (116, hereinafter referred to as n3-region) formed by deep ion implantation and the second silicon layer 114 on the n3-region 116 by shallow ion implantation. It is formed of a P-type impurity region 117 (hereinafter referred to as P30 region).

The second silicon layer 114 such that the impurity region 118 for transferring the photocharge generated from the third photodiode PD3 to the source of the third transfer transistor (not shown) is in contact with the n3-region 118. It is formed in.

A third insulating layer 115 is formed on the P30 region 117 of the third photodiode PD3 to isolate the third photodiode PD3 from an upper portion thereof. The third insulating layer 115 is formed of an oxide-based material having high light transmittance and has a thickness of 50 kPa to 300 kPa.

Considering the thickness of all other multilayers, an example of the thickness of the regions constituting each photodiode will be described.

The depths of the P10 region and the n1-region are 200 kPa to 1500 kPa, the depths of the P20 region and the n2-region are 150 kPa to 400 kPa, and the depths of the P30 region and the n3- area are 0 kPa to 500 kPa.

On the other hand, it is preferable that each P0 region has a depth of 100 kV to 500 kV vertically.

The average impurity concentration of each n-region is 1E18 atoms / cm 3 to 9E18 atoms / cm 3, and the average impurity concentration of each P 0 region is 1E18 atoms / cm 3 to 9E18 atoms / cm 3.

A fifth insulating film 119 for blocking light is formed on the first insulating film 108 and the fourth insulating film 115 to block light from entering the regions other than the first to third photodiodes PD1 to PD3. have. The fifth insulating layer 119 should have an insulating characteristic and a light blocking characteristic.

The fifth insulating layer 119 is etched to expose the upper portions of the first to third photodiodes PD1 to PD3. The fifth insulating layer 119, the first insulating layer 108, and the gate insulating layer 102 are etched to expose the source 106a of the N type (n +) of the first transfer transistor Tx1, and the exposed portion is buried. The metal contact 120a is formed, and the metal contact 120a is connected to the upper metal line 121a.

The fifth insulating layer 119 and the second silicon layer 114 are etched to expose the impurity region 113, and a metal contact 120b is formed to fill the exposed portion.

The fifth insulating layer 119, the first insulating layer 108, and the gate insulating layer 102 are etched to expose the N-type (n +) source 106b of the second transfer transistor Tx2, and the exposed portion is buried. The metal contact 120c is formed, and the metal contact 120b and the metal contact 120c are commonly connected to the upper metal line 121b.

The fifth insulating layer 119, the first insulating layer 108, and the gate insulating layer 102 are etched to expose the drain 106c of the N-type (n +) of the second transfer transistor Tx2 and is exposed. The metal contact 120d for filling the gap is formed, and the metal contact 120d is connected to the metal line 121c at the upper portion thereof.

A protective insulating film 122 and a planarizing insulating film 123 are formed on the metal lines 121a to 121c, and a microlens is formed on the planarizing insulating film 123 without a color filter array.

Hereinafter, a manufacturing process of the image sensor having the structure of FIG. 6 will be described with reference to the accompanying drawings.

5A to 5F are cross-sectional views illustrating a manufacturing process of an image sensor according to an exemplary embodiment of the present invention.

As shown in FIG. 5A, an isolation layer 101 having an STI structure is formed on a P-type substrate 100 having a structure in which a high concentration P-type (P ++) region and a P-type epitaxial layer (P-epi) are stacked. .

After the gate insulating film 102 and the gate conductive film 103 are sequentially deposited, the gate conductive film 103 is selectively etched to form gate electrodes of a plurality of transistors.

Here, only the first transfer transistor Tx and the second transfer transistor Tx2 are shown.

The gate insulating film 102 includes an oxide-based insulating film, and the gate conductive film 103 includes a structure in which a polysilicon film, a tungsten film, a tungsten silicide, or the like is singly or laminated. The gate insulating film 102 has a thickness of 50 kPa to 300 kPa.

A deep ion implantation process is performed to form the n1-region 104 for photodiodes aligned on the side of the gate electrode.

The spacer insulating film is deposited on the entire surface, and then the spacer 105 is formed on the sidewall of the gate electrode through the entire surface etching.

The first photodiode having a stacked structure of p10 region 107 / n1-region 104 is formed by performing a shallow ion implantation process to form a P10 region 107 under the surface of the substrate 100 on the n1-region 104. PD1).

The first photodiode PD1 corresponds to a light having the longest wavelength, for example, a wavelength of a red (R) or yellow (Y) color.

On the other hand, ion implantation includes the formation of a screen film, the formation of an ion implantation mask, the removal of the ion implantation mask and the screen film, and a heat treatment process for diffusion of impurities after ion implantation, but are omitted for simplicity of the drawings.

An ion implantation process for source / drain formation is performed prior to ion implantation for forming the P10 region 107 to form source / drain junction regions 106a to 106c.

Most of the transistors except the transfer transistor and the reset transistor are formed in a well and have a lightly doped drain (LDD) structure, so that an additional ion implantation process for forming the LDD structure is performed before forming the spacer 105.

As shown in FIG. 5B, the first insulating layer 108 is formed on the entire surface.

The first insulating layer 108 is used to prevent silicon from being formed in a region other than the second and third photodiodes in the silicon forming process. An insulating layer based on an oxide film such as a silicon oxide film is used.

The first insulating layer 108 is selectively etched to expose at least the first photodiode PD, and then a first silicon layer 109 is formed on the exposed portion. In this case, the first silicon layer 109 is formed by deposition through a deposition process and then etched to a predetermined thickness through an etch back process, or after forming a silicon seed layer (seed layer) Can be formed by growing through.

In the process of forming the first silicon layer 109, P-type impurities such as As or P are implanted to have a P-type conductivity, and are formed to have a thickness of 500 kPa to 2000 kPa.

As shown in FIG. 5C, a second insulating layer 110 is formed on the first silicon layer 109. The second insulating film 110 has a thickness of 50 kPa to 300 kPa.

The second insulating film 110 serves to isolate the second photodiode PD2 and the third photodiode and may serve as a screen film when forming the second photodiode (a separate screen film may be used). As the second insulating film 110, an oxide film-based insulating film such as a silicon oxide film having excellent light transmission characteristics is used.

An n2-region 111 by deep ion implantation and a P20 region 112 by shallow ion implantation are formed in the first silicon layer 109 to have a stacked structure of P20 region 112 / n2-region 111. The second photodiode PD2 is formed.

Next, an ion implantation process is performed to form the impurity region 113 in contact with the n2-region 111.

The impurity region 113 is a portion where a metal contact is made to transfer the photoelectrons generated in the second photodiode PD2 to the source 106b of the second transfer transistor Tx2.

As shown in FIG. 5D, the first silicon layer 108 is etched to form a second silicon layer 114 on the exposed second insulating layer 110. In this case, the second silicon layer 114 is formed by deposition through a deposition process and then etched to a predetermined thickness through an etch back process, or after forming a silicon seed layer (seed layer) to form the seed layer. Can be formed by growing through.

In the process of forming the second silicon layer 114, P-type impurities such as As or P are implanted to have a P-type conductivity, and are formed to have a thickness of 500 kPa to 2000 kPa.

The third insulating layer 115 is formed on the second silicon layer 114. The second insulating film 115 has a thickness of 50 kPa to 300 kPa.

In the process of forming the second silicon layer 114, the process may be performed in consideration of the thickness of the second insulating film 115, and the second insulating film 115 may be formed in a range of 50 kPa to a planarization process after deposition of the second insulating film 115. It may be made to have a thickness of 300.

The third insulating layer 115 serves to isolate the third photodiode PD3 and the upper portion thereof, and may also serve as a screen layer when forming the third photodiode (a separate screen layer may be used). As the third insulating film 115, an oxide film-based insulating film such as a silicon oxide film having excellent light transmission characteristics is used.

An n3-region 116 by deep ion implantation and a P30 region 117 by shallow ion implantation are formed in the second silicon layer 114 to have a stacked structure of P30 region 117 / n3-region 116. The third photodiode PD3 is formed.

Next, an ion implantation process is performed to form the impurity region 118 so as to contact the n3-region 117.

The impurity region 118 is a portion where a metal contact is made to transfer the photoelectrons generated in the third photodiode PD3 to a source of a third transfer transistor (not shown).

When the fifth insulating film 119 for blocking light is formed on the first insulating film 108 and the fourth insulating film 115, and selectively etched to expose the upper portions of the first to third photodiodes PD1 to PD3. Turn on.

The first insulating film 108 is for blocking light from entering the regions other than the first to third photodiodes PD1 to PD3. A first insulating film 108 is formed of a material having insulating properties and light blocking properties.

Subsequently, an open portion for the metal contact is formed through one mask process, and then the metal contacts 120a to 120d are formed and the metal lines 121a to 12c are formed thereon.

The metal contact 120a is open to expose the N-type (n +) source 106a of the first transfer transistor Tx1 by etching the fifth insulating layer 119, the first insulating layer 108, and the gate insulating layer 102. The part is embedded and connected to the upper metal line 121a.

The metal contact 120b fills an open portion in which the fifth insulating layer 119 and the second silicon layer 114 are etched to expose the impurity region 113, and the metal contact 120c is formed of the fifth insulating layer 119. The first insulating film 108 and the gate insulating film 102 are etched to fill the open portions that expose the N-type (n +) source 106b of the second transfer transistor Tx2. The metal contact 120b and the metal contact 120c are commonly connected to the metal line 121b thereon.

The metal contact 120d is open to expose the drain 106c of the N-type (n +) of the second transfer transistor Tx2 by etching the fifth insulating layer 119, the first insulating layer 108, and the gate insulating layer 102. The part is embedded and connected to the upper metal line 121c.

As shown in FIG. 5F, the protective insulating film 122 and the flattening insulating film 123 are formed on the entire surface, and then the microlenses 124 and ML are formed on the flattening insulating film 123.

According to the present invention made as described above, the photodiodes are arranged in a stacked structure in such a manner that three unit pixels are put together in a plane, and each transistor is disposed on the same plane as the lowermost photodiode, thereby increasing the degree of integration. It can be seen through the Example that can be increased 2-3 times compared to.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above can increase the density and resolution of the CMOS image sensor at the same time, thereby improving the performance and price competitiveness of the image sensor.

Claims (19)

In a CMOS image sensor for generating images for three colors having a relationship of λ1> λ2> λ3, a first photodiode for generating an image of a color corresponding to [lambda] 1; A second photodiode disposed on the first photodiode and generating an image of a color corresponding to λ2; And A third photodiode disposed on the second photodiode to generate an image having a color corresponding to λ 3; CMOS image sensor comprising a. The method of claim 1, And an insulating film disposed between the first photodiode and the second photodiode and between the second photodiode and the third photodiode so as to isolate each photodiode. The method according to claim 1 or 2, And the third photodiode and the second photodiode have a thickness of 400 mW to 600 mW, respectively, and the first photodiode has a thickness of 15000 mW to 20000 mW. The method according to claim 1 or 2, And a first transfer transistor, a first reset transistor, a first drive transistor, and a first select transistor integrated on the same plane as the first photodiode to form the first photodiode and the first unit pixel. And a second transfer transistor, a second reset transistor, a second drive transistor, and a second select transistor integrated on the same plane as the first photodiode to form the second photodiode and the second unit pixel. And a third transfer transistor, a third reset transistor, a third drive transistor, and a third select transistor integrated on the same plane as the first photodiode to form the third photodiode and the third unit pixel. CMOS image sensor. The method according to claim 1 or 2, And a first reset transistor, a first drive transistor, and a first select transistor integrated on the same plane as the first photodiode to form the first photodiode and the first unit pixel. And a second reset transistor, a second drive transistor, and a second select transistor integrated on the same plane as the first photodiode to form the second photodiode and a second unit pixel. And a third reset transistor, a third drive transistor, and a third select transistor integrated on the same plane as the first photodiode to form the third photodiode and the third unit pixel. . In a CMOS image sensor for generating images for three colors having a relationship of λ1> λ2> λ3, A first photodiode formed on the first conductive silicon substrate and configured to generate a color image of λ1; A plurality of transistors formed on the substrate; A first silicon layer of a first conductivity type formed on the first photodiode; A second photodiode formed on the first silicon layer and configured to generate a color image of λ2; A second silicon layer of a first conductivity type formed on the second photodiode; And A third photodiode formed on the second silicon layer for generating a color image of λ3 CMOS image sensor comprising a. The method of claim 6, And a second insulating film formed between the first photodiode and the first silicon layer, and a second insulating film formed between the second photodiode and the second silicon layer. The method according to claim 6 or 7, And a microlens disposed on the third photodiode without a color filter array interposed therebetween. The method of claim 8, And a light blocking insulating layer disposed between the third photodiode and the microlens to block light from being incident to a region other than the first to third photodiodes. The method according to claim 6 or 7, The first to third photodiode, And a first impurity region of an upper first conductive type and a second impurity region of a lower second conductive type, respectively. The method of claim 10, And the third photodiode and the second photodiode have a thickness of 400 mW to 600 mW, respectively, and the first photodiode has a thickness of 15000 mW to 20000 mW. The method of claim 7, wherein And the first insulating film is a gate insulating film of the plurality of transistors. The method of claim 6 or 12, The plurality of transistors, A first transfer transistor, a first reset transistor, a first drive transistor, and a first select transistor for forming the first photodiode and a first unit pixel; A second transfer transistor, a second reset transistor, a second drive transistor, and a second select transistor for forming the second photodiode and a second unit pixel; And a third transfer transistor, a third reset transistor, a third drive transistor, and a third select transistor for forming the third photodiode and the third unit pixel. The method of claim 6 or 12, The plurality of transistors, A first reset transistor, a first drive transistor, and a first select transistor for forming the first photodiode and a first unit pixel; A second reset transistor, a second drive transistor, and a second select transistor for forming the second photodiode and a second unit pixel; And a third reset transistor, a third drive transistor, and a third select transistor for forming the third photodiode and the third unit pixel. The method of claim 6, And the second photodiode and the third photodiode are connected to transistors of corresponding unit pixels through metal contacts, respectively. In the CMOS image sensor manufacturing method for generating an image for three colors having a relationship of λ1> λ2> λ3, Forming a first photodiode for generating a color image of λ1 on a first conductive silicon substrate; Forming a first insulating film on an entire surface of the first photodiode; Forming a plurality of transistors on the first insulating layer; Forming a second insulating layer on the entire surface where the plurality of transistors are formed to be thicker than the thickness of the sum of the second photodiode and the third photodiode; Selectively etching the second insulating layer to expose at least an upper portion of the first photodiode; Forming a first silicon layer of a first conductivity type in a predetermined thickness in the exposed region; Forming a second photodiode on the first silicon layer; Forming a third insulating film on the second photodiode; Forming a second silicon layer of a first conductivity type on the third insulating layer at a predetermined thickness; And Forming a third photodiode on the second silicon layer CMOS image sensor manufacturing method comprising a. The method of claim 16, After forming the third photodiode, Forming a fourth insulating film for blocking light on a front surface thereof to prevent light from being incident to a region other than the first to third photodiodes; Selectively etching the fourth insulating layer, the second silicon layer, the second insulating layer, and the first insulating layer to open a portion where the plurality of transistors, the third photodiode, and the second photodiode contact are to be made; Wow, And forming a plurality of metal lines contacted through the open portion. The method of claim 17, After the forming of the plurality of metal lines, Forming a planarization fifth insulating film on the entire surface, and forming a microlens without a color filter array on the fifth insulating film. The method of claim 16, The first to third photodiode, And a second impurity region of a first conductive type and a second impurity region of a lower conductive type, respectively.

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