KR20090084140A - Method of manufacturing high density nonvolatile memory by using low temperature high pressure annealing - Google Patents

Abstract

A method for manufacturing a nonvolatile memory using the low temperature high pressure heating is provided to decrease the electric hysteresis phenomenon by removing traps in a blocking dielectric layer. A tunneling dielectric layer(110) is formed on a semiconductor substrate with a thermal oxide layer. A nitride layer(120) is formed on the tunneling dielectric layer. A blocking dielectric layer(130) is formed on the upper part of nitride layer with the dielectric of the high dielectric constant and a gate structure is formed. The high temperature annealing is performed to the gate structure. The low temperature high pressure heating is performed after the high temperature annealing.

Description

Non-volatile memory manufacturing method using low temperature and high pressure heat treatment {METHOD OF MANUFACTURING HIGH DENSITY NONVOLATILE MEMORY BY USING LOW TEMPERATURE HIGH PRESSURE ANNEALING}

The present invention relates to a nonvolatile memory, and more particularly, to a method of manufacturing a nonvolatile memory through a two-step heat treatment using a low temperature high pressure heat treatment.

Non-volatile memory is a device that can preserve stored information even when power supply is interrupted. In particular, flash memory is a representative device of nonvolatile memory, and has high integration and excellent data retention.

The operation aspect of the flash memory includes a program operation and an erase operation. The program operation is an operation of trapping charge at an interface of a floating gate or a nitride film. On the other hand, the erase operation is an operation for transferring the trapped charge to the lower substrate. The threshold voltage of the cell transistor is changed by the program operation and the erase operation. The storage operation of the information occurs by changing the threshold voltage.

In order to achieve the operation of the above-described flash memory, the gate structure uses a floating gate of a conductor or a nitride film capable of trapping charges at an interface. Structures using nitrides are referred to as ONO (Oxide / Nitride / Oxide).

ONO (Oxide / Nitride / Oxide) type flash memory devices offer next-generation NAND flash with relatively easy scaling down, improved endurance characteristics, and even threshold voltage distribution compared to floating gate type flash memory devices. Active research is underway with memory.

However, the scaling of the tunneling and blocking dielectric films for high integration causes deterioration in recording retention and endurance. In order to solve this problem, it is proposed to replace the blocking dielectric layer with a high-k oxide instead of the conventional silicon insulating layer.

However, also in this case, defects occur at the interface or inside when the high dielectric constant insulating film for the blocking dielectric film is formed. In particular, in the case of interface defects, it is a factor that causes excessive program operation by trapping charge from the control gate (referred to as back tunneling). This causes a phenomenon in which charge remains at the interface of the blocking dielectric film even when an erase voltage is applied during the erase operation. This is called erasure saturation, which leads to degradation of memory characteristics.

The prior art has a high temperature thermal anneal (RTA) heat treatment of 800 ° C. or higher after deposition to optimize the blocking dielectric film, but there are still limitations in improving and improving the characteristics of the blocking dielectric film.

Disclosure of Invention An object of the present invention is to provide a method of manufacturing a nonvolatile memory in which the characteristics of the high dielectric constant insulating film can be secured by using a low temperature and high pressure heat treatment in a flash memory process using the high dielectric constant insulating film. It is.

A method of manufacturing a nonvolatile memory for achieving the above object of the present invention includes the steps of forming a tunneling dielectric film with a thermal oxide film on a semiconductor substrate, forming a nitride film on the tunneling dielectric film, a dielectric having a high dielectric constant on the nitride film Forming a gate blocking dielectric layer to form a gate structure, performing a high temperature heat treatment on the gate structure, and performing a low temperature and high pressure heat treatment after the high temperature heat treatment.

According to the present invention, the nonvolatile memory device manufactured by the present invention reduces the electric hysteresis phenomenon by eliminating the traps in the blocking dielectric film.

In addition, the blocking efficiency is improved in the erase operation condition of high voltage, thereby lowering the erase saturation level.

In addition, as a result of measuring charge integrity, the charge leakage rate is significantly reduced due to the trap reduction of the blocking dielectric layer.

According to the above characteristics, the program, read and erase characteristics of the nonvolatile memory are improved.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

1 to 8 are cross-sectional views illustrating a method of forming a flash memory device including an insulating film according to an embodiment of the present invention.

1 to 2 are cross-sectional views illustrating a method of forming a tunneling dielectric layer 110 in a method of forming a flash memory device including an insulating layer according to an embodiment of the present invention.

1 is a cross-sectional view of a tunneling dielectric layer 110 formed on the semiconductor substrate 100 as a single layer of a thermal oxide layer 111.

Referring to FIG. 1, a silicon thermal oxide film 111 is formed on the semiconductor substrate 100.

FIG. 2 is a cross-sectional view of a tunneling dielectric layer 110 formed on the semiconductor substrate 100 in a plurality of layers of a high dielectric constant insulating film 112 formed of a silicon thermal oxide film 111 and a dielectric having a high dielectric constant.

Referring to FIG. 2, the silicon thermal oxide film 111 is formed on the semiconductor substrate 100, and the silicon thermal oxide film 111 has a thickness greater than the final formation thickness at the time of initial formation in view of the subsequent high dielectric constant insulating film 112. To 50% thinner. The high-k dielectric layer 112 is formed on the formed silicon thermal oxide layer 111 to form the multilayer tunneling dielectric layer 110. The high dielectric constant insulating film 112 preferably uses a high-k dielectric having a high dielectric constant. Here, dielectric having a high dielectric constant is Al ₂ O ₃ , HfO ₂ , ZrO ₂ , Ta ₂ O ₅ , TiO _2, and It includes at least one of YO ₂ , or Hf Silicate, Zr Silicate, Y Silicate, or lanthanum (Ln) metal Silicate.

Subsequently, high temperature heat treatment is performed on the semiconductor substrate 100 on which the high dielectric constant insulating film 112 is formed. That is, annealing is performed at least about 1 minute at about 800 ° C. or more to cure defects in the high dielectric constant insulating film 112. However, in the case of curing in such a high temperature state, there is a limit to the complete curing of the high dielectric constant insulating film 112 having oxygen. In other words, mismatch and oxygen vacancies due to lack of oxygen concentration are difficult to heal.

3 illustrates an example of performing low temperature high pressure heat treatment after high temperature heat treatment is performed on the semiconductor substrate 100 on which the tunneling dielectric layer 110 is formed.

Referring to FIG. 3, after the high temperature heat treatment is performed on the semiconductor substrate 100 on which the tunneling dielectric layer 110 is formed, low temperature high pressure heat treatment is performed. The low temperature high pressure heat treatment is carried out in a high pressure atmosphere at a temperature of about 200 ° C to 600 ° C. At low temperature and high pressure heat treatment, pure florin or a gas containing florin is supplied to the inert gas at a concentration of 0.01-10%, and preferably 5 to 60 minutes at 2-100 atm.

In FIG. 3, when the tunneling dielectric layer 110 is formed of only a single layer of the silicon thermal oxide layer 111, the two-step heat treatment may not be performed.

4 is a cross-sectional view illustrating a tunneling dielectric film 110 and a nitride film 120 formed on a semiconductor substrate 100.

Referring to FIG. 4, the nitride film 120 is formed on the tunneling dielectric layer 110 formed on the semiconductor substrate 100. The nitride film 120 is preferably composed of a silicon nitride film (Si ₃ N ₄ ).

5 to 6 are cross-sectional views illustrating a method of forming a blocking dielectric layer 130 in a method of forming a flash memory device according to an embodiment of the present invention.

5 is a cross-sectional view illustrating a blocking dielectric layer 130 formed of a single layer of a first blocking dielectric layer 131 formed of a high dielectric constant after the tunneling dielectric layer 110 and the nitride layer 120 are formed on the semiconductor substrate 100. .

Referring to FIG. 5, the first blocking dielectric layer 131 is formed on the nitride layer 120 by a single layer blocking dielectric layer formation method. The first blocking dielectric layer 131 preferably uses a high-k dielectric having a high dielectric constant.

Next, a high temperature heat treatment is performed on the semiconductor substrate 100 on which the first blocking dielectric film 131 is formed. That is, annealing is performed at least about 1 minute at about 800 ° C. or more to cure defects in the first blocking dielectric layer 131. However, there is a limit to the complete curing of the first blocking dielectric layer 131 having oxygen in such a high temperature state. In other words, mismatch and oxygen vacancies due to lack of oxygen concentration are difficult to heal. In addition, there is a certain limit to the healing of predefect or defect formed at the interface between the nitride film 120 and the first blocking dielectric film 131.

6 illustrates an example in which the tunneling dielectric film 110, the nitride film 120, and the blocking dielectric film 130 are formed in a single layer on the semiconductor substrate 100, and then the low temperature and high pressure heat treatment is performed after the high temperature heat treatment is performed.

Referring to FIG. 6, after the blocking dielectric layer 130 is formed as a single layer, a low temperature high pressure heat treatment is performed on the semiconductor substrate 100. The low temperature high pressure heat treatment is carried out in a high pressure atmosphere at a temperature of about 200 ° C to 600 ° C. At low temperature and high pressure heat treatment, pure florin or a gas containing florin is supplied to the inert gas at a concentration of 0.01-10%, and preferably 5 to 60 minutes at 2-100 atm.

FIG. 7 shows a dielectric constant having a high dielectric constant different from that of the first blocking dielectric layer 131 in which the blocking dielectric layer 130 is formed of a high dielectric constant after the tunneling dielectric layer 110 and the nitride layer 120 are formed on the semiconductor substrate 100. It is sectional drawing of the state formed in the multilayer of the 2nd blocking dielectric film 132 formed by the.

Referring to FIG. 7, the first blocking dielectric layer 131 is formed on the nitride layer 120 by using the multilayer blocking dielectric layer 130. The first blocking dielectric layer 131 is formed to be 1-50% thinner than the final formation thickness in consideration of the amount of increase in the subsequent formation of the second blocking dielectric layer 132.

Subsequently, a second blocking dielectric layer 132 is formed on the first blocking dielectric layer 131 to form a multilayer blocking dielectric layer 130. The second blocking dielectric layer 132 preferably uses a high-k dielectric having a dielectric constant different from that of the first blocking dielectric layer 131.

Next, a high temperature heat treatment is performed on the semiconductor substrate 100 on which the multilayer blocking dielectric layer 130 is formed. That is, annealing is performed at least about 1 minute at about 800 ° C. or more to cure defects in the blocking dielectric layer 130. However, there is a limit to the complete curing of the multilayer blocking dielectric layer 130 having oxygen in such a high temperature state. In other words, mismatch and oxygen vacancies due to lack of oxygen concentration are difficult to heal. In addition, predefects or faces generated at the interface between the nitride film 120 and the first blocking dielectric film 131 and predefects or faces generated at the interface between the first blocking dielectric film 131 and the second blocking dielectric film 132. There are certain limits to the healing of defects.

8 illustrates an example in which a tunneling dielectric layer 110, a nitride layer 120, and a blocking dielectric layer 130 are formed in a plurality of layers on a semiconductor substrate 100, and then a low temperature and high pressure heat treatment is performed after the high temperature heat treatment is performed.

Referring to Figure 8, the low temperature high pressure heat treatment is carried out in a high pressure atmosphere, at a temperature of about 200 ° C to 600 ° C. At low temperature and high pressure heat treatment, pure florin or a gas containing florin is supplied to the inert gas at a concentration of 0.01-10%, and preferably 5 to 60 minutes at 2-100 atm.

9 is a graph measuring hysteresis of a flash memory formed according to a preferred embodiment of the present invention.

Referring to FIG. 9, the Y axis represents the gate capacitance and the X axis represents the tunneling dielectric layer 110 of the silicon oxide layer SiO ₂ and the nitride layer 120 of the silicon nitride layer Si ₃ N ₄ formed on the semiconductor substrate 100. The voltage applied to the insulating layer composed of the blocking dielectric film 130 of the aluminum oxide film Al ₂ O ₃ is shown.

In addition, the order of voltage application is applied clockwise from 20V to -20V and immediately counterclockwise from -20V to 20V. When applied clockwise, electrons are injected from the substrate through the tunneling dielectric layer 110.

Therefore, the capacitance-voltage graph is shifted to the right by the injected electrons. In addition, the capacitance-voltage graph moved to the right is moved to the left again when holes are injected from the substrate or the injected electrons pass through the tunneling dielectric layer 110 and are tunneled to the substrate during counterclockwise application.

The width of the two graphs is called hysteresis. When the low temperature and high pressure heat treatment is performed, defects or oxygen vacancies in the blocking dielectric layer 130 are removed, and when charges are applied from the substrate to the blocking dielectric layer 130 when charges are injected through the tunneling dielectric layer 110 when the clockwise voltage is applied. To prevent it.

Therefore, it can be seen that the amount of right shift of the capacitance-voltage graph is smaller than that of the case where the low temperature high pressure heat treatment is not performed. In addition, when the low temperature and high pressure heat treatment is performed when the counterclockwise voltage is applied, the capacitance-voltage graph can be moved more to the left by preventing charges from being injected from the gate.

10 is a graph illustrating an erase operation speed of a flash memory according to an exemplary embodiment of the present invention.

Referring to FIG. 10, the Y axis represents a variation in the flat band voltage (V _FB ), and the X axis represents the tunneling dielectric layer 110 and the silicon nitride layer Si of the silicon oxide layer SiO ₂ formed on the semiconductor substrate 100. ₃ N ₄₎ shows the voltage applied to the insulating layer consisting of the blocking dielectric layer 130 of the nitride film 120 and the aluminum oxide film (Al ₂ O _3).

The flattening voltage refers to a voltage that must be applied to flatten the energy band shifted by the electric charges stored in the elements constituting the flash device. This is closely related to the amount of electrons present in the nitride film 120 storing charge. In addition, as the erase voltage increases, the variation of the planar voltage increases, because electrons in the nitride layer 120 are erased through the tunneling dielectric layer 110. However, when a high negative voltage is applied to the gate, electrons in the nitride film 120 may pass through the tunneling dielectric film 110, but electrons pass through the blocking dielectric film 130 to the nitride film 120 in the gate layer. The incoming electrons do not completely perform the erase operation.

When the low-temperature, high-pressure heat treatment is performed, the amount of electrons flowing into the blocking dielectric layer 130 is reduced, so that the erase operation can be performed smoothly.

FIG. 11 is a graph illustrating results of analyzing write integrity characteristics of a flash memory according to an exemplary embodiment of the present invention. FIG.

Referring to FIG. 11, the Y axis represents the charge loss rate indicating the amount of electrons leaving the nitride film 120 through the flat voltage. The x-axis represents a specific temperature to determine how much of the electrons stored in the flash memory are lost at that particular temperature.

Typically, when heat is applied, electrons in the nitride film 120 gain energy and move to the conduction band. At this time, the electrons are lost in the tunneling dielectric layer 110 and the blocking dielectric layer 130. When the low temperature high pressure heat treatment is performed, it can be seen that the charge loss rate according to each temperature is reduced by preventing the loss of charge through the blocking dielectric layer 130.

Preferred embodiments of the process to which the present invention is applied are as follows. The silicon oxide film thickness (<5 nm) is appropriately adjusted with the tunneling dielectric film 110 on the silicon semiconductor substrate 100. A silicon nitride film is deposited on the tunneling dielectric film 110 with the nitride film 120. A high dielectric constant insulating film is deposited on the nitride film 120 as the blocking dielectric film 130. After the tunneling dielectric film 110 / nitride film 120 / blocking dielectric film 130 structure is formed on the silicon semiconductor substrate 100, a high temperature heat treatment is performed at 800 ° C. or higher for 1 minute. In addition, a low-pressure high-temperature heat treatment is performed for 20 minutes in a high-pressure atmosphere of 400 ℃ using a gas containing 0.04% of florin in 10 atm of argon.

1 is a cross-sectional view of a tunneling dielectric film formed on a semiconductor substrate as a single layer of a thermal oxide film.

FIG. 2 is a cross-sectional view of a tunneling dielectric film formed on a semiconductor substrate in a plurality of layers of an insulating film formed of a thermal oxide film and a dielectric having a high dielectric constant.

3 is an exemplary diagram of low temperature and high pressure heat treatment after high temperature heat treatment is performed on a semiconductor substrate on which a tunneling dielectric film is formed.

4 is a cross-sectional view of a tunneling dielectric film and a nitride film formed on a semiconductor substrate.

5 is a cross-sectional view of a state in which a blocking dielectric film is formed of a single layer of an insulating film formed of a dielectric having a high dielectric constant after a tunneling dielectric film and a nitride film are formed over a semiconductor substrate.

FIG. 6 is an exemplary view illustrating a low temperature and high pressure heat treatment after a tunneling dielectric film, a nitride film, and a blocking dielectric film are formed in a single layer on a semiconductor substrate and a high temperature heat treatment is performed.

7 is a cross-sectional view of a state in which a blocking dielectric film is formed of a multilayer of an insulating film formed of a high dielectric constant with a dielectric constant different from that of a blocking dielectric film after a tunneling dielectric film and a nitride film are formed on a semiconductor substrate.

8 illustrates an example of a low temperature and high pressure heat treatment after a tunneling dielectric film, a nitride film, and a blocking dielectric film are formed in a plurality of layers on a semiconductor substrate and a high temperature heat treatment is performed.

9 is a graph measuring hysteresis of a flash memory formed according to a preferred embodiment of the present invention.

10 is a graph illustrating an erase operation speed of a flash memory according to an exemplary embodiment of the present invention.

FIG. 11 is a graph illustrating results of analyzing write integrity characteristics of a flash memory according to an exemplary embodiment of the present invention. FIG.

Claims (5)

Forming a tunneling dielectric film on the semiconductor substrate with a thermal oxide film; Forming a nitride film over the tunneling dielectric film; And Forming a gate structure by forming a blocking dielectric layer on the nitride layer using a dielectric having a high dielectric constant; Performing a high temperature heat treatment on the gate structure; And After the high temperature heat treatment, performing a low temperature high pressure heat treatment. The method of claim 1, The tunneling dielectric film, Further comprising a high dielectric constant insulating film formed of a high dielectric constant on the thermal oxide film, After forming the tunneling dielectric layer, Performing a high temperature heat treatment; And And after the high temperature heat treatment, performing low temperature and high pressure heat treatment. The method of claim 1, The blocking dielectric layer, And a second blocking dielectric layer having a dielectric having a high dielectric constant different from that of the first blocking dielectric layer. The method according to any one of claims 1 to 3, Dielectric with high dielectric constant Al ₂ O ₃ , HfO ₂ , ZrO ₂ , Ta ₂ O ₅ , TiO ₂ and YO ₂ material containing at least one, or Hf Silicate, Zr Silicate, Y Silicate or lanthanum (Ln) metal Silicate A nonvolatile memory manufacturing method. The method according to claim 1 or 2, The low temperature high pressure heat treatment In an inert gas atmosphere such as nitrogen or argon, Pure florin or gas containing florin is supplied at a concentration of 0.01 to 10%, The temperature is at a temperature of 200 to 600 ° C. Atmospheric pressure is from 2 to 100 atm, The time is performed for 5 to 60 minutes, the method of manufacturing a nonvolatile memory.

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