KR20090081637A - Semiconductor device and method for forming bit line of semiconductor device - Google Patents

Abstract

A semiconductor device and a method for forming a bit line are provided to minimize interference between bit lines by securing capacitance of a low bit line through void-fill. A semiconductor device includes a plurality of bit lines, an interlayer insulating layer, a void(160), and a barrier layer(130). The plurality of bit lines are arranged on the semiconductor substrate with a lower structure. The interlayer insulating layer buries and insulates the space between the bit lines. A void is formed in the interlayer insulating layer between the bit lines. A barrier layer surrounds the side and the lower part of the bit line.

Description

Semiconductor device and method for forming bit line of semiconductor device

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a bit line of a semiconductor device.

 In the 60 nm or less flash device, a device is manufactured by forming a bit line and a metal line using a damascene process and then forming an intermetal dielectric (IMD). At this time, as the interval between the metal lines is narrowed, the interference phenomenon between the metal lines increases, causing signal distortion or difference in operating speed between each bit line, thereby causing distribution of the input signal. Such scattering can cause abnormal signals or interference between two signals in a multi-level cell (MLC), making the cell unable to operate correctly. Therefore, in order to minimize such interference between metal lines, attempts are being made to apply a low-k material as an intermetallic insulating film or to fill between metal lines by using voids. Low-k materials can effectively reduce capacitor and propagation delays in interconnected layers, compared to traditional silicon-based insulator materials, increasing overall chip performance and reducing power consumption. However, when the low dielectric material is applied, it is difficult to form an insulating film that maintains sufficient strength, and the adhesive strength between the insulating films or the barrier metal film is too low to be easily detached.

Filling between metal lines using voids is a method of applying a reactive ion etching (RIE) process, which is uniform depending on the state of the etched metal lines because the void gap fill process is applied after patterning the metal lines. One void gap fill is difficult.

In addition, since the reaction ion etching (RIE) process etches the metal line, it is difficult to realize uniform line resistance, and the higher the metal line, the more difficult it is to form a constant metal line due to the influence of metal particles. The reactive ion etching (RIE) process is etched along the metal particles so that they exist in the shape of particles on top of the metal and each line has a different sheet resistance (Rs) due to the step difference caused by the metal particles. And when the copper (Cu) metal is applied, the etching process itself is almost impossible due to the material properties. In the case of the damascene process, there is a problem in that there is no low dielectric material having sufficient mechanical strength to form a trench.

Therefore, in order to secure sufficient sheet resistance (RS) for driving a device in a flash process of 60 nm or less, the area of the metal line needs to be increased, and the bit line needs to be adjusted upward to increase the area. In order to do this, new materials with less interference with humans should be selected to increase metal lines and improve semiconductor processes.

The present invention provides a semiconductor device comprising: a plurality of bit lines arranged on a semiconductor substrate on which a lower structure is formed; An interlayer insulating film that fills and insulates the bit lines; And a void formed in the interlayer insulating film between the bit lines.

The semiconductor device may further include a barrier layer surrounding side and bottom portions of the bit line.

The present invention includes forming a sacrificial film on the first insulating film formed on the semiconductor substrate; Patterning the sacrificial layer and the first insulating layer to form openings in regions where bit lines are to be formed; Filling the openings with a conductive film for bit lines; Removing the sacrificial layer; And forming a second insulating layer to fill the gap between the conductive layers, wherein a void is formed between the conductive layers.

The sacrificial film is an amorphous carbon film or SOD film, and may be formed to a thickness of 500 kV to 1500 kV.

In the forming of the opening in the region where the bit line is to be formed, a two-step process may be performed using the insulating layer as an etch stop layer.

Slop of the opening may be formed to 80 to 90 degrees.

The method may further include forming a barrier layer on the inner wall of the trench before filling the opening with the conductive layer.

The conductive film is formed of tungsten (W) or aluminum (Al) and the barrier layer is Ti, Ti / TiN, Ti / TiN / Ti, Ta / TaN, Ta / TaN / Ta, Ti / TiSiN, Ti / TiSiN / Ti It may be formed of any one of the group consisting of.

The conductive layer may be formed of copper, and the barrier layer may be formed of any one group consisting of Ta / TaN, Ta / TaN / Ta, and Ru.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

1 to 3 are diagrams for explaining a method of forming a bit line of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, a first insulating film 100, a second insulating film 110, and a sacrificial film 120 are sequentially formed on a semiconductor substrate (not shown) where a predetermined process is completed. Next, after selectively patterning the sacrificial layer 120, the second insulating layer 110 is etched to a predetermined depth using the sacrificial layer as an etching mask to form an opening in a region where the bit line is to be formed.

The second insulating layer 110 is formed of a silicon-based oxide film. Silicon-based oxide film is, for example, TEOS, HDP, USG, Si ₃ N ₄ Or SiON, which can be formed by any one of them, and has a thickness of 1000 kPa to 2500 kPa. In addition, the second insulating layer 110 serves as an etch stop layer so as not to be over-etched when patterning the sacrificial layer 120, thereby securing a bit line of a certain height and minimizing interference between bit lines. have.

The sacrificial layer 120 may be formed of an amorphous carbon film or an SOD film having an excellent etching selectivity with respect to the second insulating film 110. An amorphous carbon film is formed using a plasma chemical vapor deposition (PECVD) method using a propylene source. At this time, the process temperature is performed at a low temperature of 400 ° C. or lower or a high temperature of 400 ° C. to 500 ° C., and has a thickness of about 500 kV to 1500 kPa. Since the amorphous carbon film is completely removed through ashing like the photoresist film, it does not affect the characteristics of the bit line. In addition, even if a carbon component is present in the device, since it exists as an insulator, the device does not cause deterioration of a device such as a bridge of a bit line.

In the patterning process for forming the openings, the process is performed in two steps and etched to a depth of 1500 kPa to 2000 kPa in order to keep the depth of the opening constant. And the slope of the opening can be adjusted to favor the peeling process of the metal layer. Since the trench slope affects the shape and size of the void in the subsequent void fill process, the etching process should be performed by appropriately adjusting the slope, and the appropriate slope is about 80 ° to 90 °.

Referring to FIG. 2, after the barrier layer 130 and the bit line conductive film 140 are formed on the resultant, the planarization process is performed on the bit line conductive film, for example, chemical mechanical polishing (CMP). ) To form a bit line embedded in the trench.

The barrier layer 130 is formed to prevent diffusion, to improve the contact force of the metal film, and to form ohmic contacts between the contact materials, and the barrier layer 130 is formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD). In consideration of the step coverage, the final thickness may be 80 Å or less in the side direction.

When tungsten (W) or aluminum (Al) is used as the conductive film 140 for the bit line, seeding of a metal line or gap-filling of a narrow region may be performed by chemical vapor deposition (CVD). The large area can be performed by physical vapor deposition (PVD) method, which has the effect of lowering the sheet resistance (Rs) of the bit line. Therefore, the opening may be filled by forming a seeding with a thickness of 50 kPa to 300 kPa by chemical vapor deposition and then forming a thickness of 1000 kPa to 5000 kPa by physical vapor deposition. In this case, the barrier layer 130 may be formed of any one group consisting of Ti, Ti / TiN, Ti / TiN / Ti, Ta / TaN, Ta / TaN / Ta, Ti / TiSiN, and Ti / TiSiN / Ti.

When copper (Cu) is used as the conductive film for the bit line, it may be formed by an ion plating method, and in this case, the barrier layer 130 may be formed from a group consisting of Ta / TaN, Ta / TaN / Ta, and Ru. It can be formed by either.

Referring to Figure 3, oxygen plasma (O ₂ plasma) process or a sulfuric acid solution (H ₂ SO ₄₎ by carrying out a wet etching process after removing the sacrificial film 120, a chemical vapor deposition method intermetallic insulating film (150 Using ) Is formed to perform a gap-fill process to fill the conductive film 140 for each bit line. Then, a void 160 having a predetermined size is formed between the bit lines conductive layer 140 in the gap fill process. In this case, when the intermetallic insulating layer 150 is formed by chemical vapor deposition (CVD), an overhang occurs due to a difference in deposition rates between the top part and the side part, thereby causing void fill. ) Process is more advantageous. And the shape of the voids formed is determined by the slop during the trench formation, it is preferable to maintain the deposition rate as high as possible so that the overhang occurs in the oxide film by chemical vapor deposition to the maximum.

The intermetallic insulating film 150 is formed to a thickness of 2000 kPa to 5000 kPa using a chemical vapor deposition method. In this case, a low dielectric material such as TEOS, USG, or SiON series, which can lower the dielectric constant, may be used.

As such, by applying a void fill process to separate the conductive layer 140 for the bit line, the capacitance of the bit line can be lowered and the resistance of the bit line can be reduced.

Void 160 plays an important role in lowering the capacitance. The reason is that the capacitance between the bit line and the bit line is proportional and inversely proportional to the dielectric constant of the insulating material between the bit line and the contact area between the bit line and the insulating film. Therefore, even if the material gap-filling between the bit lines is larger than the dielectric constant 1 of the void even if the material is a low dielectric constant (2 to 4.5), the formation of the void 160 is a method that can further lower the capacitance of the bit line . However, if the void is not constant, it is important to form the void 160 having a constant size because the capacitance value between each bit line is different and the interference effect between the bit lines is different from each other.

When the bit line is formed using the damascene process, the bit line capacitance tends to increase as compared with reactive ion etching (RIE). As a method of solving this problem, a stable metal line may be implemented in the line bridge by performing an oxygen plasma treatment or a wet process using a sacrificial film. In particular, it is more useful when the reaction ion etching process such as aluminum (Al) or copper (Cu) is difficult to apply at 60 nm or less.

The present invention provides a fill process between metal lines by forming a void using a damascene process using an etching target film and a chemical vapor deposition (CVD) method in forming a bit line of a flash memory. By doing so, it is possible to ensure a bit line of a constant height, thereby improving the uniformity of the resistance. The void fill can ensure low bit line capacitance to minimize interference between bit lines and increase the area of the bit line to lower the resistance.

In addition, a material for filling the opening may use a dielectric material having a low dielectric constant to lower the capacitance of the bit line to minimize interference between the bit lines. In addition, by adjusting the slop during trench formation, the size of the void formed when performing the gap fill process may be adjusted to secure a desired bit line capacitance.

1 to 3 are diagrams for explaining an electrode forming method of a semiconductor device according to the present invention.

Claims (9)

A plurality of bit lines arranged on the semiconductor substrate on which the substructure is formed; An interlayer insulating film that fills and insulates the bit lines; And And a void formed in the interlayer insulating film between the bit lines. The semiconductor device further comprises a barrier layer surrounding the side and bottom of the bit line. Forming a sacrificial film on the first insulating film formed on the semiconductor substrate; Patterning the sacrificial layer and the first insulating layer to form openings in regions where bit lines are to be formed; Filling the openings with a conductive film for bit lines; Removing the sacrificial layer; And Forming a second insulating film so as to fill the conductive film, wherein a void is formed between the conductive film; The method of claim 3, The sacrificial film is an amorphous carbon film or SOD film, the bit line forming method of a semiconductor device to form a thickness of 500 ~ 1500Å. The method of claim 3, Forming an opening in a region where the bit line is to be formed, And forming an etching stop film using the insulating layer as an etch stop layer. The method of claim 3, And a slop of the opening is 80 ° to 90 °. The method of claim 3, Before the step of filling the opening with a conductive film, And forming a barrier layer on the inner wall of the opening. The method of claim 7, wherein The conductive film is formed of tungsten (W) or aluminum (Al), and the barrier layer is Ti, Ti / TiN, Ti / TiN / Ti, Ta / TaN, Ta / TaN / Ta, Ti / TiSiN, Ti / TiSiN / A method of forming a bit line in a semiconductor device, which is formed of any one group consisting of Ti. The method of claim 7, wherein And wherein the conductive layer is formed of copper and the barrier layer is formed of any one of Ta / TaN, Ta / TaN / Ta, and Ru.

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