KR20090079789A - Architecture of high integrated semiconductor memory apparatus - Google Patents

Abstract

An inner structure of a high integrated semiconductor memory device is provided to reduce the number of transmission lines by sharing the transmission lines between adjacent column control circuit regions. A row control circuit region(310B) and a first column control circuit region(310C) correspond to a first memory bank(310A). The second row control circuit region(330B) corresponds to a second memory bank(330A). The second row control circuit region is adjacent to the first row control circuit region. The second control circuit region(330C) corresponds to the third memory bank. The second column control region is adjacent to the first column control circuit region. The first and second column control circuit regions share the first transmission line. The first and second row control circuit regions share the second transmission line. The first and second transmission lines transmit address information, test information, or power supply voltage.

Description

Internal Structure of Highly Integrated Semiconductor Memory Device {ARCHITECTURE OF HIGH INTEGRATED SEMICONDUCTOR MEMORY APPARATUS}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor design technology, and more particularly, to a high density semiconductor memory device having a plurality of memory banks for storing data and various internal circuits for performing data input / output operations. It's about structure.

In general, a semiconductor memory device including a DDR SDRAM (Double Data Rate Synchronous DRAM) stores data or outputs data according to a command required by a data processing device, for example, a central processing unit (CPU). If the CPU requests a write operation, the CPU stores the data in a memory cell corresponding to address information input from the CPU, and if the CPU requests a read operation, The data stored in the memory cell corresponding to the address information input from the CPU) is output.

Meanwhile, a semiconductor memory device includes tens of millions of memory cells, and such a set of memory cells is generally called a memory bank. The number of memory banks included in the semiconductor memory device may vary depending on the design. However, in recent years, the number of memory banks is increasing to increase the capacity of the semiconductor memory device.

1 is a diagram illustrating a general read operation and a write operation of a conventional semiconductor memory device. For convenience of description, one memory cell included in the memory bank is illustrated, and reference numeral '110' is denoted.

A simple read operation of the semiconductor memory device will be described with reference to FIG. 1.

First, when a selected word line WL is activated by decoding a row address input according to an external command signal, a cell transistor T1 of the memory cell 110 is turned on. on), and the data stored in the cell capacitor C1 is charge-shared to the precharged positive / negative bit lines BL and / BL. The positive bit line BL and the sub bit line / BL have a small potential difference through the charge sharing operation.

Subsequently, the bit line sense amplifier 120 senses and amplifies a small potential of the positive bit line BL and the corresponding sub bit line / BL. In other words, when the potential of the positive bit line BL is higher than the potential of the negative bit line / BL, the positive bit line BL is amplified by the pull-up power supply voltage RTO and the negative bit line BL is pull-down power supply voltage. Amplified by (SB). On the contrary, when the potential of the positive bit line BL is lower than the potential of the negative bit line / BL, the positive bit line BL is amplified by the pull-down power supply voltage SB and the negative bit line / BL is the pull-up power supply voltage. Amplified by (RTO).

Meanwhile, when the selected column select signal YI is decoded by decoding a column address input according to an external command signal, the column selector 130 is activated to operate with the positive and negative bit lines BL and / BL. Positive and negative segment input and output lines (SIO, / SIO) are connected. That is, the data amplified on the positive bit line BL is transferred to the positive segment input / output line SIO, and the data amplified on the negative bit line / BL is transferred to the sub segment input / output line / SIO.

Subsequently, when the input / output switching unit 140 is activated in response to the input / output control signal CTR_IO, the positive / negative segment input / output lines SIO and / SIO and the positive / negative local input / output lines LIO and / LIO are connected. That is, the data transmitted to the positive segment input / output line SIO is transmitted to the positive local input / output line LIO, and the data transmitted to the secondary segment input / output line / SIO is transmitted to the secondary local input / output line / LIO. The read driving unit 150 drives the global input / output line GIO according to data transmitted through the positive / negative local I / O lines LIO and / LIO.

As a result, the data stored in the memory cell 110 is transferred from the positive / negative bit lines BL and / BL to the positive and negative segment input / output lines SIO and SIO in response to the column selection signal YI. The data transferred to the sub-segment I / O lines SIO and / SIO are transferred to the positive and negative local I / O lines LIO and / LIO in response to the I / O control signal CTR_IO, and the positive and negative local I / O lines LIO and /. The data transferred to the LIO is transferred to the global input / output line GIO by the read driver 150. The data thus delivered is finally output to the outside through a corresponding input / output pad (not shown).

On the other hand, the data applied from the outside during the write operation is transferred in the opposite direction to the read operation. That is, data applied through the input / output pad is positive / negative local I / O lines (LIO, / LIO) from the global input / output line (GIO) through the write driving unit 160, and positive / negative local I / O lines (LIO, / LIO). ) From the positive / negative segment input / output lines (SIO, / SIO) to the positive / negative segment input / output lines (SIO, / SIO) to the positive / negative bit lines (BL, / BL). The data thus transferred is finally stored in the memory cell 110.

2 is a block diagram illustrating a memory bank structure of a conventional semiconductor memory device. For convenience of description, a semiconductor memory device having eight memory banks will be described as an example.

Referring to FIG. 2, a semiconductor memory device includes first to eighth memory banks, and includes a row control circuit region and a column control circuit region corresponding to each of the plurality of memory banks. Hereinafter, the first memory bank 210, the first row control circuit region 230, and the first column control circuit region 250 will be described as representative.

As described above, the first memory bank 210 includes a plurality of memory cells, and the first row control circuit region 230 and the first column control circuit region 250 correspond to the first memory bank 210. do. Here, circuits for controlling row access of the first memory bank 210 are disposed in the first row control circuit region 230 and a first memory in the first column control circuit region 250. Circuits for controlling column access of the bank 210 are arranged.

Although not shown in detail, the first row control circuit region 230 includes a row decoding unit for decoding word information input from the CPU and selecting a word line WL (see FIG. 1), and a bit line. Replace the power supply voltage control unit for controlling the pull-up power supply voltage (RTO) and the pull-down power supply voltage (SB) supplied to the sense amplifier unit 120, and the word line connected to the defective memory cell with another word line connected to the normal memory cell. A low redundancy control unit is disposed. Here, the pull-up power supply voltage RTO and the pull-down power supply voltage SB are voltages generated based on the external power supply voltage and the ground power supply voltage.

Subsequently, although not shown in detail, the first column control circuit area 250 decodes the address information input from the CPU to select the column selection signal YI (see FIG. 1) corresponding to the memory cell. A column decoding unit, a read driving unit 150 for outputting data read from a corresponding memory bank in response to a read command, and a write driving unit for transferring externally applied data to the corresponding memory bank in response to a write command And a column redundancy control unit for replacing the column select signal YI connected to the defective memory cell with another column select signal corresponding to a normal memory cell. Here, the column redundancy operation may be performed by replacing a column address corresponding to a defective memory cell with a column address corresponding to a normal memory cell.

 Meanwhile, the first memory bank, the second memory bank, the fifth memory bank, and the sixth memory bank are arranged in a row direction, and the third memory bank, the fourth memory bank, and the seventh memory bank are disposed. The eighth memory banks are also arranged in the row direction, and the peripheral circuit region 270 is disposed between the memory banks arranged in the row direction.

In the peripheral circuit area 270, a plurality of pads (not shown) for receiving power voltage, data information, address information, external command signals, clock signals, and the like, which are input from the outside, are disposed and input through a plurality of pads. A plurality of transmission lines are arranged to transmit various signals. The semiconductor memory device performs various operations based on various signals received through a plurality of pads.

On the other hand, a plurality of transmission lines are arranged in each of the row control circuit region and the column control circuit region. The transmission line includes a power supply line for applying power to circuits included in each of the row control circuit area and the column control circuit area, an address line for transmitting address information, and a test for transmitting signals related to various test operations. Line and the like. In other words, a power line, an address line, a test line, and the like are disposed in each of the first to eighth row control circuit regions, and each of the first to eighth column control circuit regions is also a power line, an address line, and a test line. Etc. are arranged.

Meanwhile, as semiconductor memory devices become more integrated, efforts to reduce chip area of semiconductor memory devices have been continuously performed to improve productivity. In fact, the smaller the chip area, the greater the number of chips that can be produced through one wafer, which can lead to lower manufacturing costs through improved productivity. However, in the memory bank structure of the conventional semiconductor memory device, since the power line, the address line, and the test line corresponding to each row control circuit region and column control circuit region must be disposed, the chip area for these lines is reduced. There is no room to reduce it.

In recent years, as semiconductor memory devices become more and more large, the number of memory banks is increasing, and the row control circuit area and column control circuit area corresponding to each memory bank are also increasing. An increase in the row control circuit area and the column control circuit area means that each of the power lines, the address lines, and the test lines increases, which is a burden to increase the chip area.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems, and each of the row control circuit regions corresponding to neighboring memory banks is disposed adjacent to each other, and each of the column control circuit regions corresponding to the neighboring memory banks is adjacent to each other. It is an object of the present invention to provide a semiconductor memory device that can be disposed.

Furthermore, an object of the present invention is to provide a semiconductor memory device in which row control circuit regions disposed adjacent to each other share a predetermined transmission line, and column control circuit regions disposed adjacent to each other share a predetermined transmission line. .

In accordance with an aspect of the present invention, a semiconductor memory device includes: a first row control circuit region and a first column control circuit region corresponding to a first memory bank; A second row control circuit region corresponding to a second memory bank and disposed adjacent to the first row control circuit region; And a second column control circuit region corresponding to the third memory bank and disposed adjacent to the first column control circuit region.

In accordance with another aspect of the present invention, a semiconductor memory device includes a row control circuit region corresponding to each of a plurality of memory banks, the row control circuit region disposed adjacent to a neighboring memory bank, and a column control circuit. A first and a second bank group, the first and second bank groups disposed adjacent to the column control circuit region of a neighboring memory bank, and between the first and second bank groups. It has a peripheral circuit area for signal transmission.

In the semiconductor memory device according to the present invention, the row control circuit regions corresponding to the plurality of memory banks are disposed adjacent to each other, and the column control circuit regions corresponding to the plurality of memory banks are disposed adjacent to each other, thereby providing adjacent control circuits. It is possible for an area to share a predetermined transmission line. That is, the semiconductor memory device according to the present invention can share the transmission lines that had to exist in each of the row control circuit region and the column control circuit region, thereby reducing the chip area of the semiconductor memory device by the number of shared transmission lines. Can be reduced.

In addition, according to the present invention, the length of the peripheral circuit region may be shorter than that of a conventional semiconductor memory device, and thus the length of the transmission line disposed in the peripheral circuit region may also be shortened. Shorter transmission lines mean less loading, thus ensuring faster operation of the circuit.

According to the present invention, each row control circuit region shares a transmission line with an adjacent row control circuit region and each column control circuit region shares a transmission line with an adjacent column control circuit region, thereby reducing the number of transmission lines. The effect of reducing the chip area can be obtained.

In addition, since the memory banks may be stacked to minimize the peripheral circuit area, the chip area of the semiconductor memory device as well as the faster circuit operation may be obtained.

Furthermore, since the chip area can be reduced, the number of chips produced in one wafer can be increased, thereby reducing the production cost.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3 is a block diagram illustrating a memory bank structure of a semiconductor memory device according to the present invention. For convenience of description, a semiconductor memory device having eight memory banks will be described as an example.

Referring to FIG. 3, a semiconductor memory device may include first to eighth memory banks. Each of the plurality of memory banks may have corresponding row control circuit areas and column control circuit areas. Hereinafter, the first memory bank 310A, the second memory bank 330A and the fifth memory bank 350A adjacent to the first memory bank 310A will be described.

The first memory bank 310A may include a first row control circuit region 310B in a row direction and a first column control circuit region 310C in a column direction, and the second memory bank 330A may be in a row direction. The second row control circuit region 330B and the second column control circuit region 330C in the column direction may be provided, and the fifth memory bank 350A may have the fifth row control circuit region 350B and the column in the row direction. Direction may include the fifth column control circuit region 350C.

Here, circuits for controlling row access of the corresponding memory bank may be disposed in each row control circuit region, and circuits for controlling column access of the corresponding memory bank may be disposed in each column control circuit region.

Hereinafter, the row control circuit area and the column control circuit area will be described in more detail. Although not shown in detail, each row control circuit area decodes address information input from the CPU to the word line WL, A row decoding unit for selecting a power supply unit, a power supply voltage control unit for controlling a pull-up power supply voltage RTO and a pull-down power supply voltage SB supplied to the bit line sense amplifier 120, and a defective memory cell A low redundancy control unit may be disposed to replace a word line connected to another word line connected to a normal memory cell. Here, the pull-up power supply voltage RTO and the pull-down power supply voltage SB are voltages generated based on the external power supply voltage and the ground power supply voltage, and the external power supply voltage and the ground power supply voltage are shared through the shared power line, which will be described later. Can be delivered.

Subsequently, although not shown in detail, each column control circuit region decodes address information input from the CPU to select a column selection signal YI (see FIG. 1) corresponding to the memory cell. And a read driver 150 for outputting data read from the corresponding memory bank in response to the read command, and a write driver 160 for transferring externally applied data to the corresponding memory bank in response to the write command. And a column redundancy control unit for replacing the column select signal YI connected to the defective memory cell with another column select signal corresponding to a normal memory cell. Here, the column redundancy operation may be performed by replacing a column address corresponding to a defective memory cell with a column address corresponding to a normal memory cell.

Meanwhile, the first row control circuit region 310B and the fifth row control circuit region 350B of the semiconductor memory device according to the present invention are disposed adjacent to each other, and the second column control circuit region 310C and the second column control are disposed adjacent to each other. The circuit regions 330C may be disposed adjacent to each other. Therefore, the first row control circuit region 310B and the fifth row control circuit region 350B may share the same transmission line, and the first column control circuit region 310C and the second column control circuit region ( 330C may be unique to the same transmission line. Here, the same transmission line means a transmission line that can be shared in the first row control circuit region 310B and the fifth row control circuit region 350B. Representatively, a power line, an address line, a test line, and the like are represented. This may be the case.

In other words, in the case of the conventional semiconductor memory device, a power line, an address line, a test line, and the like for each of the plurality of row control circuit areas and the plurality of column control circuit areas had to be disposed due to the structure of the memory bank. However, in the semiconductor memory device according to the present invention, since the row control circuit area and the column control circuit area corresponding to each other are disposed between the memory bank and the adjacent memory bank, the power line, the address line, the test line, and the like are shared. It is possible to arrange. As a result, the semiconductor memory device according to the present invention can reduce the number of transmission lines required than before. This means that the chip area of the semiconductor memory device can be reduced.

On the other hand, as the capacity of semiconductor memory devices increases, the number of addresses applied from the outside also increases. In order to process such a large number of addresses more efficiently, a method of pre-decorating address information is adopted. The semiconductor memory device may include a circuit for performing such a pre-decoding operation, and the region in which the circuits are disposed will be referred to as a "cross circuit region" below.

Prior to the description of the cross circuit area, the up bank group and the down bank group will be described. Here, the up bank group refers to circuits disposed above the peripheral circuit region 370. That is, the up bank group includes a first memory bank 310A, a second memory bank 330A, a fifth memory bank 350A, and a sixth memory bank (not shown). It may include a row control circuit region and a column control circuit region corresponding to the. In addition, it may include an upcross circuit region 390 that is an area where the row control circuit region and the column control circuit region meet on an extension line.

Subsequently, the down bank group refers to circuits disposed below the peripheral circuit region 370. That is, the first memory bank includes a third memory bank, a fourth memory bank, a seventh memory bank, and an eighth memory bank, and includes a row control circuit region and a column control circuit region corresponding to each memory bank, and down-crosses. It may include a circuit region.

On the other hand, as shown in the figure, each memory bank is stacked, it is possible to design the peripheral circuit region 370 to be shorter than the conventional. That is, the transmission line disposed in the peripheral circuit region 370 can be designed to be shorter. In the transmission line disposed in the peripheral circuit region 370, a global input output line (GIO) that is responsible for data transfer between circuits included in the up bank group and the down bank group and a pad (not shown). There is this. Reducing the length of the global I / O lines means less loading for data transmission, which can speed up circuit operation.

On the other hand, the semiconductor memory device according to the present invention may include an up cross circuit region 390 and a down cross circuit region (not shown). For convenience of explanation, the upcross circuit region 390 will be described as a representative.

The upcross circuit region 390 may include a predecoder for predecoding address information, a bank controller for controlling activation of memory banks included in each upbank group, and the like. That is, the memory bank included in the up bank group is activated in response to the bank activation signal (not shown) generated in the up cross circuit region 390, and the row control circuit region and the column control circuit region included in the up bank group. The second terminal may receive pre-decoded address information from the upcross circuit region 390 to perform an operation. Subsequently, the down cross circuit region may also be composed of circuits that perform operations similar to the up cloth circuit region 390.

On the other hand, as shown in the figure, the semiconductor memory device according to the present invention may include one up-cross circuit region 390 and one down-cross circuit region. In the conventional case (see FIG. 2), two regions (not shown) serving this role are provided in the up bank group and the down bank group, respectively, so that a transmission line to which address information is input must have at least four groups. . However, the upcross circuit region 390 of the semiconductor memory device of the present invention can receive address information through a transmission line shared with respect to four memory banks included in the up bank group, and the down cross circuit region is a down bank. Address information may be input through a transmission line shared corresponding to four memory banks included in the group. That is, two groups corresponding to the up bank group and the down bank group may be required for the transmission line for inputting address information.

Subsequently, as the cross circuit areas are reduced from four to two, the number of power lines required, for example, in each cross circuit area can be reduced. As a result, as the number of cross circuit areas is reduced, the number of required transmission lines is also reduced, which also means that the chip area of the semiconductor memory device can be reduced.

Meanwhile, the four row control circuit regions included in the up bank group may share all shareable transmission lines. In this case, the transmission lines may be arranged to cross the up cross circuit region 390. In this context, the four column control circuit regions included in the up bank group may share all the shareable transmission lines, and the row control circuit region and the column control circuit region included in the down bank group may also share the transmission lines. Everyone will be able to share.

The arrangement according to the present invention may be very useful for reducing the chip area of the semiconductor memory device in a situation where the number of memory banks increases as the semiconductor memory device becomes more integrated. Furthermore, reducing the chip area of the semiconductor memory device can increase the number of chips produced in one wafer, thereby reducing the production cost.

In conclusion, in order to reduce the chip area of the highly integrated semiconductor memory device, the row control circuit region is disposed between the row control circuit regions and the column control circuit region is adjacent to the column control circuit regions between neighboring memory banks among a plurality of memory banks. And by sharing the required transmission line, it is possible to reduce the number of required transmission lines.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible with various substitutions, modifications, and changes within the scope of the technical idea of the present invention.

In addition, in the above-described embodiment, the row control circuit region and the column control circuit region each share a power line, an address line, and a test line. It can also be applied to other transmission lines that can be shared in each area.

In addition, in the above-described embodiment, the case in which the global input / output line (GIO, not shown) disposed in the peripheral circuit area 370 is shortened has been described as an example. However, the present invention is a peripheral circuit area due to a stack arrangement of memory banks. Since 370 becomes smaller overall, it can be applied to all the lines disposed in the peripheral circuit region 370.

In addition, in the above-described embodiment, the position of the corresponding row control circuit region and the column control circuit region of each memory bank may be changed according to design.

1 is a view for explaining a general read operation and a write operation of a conventional semiconductor memory device.

2 is a block diagram illustrating a memory bank structure of a conventional semiconductor memory device.

3 is a block diagram illustrating a memory bank structure of a semiconductor memory device according to the present invention;

* Explanation of symbols for the main parts of the drawings

310A: first memory bank 310B: first row control circuit area

310C: first column control circuit area 330A: second memory bank

330B: second row control circuit area 330C: second column control circuit area

350A: fifth memory bank 350B: fifth row control circuit area

350C: fifth column control circuit region 370: peripheral circuit region

Claims (14)

A first row control circuit region and a first column control circuit region corresponding to the first memory bank; A second row control circuit region corresponding to a second memory bank and disposed adjacent to the first row control circuit region; And A second column control circuit region corresponding to a third memory bank and disposed adjacent to the first column control circuit region A semiconductor memory device having a. The method of claim 1, The first column control circuit region and the second column control circuit region share a first transmission line, and the first row control circuit region and the second row control circuit region share a second transmission line. A semiconductor memory device. The method of claim 2, And the first and second transfer lines transmit address information or test information or a power supply voltage, respectively. The method of claim 3, The first and second row control circuit regions, respectively, A row decoder for decoding the address information and selecting a word line of a corresponding memory bank; A power supply voltage controller configured to control the power supplied to the bit line detection amplifier of the corresponding memory bank by receiving the power supply voltage; And And a low redundancy control unit for replacing a word line connected to a defective memory cell with another word line connected to a normal memory cell. The method of claim 3, The first and second column control circuit regions, respectively, A column decoding unit for decoding the address information and selecting memory cells of a corresponding memory bank; A read driver for outputting data read from a corresponding memory bank in response to a read command; A write driver for transferring externally applied data to a corresponding memory bank in response to a write command; And And a column redundancy control unit for replacing column address information corresponding to a defective memory cell with column address information corresponding to a normal memory cell. A row control circuit region corresponding to each of the plurality of memory banks, the row control circuit region corresponding to each of the plurality of memory banks disposed adjacent to the row control circuit region of the neighboring memory bank and the column control circuit disposed adjacent to the column control circuit region of the neighboring memory bank. First and second bank groups, and Peripheral circuit regions disposed between the first and second bank groups to transfer signals between the first and second bank groups and pads. A semiconductor memory device having a. The method of claim 6, And a cross circuit region disposed in an area where the row control circuit region and the column control circuit region meet on an extension line of the row control circuit region. The method of claim 7, wherein The cross circuit region, A decoding unit for decoding the address information; And a bank controller for activating the memory bank. The method of claim 7, wherein And the cross circuit area receives address information applied from the outside through a common transmission line. The method of claim 6, Each of the first and second bank groups A first row control circuit region and a first column control circuit region corresponding to the first memory bank; A second row control circuit region corresponding to a second memory bank and disposed adjacent to the first row control circuit region; And And a second column control circuit region corresponding to the third memory bank and disposed adjacent to the first column control circuit region. The method of claim 10, The first column control circuit region and the second column control circuit region share a first transmission line, and the first row control circuit region and the second row control circuit region share a second transmission line. A semiconductor memory device. The method of claim 11, And the first and second transfer lines transmit address information or test information or a power supply voltage, respectively. The method of claim 10, The first and second row control circuit regions, respectively, A row decoder for decoding the address information and selecting a word line of a corresponding memory bank; A power supply voltage controller configured to control the power supplied to the bit line detection amplifier of the corresponding memory bank by receiving the power supply voltage; And And a low redundancy control unit for replacing a word line connected to a defective memory cell with another word line connected to a normal memory cell. The method of claim 10, The first and second column control circuit regions, respectively, A column decoding unit for decoding the address information and selecting memory cells of a corresponding memory bank; A read driver for outputting data read from a corresponding memory bank in response to a read command; A write driver for transferring externally applied data to a corresponding memory bank in response to a write command; And And a column redundancy control unit for replacing column address information corresponding to a defective memory cell with column address information corresponding to a normal memory cell.

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