KR20090076711A - Chipset for splash images application in multimedia apparatus - Google Patents

Abstract

A chipset for supporting an initial image in a multimedia apparatus is provided to support an application for support a splash image by hardware without storing the application in a memory, thereby removing a burden of a memory. A register unit receives information of an image stored in a memory. The register unit sets a register value of the image. A memory controller(220) transmits a read signal to the memory according to a location and a size of the image. A buffer(240) stores image data inputted from the memory by the read signal. The buffer outputs the image data as an image output signal. A clock generator(230) outputs a video clock signal according to resolution of the image.

Description

Chipset for splash images application in multimedia apparatus}

The present invention relates to a chipset of a multimedia device, and more particularly, to a chipset capable of more quickly outputting an initial image output upon initial power-up of a multimedia device.

Recently, various multimedia have been digitized, and devices supporting various multimedia have been developed. Digital versatile disks (DVDs), which are capable of semi-permanently storing multimedia of higher quality, have become commonplace, and IP set-top boxes (IP), which mediate various multimedia to TVs and monitors, are spreading through networks.

Multimedia devices such as a DVD player, an IP set-top box, an IP TV, and a portable multimedia player (PMP) output a splash image to a monitor when the initial power is applied. The initial image is used to inform the user that the multimedia device is turned on and to recognize the logo of the manufacturer of the multimedia device.

1 is a block diagram illustrating a processor for supporting a conventional initial image.

Referring to FIG. 1, in order to support an initial image, the memory 10 includes a raw image 11, an image application 12, and an OS + application image 13. The operating system application image 13 is a file in which the operating system and the kernel are compressed. While the operating system application image 13 is compressed and stored for the efficiency of the memory, in order to quickly output the initial image upon initial power-up, the raw image 11 and the image application 12 are uncompressed in memory. Are stored in.

When the initial power is applied, the central processing unit 20 immediately executes the image application 12. The operating system application image 13 needs time to decompress and load. The image application 12 reads the raw image 11 from the memory 10 and outputs the raw image 11 to the display device 40 through the display controller 30.

When the initial image is stored in the uncompressed memory in the raw image 11 and the image application 12 in order to output quickly before all the kernels are loaded, the original image 11 and the image application 12 ) Occupies a storage space as large as the operating system application image 13 that compresses the operating system and the kernel, thereby burdening the memory 10. In particular, in a system in which the storage space of the memory 10 is limited, a large ratio of the memory must be allocated for outputting an initial image, which causes a decrease in the efficiency of the system.

There is a need for a processor that can reduce the burden of memory in a multimedia device and output an initial image quickly.

An object of the present invention is to provide a chipset that can reduce the burden of the memory in the multimedia device and quickly output the initial image.

According to an aspect of the present invention, a chipset that supports a splash image output upon initial power-up in a multimedia device may receive information about a position, a size, and a resolution of an image stored in a memory from a CPU. A resist unit for setting a resist value for size and resolution, a memory controller for sending a read signal to the memory according to the position and size of the image set in the resist unit, input from the memory by the read signal And a clock generator configured to store the image data, and output a video clock signal according to the resolution of the image. The apparatus may further include a multiplexer configured to multiplex the image output signal and the video clock signal. The multiplexer may selectively output the image output signal and the video clock signal from a signal sent from the CPU. The apparatus may further include a display controller configured to modulate a signal output from the multiplexer into a signal that can be executed in the display device.

According to another aspect of the present invention, a chipset supporting an initial image may include a memory for storing an image file for an initial image, an initial image loader for reading and outputting the image file stored in the memory as an image signal and inputting the initial image loader. And a multiplexer for selectively outputting the video signal and the video signal input from the CPU. The apparatus may further include a display controller configured to modulate a signal output from the multiplexer into a signal that can be executed in the display device. The initial image loader may receive a register for the position, size, and resolution of the image file from the CPU.

By supporting an application for supporting a splash image output at initial power-up in a multimedia device without hardware in the memory, the burden on the memory can be reduced and the memory can be utilized more efficiently.

FIG. 2 is a block diagram illustrating a chipset supporting a splash image in a multimedia device according to an embodiment of the present invention.

Referring to FIG. 2, a chipset 100 supporting an initial image includes a memory 110, a CPU 120, a display controller 130, a splash image loader 150, and a multiplexer. (multiplexer, MUX; 160).

The memory 110 stores a raw image 111 and an operating system application image 113. The raw image 111 is stored in an uncompressed state, and the operating system application image 113 is compressed and stored.

The initial image loader 150 reads the raw image 111 from the memory 110 and outputs an image signal to the multiplexer 160. The video signal includes a video output signal and a video clock signal. The initial image loader 150 receives a register for the storage location of the raw image 111, the size of the image file, and the image resolution from the CPU 120.

The CPU 120 notifies the register to the initial image loader 150 for outputting the initial image. The register consists of information about a storage location of the original image 111 stored in the memory 110, an image file size, an image resolution, and the like. The CPU 120 outputs an input selection signal, an image output signal, and a video clock signal to the multiplexer 160. The input selection signal causes the multiplexer 160 to select and input an image signal input from the initial image loader 150 and an image signal input from the CPU 120.

The multiplexer 160 selectively outputs signals input from the CPU 120 and the initial image loader 150 according to an instruction of the CPU 120, that is, an input selection signal. That is, the multiplexer 160 outputs an initial image input from the initial image loader 150 to the display controller 130 when initial power is applied, and receives an input selection signal from the CPU 120 while outputting the initial image. When the image output signal and the video clock signal input from the CPU 120 is output to the display controller 130.

The image output signal output from the initial image loader 150 and the CPU 120 to the multiplexer 160 is a CVBS (Composite Video Blanking Sync) signal, Y / Cb / Cr signal, RGB (Red, Green, Blue) signal, etc. This can be The CVBS signal is a video signal in which the color difference, brightness, and sync of the image are mixed into one. The Y / Cb / Cr signal is a video signal in which the brightness and sync of the video are mixed and the color difference is separated. The RGB signal is R (red). , G (green), B (blue) and sink are all separated video signals. The video clock signal output from the initial image loader 150 and the CPU 120 to the multiplexer 160 may be a vertical synchronization signal vsync, a horizontal synchronization signal hsync, a valid signal, and the like.

The display controller 130 modulates the image output signal and the video clock signal input from the multiplexer 160 into signals suitable for the image application and the display device 40 according to internal register settings input from the CPU 120. The modulated image output signal and the video clock signal are displayed through the display device 40.

3 is a block diagram illustrating a structure of an initial image loader according to an embodiment of the present invention. The initial image loader may be configured as one chip or chipset.

Referring to FIG. 3, a splash image loader 200 may register a register 210, a memory controller 220, a clock generator 230, and a buffer 240. Include.

The register unit 210 receives an address signal ADDR, a data signal DATA, a write signal WR, and a read signal RD from the CPU 120. Set the value. The register is mapped to an address signal ADDR, an image file size signal FILE SIZE, and an image resolution signal IMAGE SIZE, indicating a location of an image stored in the memory 110. The register unit 210 sends an address signal ADDR and an image file size signal FILE SIZE to the memory controller 220, and sends an image resolution signal IMAGE SIZE to the clock generator 230.

The memory controller 220 may receive an address signal ADDR and an image file size signal FILE SIZE from the register unit 210 to find the location of the image and the size of the image file in the memory 110. The memory controller 220 sends an address signal ADDR indicating the position of the image to the memory 110. The memory 110 sends an acknowledgment (ACK) signal in response to the address signal ADDR. The memory controller 220 generates a read signal RD reading the image data according to the position of the image and the size of the image file and sends the read signal RD to the memory 110. The memory 110 transmits the image data signal DATA to the buffer 240 according to the read signal RD.

The buffer 240 stores image data input from the memory 110. The buffer 240 generates image data as an image output signal and sends the image data to the multiplexer 160. The image output signal may be a CVBS (Composite Video Blanking Sync) signal, a Y / Cb / Cr signal, an RGB (Red, Green, Blue) signal, or the like.

The clock generator 230 generates a video clock signal suitable for the image resolution signal IMAGE SIZE input from the register unit 210 and sends it to the multiplexer 160. The video clock signal may be a vertical synchronization signal vsync, a horizontal synchronization signal hsync, a valid signal, and the like.

The multiplexer 160 multiplexes an image output signal input from the buffer 240 and a video clock signal input from the clock generator 230. The multiplexer 160 may selectively output signals input from the CPU 120 and the initial image loader 200 according to the instruction of the CPU 120.

In the above description, the initial image loader 200 and the multiplexer 160 are separated from each other. However, the initial image loader 200 and the multiplexer 160 may be configured as one chip. In addition, the CPU 120, the initial image loader 200, the multiplexer 160, the memory 110, and the display controller (FIG. 2 130) may be configured as one chip.

In order to support the splash image output when the power is initially supplied from the multimedia device, the application is hardware-supported using the initial image loader 200 and the multiplexer 160 without storing the application in the memory 110. Thus, the burden on the memory 110 can be reduced and the memory 110 can be utilized more efficiently.

Although the present invention has been described above with reference to the embodiments, it will be apparent to those skilled in the art that the present invention may be modified and changed in various ways without departing from the spirit and scope of the present invention. I can understand. Therefore, the present invention is not limited to the above-described embodiment, and the present invention will include all embodiments within the scope of the following claims.

1 is a block diagram illustrating a processor for supporting a conventional initial image.

FIG. 2 is a block diagram illustrating a chipset supporting a splash image in a multimedia device according to an embodiment of the present invention.

3 is a block diagram illustrating a structure of an initial image loader according to an embodiment of the present invention.

Claims (7)

A resist unit which receives information on a position, a size, and a resolution of an image stored in a memory from a CPU, and sets a resist value for the position, the size, and the resolution of the image; A memory controller which sends a read signal to the memory according to the position and size of the image set in the resist unit; A buffer for storing image data input from the memory by the read signal and outputting the image data as an image output signal; And And a clock generator for outputting a video clock signal according to the resolution of the image. The chipset of claim 1, further comprising a multiplexer for multiplexing the video output signal and the video clock signal. The chipset of claim 2, wherein the multiplexer selectively outputs the image output signal and the video clock signal from a signal transmitted from the CPU. The chipset of claim 2, further comprising a display controller configured to modulate a signal output from the multiplexer into a signal that can be executed in a display device. A memory for storing an image file for an initial image; An initial image loader reading the image file stored in the memory and outputting the image file as an image signal; And And a multiplexer for selectively outputting an image signal input from the initial image loader and an image signal input from the CPU. The chipset of claim 5, further comprising a display controller configured to modulate a signal output from the multiplexer into a signal that can be executed in a display device. The chipset of claim 5, wherein the initial image loader receives a register for the position, size, and resolution of the image file from the CPU.

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