KR20090075530A - Shader processor, method for processing dual phase instruction - Google Patents

Abstract

A shader processor and a dual phase command processing method using a phase processing unit of N reads out source data and an arithmetic-logic unit computing source data are provided to process commands in dual phase type. N phase processors read out source data from a register unit according to a phase command. An arithmetic and logic unit(135) includes operators of the m(arbitrary natural number). The arithmetic and logic unit outputs the result data by operating source data received from each phase processing unit according to the predetermined method.

Description

Shader processor, method for processing dual phase instruction

The present invention relates to a shader processor, and more particularly to a three-dimensional graphics shader processor capable of processing dual page instructions.

 The real-time three-dimensional graphics field is developing at a very fast pace as hardware improvements and usage increases. Three-dimensional graphics use a large amount of data to perform complex operations. By transferring the functions that were previously implemented on the CPU to the graphics hardware, the performance is improved and the CPU can concentrate on tasks other than graphics.

In general, a graphics processor unit (hereinafter referred to as a GPU) which is dedicated to processing graphics operations for acceleration of 3D graphics is used. The GPU consists of various functional acceleration units, such as fixed pipeline transform and lighting processors, rasterizers, and shaders.

Among these, the shader provides the user with an environment in which to program operations to be performed on the GPU. In general, rendering refers to the process of adding realism to computer graphics by incorporating three-dimensional textures, such as shadows or changes in color and density, and shaders add the relationship between objects and light to these processes. This allows you to handle various effects. Therefore, if you enable the shader option, texture acceleration will give you a more realistic graphical image.

Shader functionality, high level language, assembly language, and structural features are defined in the 3D graphics programming interface standards Direct3D and OpenGL (Open Graphics Library). Vertex Shader Model 2.0 and Pixel Shader Model 2.x versions of Direct3D support Static Flow Control, and Dynamic Flow Control from Vertex Shader Model 2.x and Pixel Shader Model 3.0 versions. ), Loop and branch functions.

However, in the related art, the shader is processed in a single instruction multiple data architecture (SIMD) scheme, which causes a lot of waste for an operator.

The present invention provides a shader processor and a dual phase instruction processing method capable of processing shader instructions in a dual phase manner.

The present invention also provides a shader processor and dual phase instruction processing method capable of supporting shader model 3.0 and OpenGL-ES 2.0 including loop instructions and branch instructions.

The present invention also provides a shader processor and a dual phase instruction processing method capable of flexibly processing instructions by grouping n registers.

The present invention also provides a shader processor and a dual phase instruction processing method capable of sharing an arithmetic logic unit that simultaneously executes up to two kinds of instructions.

The present invention also provides a shader processor and a dual phase instruction processing method capable of reconstructing each instruction into one or more unit instructions.

According to an aspect of the present invention, there is provided a shader processor capable of simultaneously calculating n phase instructions by reconfiguring the instructions in phase units.

According to an embodiment of the present invention, a shader processor includes: an extractor for extracting one or more unit instructions; An instruction constructing unit configured to analyze the k unit instructions, divide them into phase units, and generate and output one or more phase instructions; N phase processing units (where n is a natural number of 2 or more) for reading and outputting source data according to the phase command from a register unit; And an arithmetic logic operation unit having m (random natural numbers) operators, each receiving the source data from each phase processing unit, performing arithmetic operations according to a predetermined method, and outputting result data respectively. Can be provided.

The arithmetic logic unit shares the m operators by the n phase processors, receives n source data according to the n phase instructions from the n phase processors, and performs n operations according to the same clock. Results of operations can be output.

The unit command may consist of a first status bit, a second status bit, and a command bit of p (any natural number) bit.

The first status bit may include extension information of a unit command, and the second status bit may include phase division information of a unit command.

The instruction configuration unit analyzes the first status bits of the input unit instructions to determine the size or number of operation instructions, and analyzes the second status bits of each unit instruction included in the determined operation instruction to generate one or more phase instructions. Can be generated and printed.

If the first status bit of the target unit command among the input unit commands is a first bit value, the instruction configuration unit determines up to the target unit command as the operation command, and the second of the unit command included in the operation command. If the status bit is a second bit value, it may be determined as a first phase command. If the status bit is a third bit value, it may be determined as a second phase command.

The instruction constructing unit may update the program counter using a subsequent address of the target unit instruction, and the drawing unit may fetch unit instructions with reference to the program counter.

The phase processor may include a first phase processor and a second phase processor, and the command component may output the generated phase command to the second phase processor if the generated phase command is any one of a branch, an indirect address, and a loop command.

According to another aspect of the present invention, a method is provided in which a shader processor processes instructions in a dual phase manner.

According to an embodiment of the present invention, a method in which a shader processor processes an instruction in a dual phase manner, the method comprising: (a) fetching one or more unit instructions; (b) analyzing the retrieved unit instructions and dividing them into phase units to generate one or more phase instructions; (c) reading and outputting source data according to each phase command from a register unit; And (d) receiving each of the source data and performing arithmetic operations according to a predetermined method, respectively, and outputting arithmetic results, wherein step (c) is performed at predetermined time intervals corresponding to the number of generated phase instructions. An instruction processing method may be provided that accesses a unit and reads and outputs source data according to each phase command.

The unit command consists of a first status bit, a second status bit and a command bit of p (any natural number) bit.

The first status bit may include extension information of a unit command, and the second status bit may include phase division information of a unit command.

The step (b) may include analyzing a first status bit of the retrieved unit instructions to determine a size or number of arithmetic instructions; And analyzing the second status bit of each unit command included in the determined operation command to generate one or more phase commands.

The method may further include updating a program count using a subsequent address of the target unit command, wherein step (a) may refer to the program counter with reference to the program counter.

By providing the shader processor and the dual phase instruction processing method according to the present invention, there is an effect that can process the instruction in a dual phase method.

In addition, the present invention has the effect of supporting shader model 3.0 and OpenGL-ES 2.0, including loop instructions and branch instructions.

In addition, the present invention also has the effect of being able to flexibly process instructions by grouping n registers.

In addition, the present invention also has the effect of sharing the arithmetic logic unit that can simultaneously execute up to two types of instructions.

The present invention also has the effect of reconstructing each instruction into one or more unit instructions.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all transformations, equivalents, and substitutes included in the spirit and scope of the present invention. In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The shader processor 100 according to the present invention, which will be described below, may simultaneously process up to two instructions corresponding to the same clock to output respective calculation results. Hereinafter, each internal functional block of the shader processor 100 according to the present invention will be described in detail with reference to FIG. 1.

1 is a diagram illustrating an internal functional block of a shader processor according to an embodiment of the present invention, FIG. 2 is an exemplary diagram for explaining an exclusive pairing rule according to an embodiment of the present invention, and FIG. 3 is an embodiment of the present invention. 4 is a diagram illustrating a form of an operation instruction according to an embodiment of the present invention, and FIG. 4 is a diagram illustrating a drawing process of unit instructions according to an embodiment of the present invention.

As illustrated in FIG. 1, the shader processor 100 according to the present invention may include a drawing unit 110, an instruction constructing unit 115, a register unit 120, a first phase processing unit 125, and a second phase processing unit ( 130) and the arithmetic logic unit 135 is configured.

In the present specification, the shader processor 100 may extract a plurality of unit instructions, divide them into phase units, generate one or more phase instructions, and access the register unit 120 at predetermined time intervals to read source data. The shader processor 100 includes n phase processing units (for example, the first phase processing unit 125 and the second phase processing unit 130), and each phase processing unit (for example, The first phase processor 125 and the second phase processor 130 share a single arithmetic logic unit 135. Accordingly, in the shader processor 100 according to the present invention, n (random natural numbers) phase processing units (for example, the first phase processing unit 125 and the second phase processing unit 130) may include one arithmetic logic unit 135. ) May be shared to perform calculations corresponding to respective phase commands according to the same clock (or control signal), and output the calculation results.

As described above, the arithmetic logic unit 135 is shared by the n number of phase processing units (for example, the first phase processing unit 125 and the second phase processing unit 130), and each phase processing unit ( For example, each phase instruction processed by the first phase processing unit 125 and the second phase processing unit 130 should not use the same operator of the arithmetic logic operation unit 135.

Hereinafter, each command input to the n processing units (for example, the first phase processing unit 125 and the second phase processing unit 130) will be referred to as a phase command. The phase command will be described in more detail with reference to the accompanying drawings below.

That is, a phase command input to the first phase processor 125 is called a first phase command, and a phase command input to the second phase processor 130 is called a second phase command.

In the present specification, a rule configured such that n phase instructions calculated through the arithmetic logic unit 135 corresponding to the same clock or control signal do not use the same arithmetic operator of the arithmetic logic unit 135 so as to not use an "exclusive paying rule ( exclusive paring rules) ".

Referring to FIG. 2, the first phase instruction (ie, mul abc) and the second phase instruction (ie, add def) of 210a and 210b correspond to the same clock since they use multipliers and adders of the arithmetic logic unit 135, respectively. It can be seen that the operation for each phase instruction can be performed. That is, each phase instruction illustrated in 210a and 210b may be performed without using the same operator of the arithmetic logic unit 135.

As will be described in more detail below, the arithmetic logic unit 135 has a respective operator corresponding to each component (eg, x y z w). Therefore, when each phase instruction processed by the first phase processor 125 and the second phase processor 130 is configured not to use the same operator for each component, the arithmetic logic unit 135 corresponds to the same clock. You can perform the operation.

In the case of the first phase instruction (mul.xabc, add.yz bc) and the second phase instruction (add.xw def, mul.yzw ef) illustrated in 220a and 220b, a multiplier and an adder are used, but the components are different. Able to know. Accordingly, it can be seen that the first phase command and the second phase command do not use the same operator of the arithmetic logic operation unit 135 so that the operation can be performed corresponding to the same clock.

In the case of the first phase instruction (add.xyz abc) and the second phase instruction (add.xdef) illustrated in 230a and 230b, the arithmetic unit corresponding to the same clock is used because the operator of the same component (that is, the adder of the x component) must be used repeatedly. It can be seen that only one phase instruction is calculated by the logic operator 135.

In addition, only one operator for the phase instruction (RPC instruction) illustrated in 240a is provided in the arithmetic logic operation unit 135, and the RPC instruction is performed by sharing all areas of the arithmetic logic operation unit 135 so that simultaneous execution with other instructions is possible. impossible.

In addition, the phase instruction (MOV instruction) illustrated in 250a and 250b uses the data path of the operation result of each component (X, Y, Z, W) operator. Accordingly, since the MOV instruction does not have an operator that is actually provided in the arithmetic logic operation unit 135, overlapping is allowed unlike other instructions.

Referring to 260a and 260b, in the case of the first phase command (branch 100) and the second phase command (branch 200), the first phase processing unit 125 and the second phase processing unit 130 are instructions for changing the control flow in the case of the branch instruction. Must be performed in either). In the present specification, for convenience of understanding and description, it will be described on the assumption that complex instructions such as branch and loop instructions are performed only through the second phase processor 130.

In addition, in the case of the indirect address command (indirect) illustrated in 270b, the register unit 120 needs to be accessed n times with the instruction including the address in the operand to read the source data. Therefore, in the case of the indirect address command, the second phase processor 130 must be executed by the control of the first phase processor 125. For this reason, it will be assumed that the indirect address command is performed by the first phase processor 125.

Exemplary pairing rules according to the present invention will be fully understood by the foregoing description, and the internal functional blocks of the shader processor 100 will be described with reference to FIG. 1 again.

Hereinafter, in the present specification, it is assumed that shader instructions (for example, MUL, ADD, BL, Call, etc.) are rearranged into a maximum of four unit instructions, and the shader processor 100 fetches the unit instructions to each operation. This will be described.

Since the method of rearranging the shader instructions into one or more unit instructions in the shader processor 100 is obvious to those skilled in the art, a separate description thereof will be omitted.

(n은 임의의 자연수)비트 단위의 유닛 명령들을 인출하여 명령 구성부(115)로 출력한다. 본 명세서에서는 쉐이더 명령이 128비트인 것을 가정하며, 하나의 쉐이더 명령은 최대 4개의 유닛 명령으로 구성되어 있는 것을 가정한다. 따라서, 인출부(110)는 프로그램 카운터를 참조하여 회당 4개의 유닛 명령을 인출하여 명령 구성부(115)로 출력한다. Referring again to FIG. 1, the drawing unit 110 may refer to a program counter (PC).

(n is an arbitrary natural number) The unit instructions in units of bits are extracted and output to the instruction constructing unit 115. In the present specification, it is assumed that the shader instruction is 128 bits, and that one shader instruction is composed of up to four unit instructions. Accordingly, the withdrawal unit 110 withdraws four unit instructions per time with reference to the program counter and outputs them to the instruction configuration unit 115.

The program counter is incremented by the number of unit commands fetched and stores the address of the next instruction to be fetched. If the instruction to be executed is a branch instruction, the address of the program counter is changed according to the result of the discrimination condition determination. Accordingly, the instruction corresponding to the address indicated by the program counter changed after the branch instruction is executed. That is, the drawing unit 110 may obtain a start address of a command to be fetched at a current time (or a clock) with reference to a program counter. Since this is obvious to those skilled in the art, a separate description thereof will be omitted.

In the following description, the shader instruction is assumed to be composed of up to four unit instructions for the purpose of convenience of understanding and description. In addition, when the number of unit instructions constituting the shader instruction is different, it is apparent that the number of unit instructions drawn out per unit by the drawing unit 110 may be different.

For convenience of understanding and explanation, the structure of the unit instruction will be briefly described with reference to FIG. 3.

As shown in FIG. 3, each unit command consists of a first status bit 310, a second status bit 315, and an instruction bit 320 of m (any natural number) bits.

The first status bit 310 indicates whether or not each unit command is extended, and the second status bit 315 indicates whether a phase command including the unit command belongs.

For example, if the first status bit 310 is the first bit value (eg, "0"), then the unit command is recognized as an extended command and the first status bit 310 is the second bit value. (Eg, "1"), the unit command is recognized as the last command. This will be described in more detail in the command configuration unit 115 below.

Referring again to FIG. 1, the extractor 110 extracts a plurality of unit instructions by referring to a program counter and outputs the same to the instruction constructing unit 115 as described above.

The instruction constructing unit 115 analyzes k (arbitrary natural numbers) unit instructions input through the drawing unit 110 to determine the number and size of the computation instructions. In addition, the instruction configuring unit 115 analyzes the determined operation instruction to generate up to n (random natural numbers) phase instructions for each phase processing unit (eg, the first phase processing unit 125 and the second phase processing unit 130). Output as)).

In the present specification, the operation instruction is defined as an instruction that can be operated simultaneously through the arithmetic logic operation unit 135 within the same clock.

For example, the instruction constructing unit 115 may analyze the first status bits of the input k unit instructions to determine the size and number of operation instructions.

For example, assume that the address of the program counter is "6", as illustrated in FIG. In such a case, the drawing unit 110 refers to the address "6" of the program counter, and withdraws four unit instructions from the corresponding address and outputs it to the instruction constructing unit 115. Here, assume that the first status bit of the input unit commands is as illustrated at 410. The instruction constructing unit 115 compares whether the first status bit of the first unit command input is the second bit value. Since the first status bit of the first unit command is the first bit value, the instruction construct 115 compares whether the first status bit of the second unit command is the second bit value. Since the first status bit of the second unit command is also the first bit value, the instruction constructing unit 115 compares whether the first status bit of the third unit command is the second bit value. Since the first status bit of the third unit instruction is the second bit value, the instruction constructing unit 115 determines that the first unit instruction to the third unit instruction is an operation instruction operable within the same clock by the arithmetic logic operation unit 135. . The instruction constructing unit 115 then updates the address of the program counter using the subsequent address of the third unit instruction ("9" in FIG. 4). Accordingly, the withdrawal unit 110 may withdraw four unit commands from the corresponding address (ie, “9”) at the next time point.

In addition, the instruction constructing unit 115 determines the size and number of operation instructions, analyzes the second status bits of each unit instruction included in the operation instruction, and divides them into phase units to generate one or more phase instructions.

In addition, suppose that the number of unit instructions withdrawn from the takeout unit 110 is four. In this case, the operation instruction may be configured in four forms.

That is, as illustrated in 325 to 340 of FIG. 3, the operation instruction may be composed of at least one unit instruction and may be composed of up to four unit instructions.

In the following description, it is assumed that one phase command is composed of a maximum of two unit commands in order to facilitate understanding and explanation.

In addition, the instruction constructing unit 115 recognizes the first phase command if the second status bit of each unit command included in the operation instruction is the first bit value, and the second phase command if the second status bit is the second bit value. I can recognize it.

Referring again to FIG. 1, the register unit 120 stores a program counter and a plurality of source data. In addition, the register unit 120 stores arithmetic results calculated by the arithmetic logic operation unit 135.

In the present specification, it is assumed that two phase processing units (for example, the first phase processing unit 125 and the second phase processing unit 130) are described.

The first phase processor 125 and the second phase processor 130 decode each input phase command and access the register 120 corresponding to the phase command to read and output the corresponding source data. do. In addition, when a subcommand is input from the first phase processor 125, the second phase processor 130 may read source data from the register unit 120 corresponding to the subcommand.

The register unit 120 and the arithmetic logic unit 135 according to the present invention are shared by n phase processing units (the first phase processing unit 125 and the second phase processing unit 130). For this reason, even if n phase commands are generated, the command configuration unit 115 preferentially outputs the first phase command to the first phase processing unit 125, and then, after a predetermined time elapses, outputs the second phase command to the second phase command. The output may be output to the phase processor 130. For this reason, the first phase processing unit 125 and the second phase processing unit 130 are different from each other in connection with the register unit 120. However, the first phase processing unit 125 and the second phase processing unit 130 correspond to the same clock in order to perform an operation corresponding to each phase command in accordance with the same clock through the arithmetic logic operation unit 135. May be output to the arithmetic logic operation unit 135. To this end, the first phase processor 125 may allow the second phase processor 130 to wait for a predetermined time until the source data is read from the register unit 135.

In another example, the first phase processing unit 125 may include information about an operation command (for example, information about whether one phase command or two phase commands) is received from the command configuration unit 115 together with the phase command. You can also receive input.

That is, when the first phase processor 125 receives the information about the operation command and recognizes that the operation command is composed of one phase command, the inputted phase command regardless of whether the second phase processor 130 performs an operation or not. The source data may be read from the register unit 120 and output to the arithmetic logic operation unit 135 to perform the operation.

However, if it is recognized that the operation command is composed of two phase commands, the first phase processing unit 125 reads the source data according to the input phase command from the register unit 120 when the second phase processing unit 130 is input. After waiting until it may be controlled to output the source data to the arithmetic logic operation unit 135 together. Here, when the reading of the source data is completed, the second phase processing unit 130 may output a control signal to the first phase processing unit 125 to recognize the completion of reading.

The arithmetic logic operation unit 135 includes an operator of m (any natural number) for each component. In addition, the arithmetic logic operation unit 135 is shared by the first phase processing unit 125 and the second phase processing unit 130. That is, the arithmetic logic unit 135 may receive one or more of a first phase command and a second phase command from the first phase processor 125 and the second phase processor 130, respectively, corresponding to the same clock. The arithmetic logic operation unit 135 receives source data from each phase processing unit (eg, the first phase processing unit 125 and the second phase processing unit 130) in accordance with the same clock, and performs a predetermined operation. To output the result.

5 is a diagram illustrating a configuration of a phase command according to an operation command according to an embodiment of the present invention.

As shown in FIG. 5, the operation instruction is composed of up to four unit instructions. Since the operation instructions MUL_sat A, B, and C illustrated in 510 are configured as one unit instruction, they may be processed by the first phase processor 125.

In addition, since the operation instructions ADD A, B, and C illustrated in 515 are one phase instruction composed of two unit instructions, they may be processed by the first phase processor 125.

In addition, since the operation instructions ADD A, B [D.W], and C illustrated in 520 may be configured with one ADDR instruction and one addition instruction, it may be understood that the operation instructions ADD A, B [D.W], and C may be simultaneously operated by configuring two phase instructions.

In addition, the operation instruction ADD_predicate (E) A, B, and C [D.w] of 525 may be composed of two phase instructions. That is, the first phase instruction composed of the ADDR D.W and PREDZ E unit instructions and the second phase instruction composed of the ADD instruction may be configured to simultaneously perform operations through one arithmetic logic operation unit 135.

6 is a flowchart illustrating a method in which a shader processor performs an operation on an arbitrary instruction according to an embodiment of the present invention. Each step described below is performed by each internal component of the shader processor 100, but will be collectively described as the shader processor 100 for the convenience of understanding and description.

In operation 610, the shader processor 100 fetches k (random natural numbers) unit instructions with reference to a program counter.

In operation 615, the shader processor 100 analyzes the extracted k unit instructions to determine the size or number of operation instructions, and analyzes the determined operation instructions to generate one or more phase instructions.

The method of determining the size or number of operation instructions and the method of analyzing the operation instructions and generating one or more phase instructions by dividing them into phase units are the same as described above, and thus redundant description thereof will be omitted.

In operation 620, the shader processor 100 reads and outputs source data according to each generated phase instruction from the register unit 120.

As described above, the shader processor 100 according to the present invention has a structure in which n (random natural numbers) phase processing units share one register unit 120 and an arithmetic logic operation unit 135. As a result, the shader processor 100 may read the source data corresponding to each phase instruction by accessing the register unit at predetermined predetermined time intervals. Since it is the same as described above, overlapping description will be omitted.

In operation 625, the shader processor 100 performs an operation on each source data and outputs an operation result.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention as set forth in the claims below It will be appreciated that modifications and variations can be made.

1 illustrates internal functional blocks of a shader processor in accordance with one embodiment of the present invention.

2 is an exemplary diagram for explaining an exclusive pairing rule according to an embodiment of the present invention.

3 is a diagram illustrating a form of an operation instruction according to an embodiment of the present invention.

4 is a diagram illustrating a process of fetching unit instructions according to an embodiment of the present invention.

5 is a diagram illustrating a configuration of a phase command according to an operation command according to an embodiment of the present invention.

6 is a flowchart illustrating a method in which a shader processor performs an operation on an arbitrary instruction according to an embodiment of the present invention.

Claims (13)

In the shader processor, A drawing unit for drawing one or more unit commands; An instruction constructing unit configured to analyze the unit commands, divide the data into phase units, and generate and output one or more phase commands; N phase processing units (where n is a natural number of 2 or more) for reading and outputting source data according to the phase command from a register unit; And and an arithmetic logic operation unit comprising m (arbitrary natural numbers) operators and receiving the source data from each phase processing unit, and performing arithmetic operations according to a predetermined method, respectively, and outputting result data. According to claim 1, The arithmetic logic unit shares the m operators by the n phase processors, receives n source data according to the n phase instructions from the n phase processors, and performs n operations according to the same clock. A shader processor for outputting the result of the operation. According to claim 1, And wherein the unit instruction consists of a first status bit, a second status bit, and an instruction bit of p (any natural number) bit. The method of claim 3, wherein And the first status bit includes extension information of a unit command, and the second status bit includes phase discrimination information of a unit command. The method of claim 3, wherein The command configuration unit analyzes the first status bits of the unit instructions to determine the size or number of operation instructions, and analyzes the second status bits of each unit instruction included in the determined operation instruction to generate one or more phase instructions. Outputting a shader processor. The method of claim 5, If the first status bit of the target unit command of the input unit command is the first bit value of the input unit command, the command configuration unit determines up to the target unit command as the operation command, A shader, if the second state bit of the unit command included in the operation instruction is a second bit value, is determined as a first phase instruction; and if the second state bit is a third bit value, the shader is determined as a second phase instruction. Processor. The method of claim 6, The instruction constructing unit updates the program counter with a subsequent address of the target unit instruction, And the drawing unit fetches unit instructions with reference to the program counter. The method of claim 2, The phase processing unit includes a first phase processing unit and a second phase processing unit, And the instruction constructing unit outputs the generated phase instruction to the second phase processor if the generated phase instruction is any one of a branch, an indirect address, and a loop instruction. In the method that the shader processor processes instructions in a dual phase manner, (a) withdrawing one or more unit instructions; (b) analyzing the retrieved unit instructions and dividing them into phase units to generate one or more phase instructions; (c) reading and outputting source data according to each phase command from a register unit; And (d) receiving each of the source data and performing arithmetic operation according to a predetermined method to output arithmetic results, The step (c) of the command processing method, characterized in that for accessing the register unit at a predetermined predetermined time interval corresponding to the number of generated phase command to read and output the source data according to each phase command. The method of claim 9, And said unit command is comprised of command bits of a first status bit, a second status bit, and a p (any natural number) bit. The method of claim 10, The first status bit includes extended information of a unit command, and the second status bit includes phase discrimination information of a unit command. The method of claim 11, wherein In step (b), Analyzing a first status bit of the retrieved unit instructions to determine a size or number of arithmetic instructions; And And analyzing the second status bit of each unit instruction included in the determined operation instruction to generate one or more phase instructions. The method of claim 12, Updating a program count using a subsequent address of the target unit instruction, In the step (a), the unit command is fetched with reference to the program counter.

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