KR20090075044A - Display driver integrated circuit capable of improving data transmission efficiency - Google Patents

Abstract

A display driver integrated circuit is provided to reduce data transmission speed between a timing controller and a display circuit by reducing a lock time of a delay locked loop. Source drivers(210, 220, 230) operate a panel by using a data signal and a clock signal from a timing controller. Clock signal generators(211, 221, 231) generate an arranged clock signal to drive the operation panel, and a coast signal generator(240) generates a coast signal having more than one active section by corresponding to the operation of a source driver, and controls the arrangement of clock signal generator in the active section disable.

Description

Display Driver Integrated Circuit Capable of Improving Data Transmission Efficiency

The present invention relates to a display driving circuit, and more particularly, to a display driving circuit with improved data transmission efficiency.

In recent years, as the resolution and frame rate of a display device including a liquid crystal panel display device are improved, more channels are integrated in a display driver IC for driving a panel. It is a trend. In order to support such an improved resolution and frame rate, the data transfer rate between the display driving integrated circuit and a timing controller must be increased.

Due to the characteristics of the data transmission line between the driving integrated circuit and the timing controller, the characteristics of the signal are degraded due to impedance mismatch, which causes a limit in increasing the data transmission rate. In order to overcome this problem, the number of transmission lines may be increased, but in this case, an increase in electromagnetic interference (EMI) may occur, and a problem such as an increase in complexity on the PCB board may occur.

As a method of improving the data transmission speed between the driving integrated circuit and the timing controller while reducing the above problems, a point-to-point or clock embedded method is a transmission method of the next generation display. The trend is being adopted. In particular, in a clock embedded scheme, the timing controller does not transmit a clock signal to a driving integrated circuit through a separate transmission line, but simultaneously transmits data and a clock signal to the driving integrated circuit through the same transmission line. The driving integrated circuit extracts and uses a clock signal among the signals transmitted through the transmission line.

Meanwhile, when a plurality of source drivers provided in the driving integrated circuit simultaneously provide data to the panel in synchronization with a predetermined data enable signal, the voltages VDD and And / or VSS voltage), and as an example, the level of the supply voltage is fluctuated by about ± 200-300 mV. Such supply noise affects the analog circuits provided in the driving integrated circuit, and in particular, a delay locked loop and / or a phase locked loop including a clock embedded method. In the case of a driving integrated circuit including a phase locked loop, the supply noise greatly affects the operation of the delay lock loop and / or the phase lock loop.

That is, if the delay lock loop is maintained while the supply noise is generated, the level of the delay control voltage in the delay lock loop is greatly shaken, and then restored again after the supply noise generation period has passed. The time it takes to increase. Supply noise has a similar effect on the phase locked loop, which increases the lock time like the delay locked loop.

As a method for preventing the influence of the supply noise, the timing controller may not consider providing data to the driving integrated circuit while the driving integrated circuit performs data such as providing data to the panel. . However, in such a case, the data transfer efficiency between the timing controller and the driving integrated circuit is reduced, and a problem arises in that the transfer rate must be increased during data transfer.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a display driving circuit which improves data transmission efficiency by reducing the lock time of a delay lock loop and / or a phase lock loop.

In order to achieve the above object, the display driving circuit according to an embodiment of the present invention, at least one source driver for driving the panel using a data signal and a clock signal provided from the timing controller, and the driving of the panel; One or more clock signal generators for generating clock signals arranged for use, and generating a coast signal having one or more activation intervals corresponding to an operating state of the source driver, and converting the coast signal into the clock signal. And a cost signal generator for controlling the alignment operation of the clock signal generator to be disabled during the activation period by providing the signal generator.

Preferably, each of the one or more clock signal generators is one of a phase locked loop and a delay locked loop.

Also preferably, the coast signal may be in an active state at the time when the source driver starts providing the data signal to the panel and / or when the source driver stops providing the data signal to the panel. It is characterized by.

Preferably, the cost signal is generated using a second control signal that is out of phase with a first control signal for controlling data supply from the source driver to the panel.

On the other hand, the cost signal generator, in response to the level transition of the control signal associated with the data supply from the source driver to the panel to activate and output the cost (coast) signal after the level transition of the control signal and After a predetermined time elapses, an activation control unit may provide an activation control signal to the signal generator to control the coast signal to be deactivated.

Preferably, the activation control unit performs a counting operation as many as a preset number in response to the transition of the control signal, and activates an active control signal for controlling the coast signal to be deactivated after the counting operation ends. It is characterized in that the counter provided to the generator.

Each of the one or more clock signal generators may be any one of a phase locked loop and a delay locked loop, and the cost signal may be provided in the clock signal generator. One or more circuit blocks of the plurality of circuit blocks may be provided to control the alignment operation to be disabled.

Preferably, the coast signal is provided to at least one of a phase detector and a charge pump included in the clock signal generator, thereby controlling the alignment operation to be disabled.

Preferably, the activation period of the coast signal corresponds to a noise generation period of the power supply voltage VDD and / or the ground voltage VSS provided to the source driver.

Preferably, the at least one clock signal generation unit is provided to extract a clock signal provided from the timing controller.

According to the present invention as described above, it is possible to reduce the lock time of the phase synchronization loop and / or delay synchronization loop provided in the display driving circuit, thereby improving the data transfer efficiency between the timing controller and the display driving circuit. In addition, there is an effect that can lower the transmission speed during data transmission.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings that illustrate preferred embodiments of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a block diagram illustrating a display driving circuit according to an exemplary embodiment of the present invention. As shown, the display device includes a display driving circuit 200 for driving the panel 100. The display driving circuit 200 receives the data signal and the clock signal clk from the timing controller 300, and uses the received data signal and the clock signal clk to control the panel 100. Drive.

The display driving circuit 200 includes one or more source drivers S / D, 210, 220, and 230 for providing an image to the panel 100 by providing a data signal to the source line. In FIG. 1, only the source drivers 210, 220, and 230 are shown in the display driving circuit 200 to explain an embodiment of the present invention. It will be apparent to those skilled in the art that an internal voltage generator or the like for generating a voltage may be provided.

The display driving circuit 200 may include one or more clock signal generators 211, 221, and 231 which generate clock signals aligned for use in driving the panel 100. As an example of the clock signal generators 211, 221, and 231, a phase locked loop (PLL) is illustrated. The clock signal generators 211, 221, and 231 may use a delay locked loop (DLL) for generating an aligned clock signal.

1 illustrates an example in which the display driving circuit 200 and the timing controller 300 transmit signals in a clock embedded manner. According to the above scheme, the timing controller 300 simultaneously provides the data signal data and the clock signal clk to the source drivers 210, 220, and 230 through the same transmission line. Each of the source drivers 210, 220, and 230 extracts a clock signal clk based on signals provided through the same transmission line, and uses the same to drive the panel 100.

Meanwhile, the clock signal generators 211, 221, and 231 extract the clock signal clk using signals provided through transmission lines corresponding to the respective source drivers 210, 220, and 230. Accordingly, each of the clock signal generators 211, 221, and 231 may be disposed in each of the source drivers 210, 220, and 230. In addition, although FIG. 1 illustrates a case where a phase locked loop and / or a delay locked loop are disposed in the source drivers 210, 220, and 230, embodiments of the present invention are not limited thereto. It can be applied to the entire display driving circuit having a delay lock loop. In addition, the embodiment of the present invention may be applied to the case of transmitting a signal between the display driving circuit 200 and the timing controller 300 according to another method besides clock embedded.

On the other hand, if the data signal is provided to the panel 100 or the supply is blocked by driving an amplifier (not shown) provided in the source driver 210, 220, 230, the display driver 200 is provided to the display driving circuit 200. Supply noise occurs in the voltage (VDD and / or VSS voltage) values. The generation of the supply noise causes a problem of increasing the lock time of the phase locked loop and / or the delay locked loop. Accordingly, in one embodiment of the present invention, a cost signal generator 240 is provided in the display driving circuit 200, and the cost signal generator 240 is the source driver 210, 220, In response to the operating state of 230, a cost signal having one or more activation periods is generated. The coast signal is provided in a phase locked loop and / or a delay locked loop, and the phase locked loop and / or the delay locked loop disable an alignment operation during an activation period of the cost signal.

Meanwhile, in relation to an activation period of a coast signal, the activation period may be a time point at which the source driver 210, 220, or 230 starts providing the data signal to the panel 100 and / or the source driver. Reference points 210, 220, and 230 block the provision of the data signal data to the panel 100. Preferably, the cost signal may include a first activation period and a second activation period, and the source driver 210, 220, or 230 may start providing the data signal to the panel 100. The time point exists in the first activation period, and the time point at which the source driver 210, 220, 230 blocks the provision of the data signal data to the panel 100 exists in the second activation period.

In order to generate the coast signal as described above, the coast signal generator 240 may use a predetermined control signal. Preferably, the display driving circuit 200 may receive a control signal for controlling data provision from the source driver 210, 220, 230 to the panel 100, and the cost signal generator 240 may The cost signal may be generated using the signal TP_PRE ahead of a predetermined section phase.

Accordingly, by disabling the alignment operation of the clock signal generators 211, 221, and 231 using a cost signal at a time when supply noise may occur, a loop (DLL and / or PLL) due to supply noise is generated. Loop) to prevent shaking. In addition, after the supply noise is reduced, the lock time may be reduced by performing the alignment operation of the clock signal generators 211, 221, and 231 again. As the lock time is reduced, the restriction of the signal transmission interval between the display driving circuit 200 and the timing controller 300 may be minimized.

A detailed configuration and operation of the display driving circuit 200 shown in FIG. 1 will be described below.

2A and 2B are block diagrams illustrating a clock signal generator included in the display driving circuit of FIG. 1. As an example, FIG. 2A illustrates a case in which one clock signal generator 211 is a phase locked loop (PLL), and FIG. 2B illustrates that one clock signal generator 211 is a delayed synchronization loop (DLL). The case is shown.

As shown in FIG. 2A, the phase locked loop PLL includes phase / frequency detection units 211_1 and PFD, charge pumps 211_2 and CP, loop filters 211_3 and LPF, and voltage controlled oscillators 211_4 and VCO), frequency divider 211_5, Divider, and the like. The coast signal generated from the coast signal generator 240 is provided to any one or more of a plurality of circuit blocks included in the phase lock loop PLL to align the phase lock loop PLL. You can disable the operation.

For example, the cost signal may be provided to any one or more of the phase / frequency detectors 211_1 and PFD and the charge pump 211_2 and CP. When a coast signal is provided to the phase / frequency detectors 211_1 and PFD, the phase / frequency detectors 211_1 and PFD respond to the input signal Fin and the feedback signal in response to activation of the coast signal. Regardless of the phase difference of the signal divided by Fout, a pulse signal is not generated, or when a coast signal is provided to the charge pumps 211_2 and CP, in response to activation of the coast signal. The charge pump 211_2 and CP may disable the charge pumping operation, thereby disabling the alignment operation of the phase locked loop PLL.

As illustrated in FIG. 2B, the delay synchronization loop DLL may include a phase detector PD, a charge pump CP, a loop filter LPF, a voltage control delay unit VCDL, and the like. . The cost signal generated from the cost signal generator 240 is provided to any one or more of a plurality of circuit blocks included in the delay synchronization loop DLL to align the delay synchronization loop DLL. You can disable the operation. For example, the cost signal may be provided to any one or more of the phase detector PD and the charge pump CP. As described above, the alignment operation of the delay synchronization loop DLL may be disabled by blocking the generation of the pulse signal according to the phase difference or by blocking the charge pumping operation.

FIG. 3 is a circuit diagram illustrating in detail the cost signal generator of FIG. 1.

As shown in FIG. 3A, the cost signal generator 240 includes a signal generator 241 for activating and outputting a cost signal, and the signal generator 241. The control unit 242 may be configured to generate an active control signal CON for controlling the cost signal to be deactivated by controlling.

The signal generator 241 receives a signal related to providing data to the panel 100 from the source drivers 210, 220, and 230, and activates and outputs a cost signal in response to the level transition of the signal. . As described above, the cost signal is activated and output using the signal TP_PRE ahead of a control signal for controlling the data supply from the source drivers 210, 220, 230 to the panel 100. .

On the other hand, the activation controller 242 provides the active control signal CON to the signal generator 241 to control the coast signal to be deactivated, thereby controlling the cost signal generated by the signal generator 241. The width of the activation section can be controlled. Preferably, the activation control unit 242 provides an active control signal CON to the signal generation unit 241 when a predetermined time elapses after the level transition of the signal TP_PRE, so that the cost signal is generated. You can control it to be deactivated.

Also preferably, the activation control unit 242 may include a counter. The counter performs a counting operation as many as a preset number in response to the level shift of the signal TP_PRE. As an example, the counter operates in response to the level transition of the signal TP_PRE, and performs a counting operation on the clock by a predetermined number of predetermined clock signals (for example, the signal Fout may be used). can do. The counter provides an active control signal CON to the signal generator 241 when the counting operation is completed. In this case, the width of the activation interval of the cost signal depends on the counting number set in the counter.

3B is a circuit diagram illustrating an example of an implementation of the signal generator 241. As illustrated, the signal generator 241 may include one or more flip-flops 241_1 and 241_2 and a logic element 241_3. An example of an OR gate is shown as an example of the logic element 241_3.

As shown, a power supply voltage VDD may be input to input terminals of one or more flip-flops 241_1 and 241_2, and the signal TP_PRE is input to a clock terminal of one or more flip-flops 241_1 and 241_2. Can be. The signal TP_PRE may be inverted and input to the clock terminal of one flip-flop 241_2. In addition, the active control signal CON may be input to the reset terminal R of the one or more flip-flops 241_1 and 241_2.

Meanwhile, output signals of one or more flip-flops 241_1 and 241_2 may be input to an input terminal of the logic element 241_3, which may be an OR gate. The logic device 241_3 may perform a logical sum operation on the output signals of the one or more flip-flops 241_1 and 241_2, and provide the result as a cost signal.

FIG. 4 is a waveform diagram illustrating an operation of a coast signal generator of FIG. 3. By using a control signal TP for controlling data supply from the source drivers 210, 220, and 230 to the panel 100, the signal TP_PRE may be generated before the control signal TP. The signal TP_PRE is provided to the clock terminal of the flip-flop 241_1, and the inverted signal of the signal TP_PRE is provided to the clock terminal of the flip-flop 241_2.

First, a coast signal is activated in response to the rising edge of the signal TP_PRE. In addition, in response to the rising edge of the signal TP_PRE, the counter performs a counting operation for a predetermined number. The active control signal CON is generated in response to the counter completing the counting operation by the preset number. In response to the active control signal CON, a coast signal is deactivated again.

Thereafter, the coast signal is activated again in response to the falling edge of the signal TP_PRE. In addition, in response to the falling edge of the signal TP_PRE, the counter performs a counting operation as many as a preset number. As the counter provides the active control signal CON to the signal generator 241 in response to the completion of the counting operation by the preset number, the coast signal is inactivated again.

As shown in FIG. 4, a coast signal is in an activated state at the rising edge of the control signal TP, and a coast signal is in an active state at the falling edge of the control signal TP. That is, since the coast signal is activated at the rising edge of the control signal TP corresponding to the data providing time from the source drivers 210, 220, and 230 to the panel 100, the clock signal corresponds to the occurrence of supply noise. The alignment operation of the generators 211, 221, and 231 is disabled. In addition, since the coast signal is activated at the falling edge of the control signal TP corresponding to the time point at which the data supply from the source drivers 210, 220, 230 to the panel 100 is cut off, the clock signal corresponds to the supply noise. The alignment operation of the generators 211, 221, and 231 is disabled.

5A and 5B are block diagrams and waveform diagrams for illustrating a first example of using the coast signal of FIG. 1. The cost signal is provided to a phase locked loop (PLL) or a delay locked loop (DLL) to disable the alignment operation of the phase locked loop (PLL) or delay locked loop (DLL). As an example, FIG. 5A shows that a cost signal is provided to the phase / frequency detection unit 211_1 (PFD) of the phase locked loop PLL.

As shown in FIG. 5B, when an activated coast signal is input while the PLL is operating, the phase / frequency detection unit may be used regardless of the state of the up signal UP and the down signal DOWN. The reset signal is provided to one or more flip-flops provided in 211_1. By the reset signal, the up signal UP and the down signal DOWN output from one or more flip-flops are deactivated during the activation period of the cost signal.

6A and 6B are block diagrams and waveform diagrams for illustrating a second example of using the coast signal of FIG. 1. As an example, FIG. 6A shows that a cost signal is provided to the charge pumps 211_2, CP of the phase locked loop PLL.

As shown in FIG. 6B, the up signal UP and the down signal DOWN are output with a predetermined waveform according to various signals provided to the phase / frequency detection unit 211_1, and the up signal UP and the down signal are output. The pumping operation of the charge pump 211_2 is controlled by DOWN controlling the switch provided in the charge pump 211_2. However, since the activated cost signal controls the current source provided in the charge pump 211_2 to be disabled, the actual pumping operation does not occur even if the switch is turned on.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a block diagram illustrating a display driving circuit according to an exemplary embodiment of the present invention.

2A and 2B are block diagrams illustrating a clock signal generator included in the display driving circuit of FIG. 1.

FIG. 3 is a circuit diagram illustrating in detail the cost signal generator of FIG. 1.

FIG. 4 is a waveform diagram illustrating an operation of a coast signal generator of FIG. 3.

5A and 5B are block diagrams and waveform diagrams for illustrating a first example of using the coast signal of FIG. 1.

6A and 6B are block diagrams and waveform diagrams for illustrating a second example of using the coast signal of FIG. 1.

  Explanation of symbols on the main parts of the drawings

100: panel

200: display driving circuit

210, 220, 230: source driver

211, 221, and 231: clock signal generator

240: coast signal generator

300: timing controller

Claims (11)

One or more source drivers for driving the panel using data signals and clock signals provided from the timing controller; One or more clock signal generators for generating clock signals aligned for use in driving the panel; And In response to an operating state of the source driver, a coast signal having at least one activation period is generated, and the coast signal is provided to the clock signal generator so that the alignment operation of the clock signal generator is performed during the activation period. And a cost signal generator for controlling to be disabled. The method of claim 1, And each of the one or more clock signal generators is one of a phase locked loop and a delay locked loop. The method of claim 1, wherein the cost (coast) signal, And at the time when the source driver starts providing the data signal to the panel and / or when the source driver stops providing the data signal to the panel. The method of claim 3, wherein the cost signal (coast), And a second control signal whose phase is earlier than a first control signal for controlling the data supply from the source driver to the panel. The method of claim 1, wherein the cost signal generation unit, A signal generator for activating and outputting the cost signal in response to a level shift of a control signal associated with providing data from the source driver to the panel; And And an activation controller for providing an active control signal to the signal generator for controlling the coast signal to be deactivated after a predetermined time elapses after the level transition of the control signal. The method of claim 5, wherein the activation control unit, And a counter configured to perform a counting operation as many as a preset number in response to the transition of the control signal, and to provide the signal generator with an active control signal for controlling the coast signal to be deactivated after the counting operation ends. Display drive circuit. The method of claim 5, Each of the one or more clock signal generators is any one of a phase locked loop and a delay locked loop. The cost signal may be provided to one or more circuit blocks of a plurality of circuit blocks included in the clock signal generator to control the alignment operation to be disabled. The method of claim 7, wherein And the cost signal is provided to at least one of a phase detector and a charge pump included in the clock signal generator, thereby controlling the alignment operation to be disabled. The method of claim 5, And the control signal is a second control signal whose phase is earlier than a first control signal for controlling data supply from the source driver to the panel. The method of claim 1, And an activation period of the coast signal corresponds to a noise generation period of a power supply voltage VDD and / or a ground voltage VSS provided to the source driver. The method of claim 1, wherein the one or more clock signal generation unit, And a clock signal for extracting a clock signal provided from the timing controller.

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