JP5987292B2 - Semiconductor integrated circuit device and electronic apparatus using the same - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device employing an SSCG (Spread Spectrum Clock Generation) system that reduces electromagnetic radiation noise by diffusing the spectrum of a clock signal. Furthermore, the present invention relates to an electronic device using such a semiconductor integrated circuit device.

  With the recent increase in the speed of electronic devices, the frequency of clock signals used in electronic devices is increasing, and an increase in electromagnetic radiation noise radiated from electronic devices has become a problem. In order to reduce such electromagnetic radiation noise, an SSCG system that spreads the spectrum of a clock signal has been developed.

  In a semiconductor integrated circuit device adopting the SSCG method, the peak component of electromagnetic radiation noise is reduced by frequency-modulating the clock signal to spread the spectrum of the clock signal. However, when an unexpected event such as electrostatic discharge or abnormal fluctuation of power supply voltage occurs, the frequency of the clock signal is fixed due to deadlock of the SSCG circuit, or the waveform of the clock signal is disturbed due to malfunction of the SSCG circuit. To do.

  Therefore, conventionally, the deadlock or malfunction of the SSCG circuit has been prevented by inserting multiple malfunction prevention circuits or malfunction detection circuits. However, in order to verify that such a malfunction prevention circuit or malfunction detection circuit operates reliably, a great amount of man-hours is required, and it is proved that the malfunction prevention circuit or malfunction detection circuit operates reliably. Was very difficult.

  As a related technique, Patent Document 1 discloses an electronic control device capable of continuing a stable CPU operation even if there is a transient CPU abnormal phenomenon such as noise. This electronic control unit determines whether or not an abnormality has occurred in the CPU based on an operation signal periodically output as a pulse having a predetermined cycle and duty from the CPU that controls the operation of the entire system. A CPU monitoring means for outputting an abnormal signal indicating an abnormality of the CPU when it is determined that an abnormality has occurred, and a counter for counting the number of occurrences of the abnormal signal output from the CPU monitoring means; When the value reaches a predetermined abnormality detection threshold, a reset signal for resetting the CPU is output.

  In this CPU monitoring means, whether or not an abnormality has occurred in the CPU is determined by whether or not the pulse period and / or duty of the operation signal output from the CPU is within a predetermined allowable range. However, if such a determination is made in the SSCG circuit, the circuit scale increases and it is considered difficult to prove that the circuit operates reliably.

JP 2007-65961 A (Claims 1 and 2, FIG. 1)

  According to some aspects of the present invention, in a semiconductor integrated circuit device that reduces electromagnetic radiation noise by diffusing the spectrum of a clock signal, an SSCG circuit can be obtained by using a circuit configuration that is small and simple and operates reliably. Can reliably recover from deadlocks and malfunctions.

  In order to solve the above problems, a semiconductor integrated circuit device according to one aspect of the present invention is a semiconductor integrated circuit device that reduces electromagnetic radiation noise by frequency-modulating a clock signal, and has a clock having a predetermined frequency. A modulated frequency by selecting a delay circuit that outputs a multiphase clock signal having a plurality of different phases based on the signal and one of the multiphase clock signals output from the delay circuit according to the selection signal A reset circuit that generates a modulated clock signal, a clock stop detection circuit that outputs a reset signal when generation of the modulation clock signal by the selection circuit stops, and a reset signal output from the clock stop detection circuit, Counts the number of pulses contained in the modulated clock signal generated by the selection circuit. To generate a selection signal so as to increase or decrease the frequency of the modulation clock signal in a predetermined modulation period in response to the timing signal generated by the timing signal generation circuit and the timing signal generation circuit generated periodically. And a control circuit.

  Here, the timing signal generation circuit increments the count value in synchronization with the modulation clock signal generated by the selection circuit, and outputs the timing signal and resets the count value when the count value reaches the set value. You may make it do.

  Alternatively, the timing signal generation circuit increments the count value in synchronization with the modulation clock signal generated by the selection circuit, and outputs the timing signal and the count value when the count value reaches the first set value. The count value may be reset when becomes the second set value.

  The semiconductor integrated circuit device further includes an input terminal for inputting a period setting signal, and the timing signal generation circuit sets a period for generating the timing signal in accordance with the period setting signal input to the input terminal, and the control circuit However, the modulation period for increasing or decreasing the frequency of the modulation clock signal may be set according to the period setting signal input to the input terminal.

  Furthermore, an electronic apparatus according to one aspect of the present invention includes any one of the above semiconductor integrated circuit devices.

  According to the present invention, the clock stop detection circuit that outputs a reset signal when the generation of the modulation clock signal is stopped, and the number of pulses that are reset by the reset signal and included in the modulation clock signal are counted periodically. By using a timing signal generation circuit that generates a timing signal at the same time, the control circuit is initialized at regular intervals, so that the SSCG circuit can be reliably recovered from a deadlock or malfunction.

1 is a block diagram showing a configuration of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration example of a delay circuit illustrated in FIG. 1. The figure for demonstrating selection operation | movement of the multiphase clock signal output from a delay circuit. FIG. 2 is a block diagram illustrating a configuration example of a clock stop detection circuit illustrated in FIG. 1. FIG. 2 is a block diagram showing a first configuration example of a timing signal generation circuit shown in FIG. 1. FIG. 3 is a block diagram showing a second configuration example of the timing signal generation circuit shown in FIG. 1. The figure which shows the relationship between the timing signal of 1 pulse, and the frequency of a modulation | alteration clock signal. The figure which shows the relationship between a periodic timing signal and the frequency of a modulation clock signal.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same referential mark is attached | subjected to the same component and the overlapping description is abbreviate | omitted.
FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit device according to an embodiment of the present invention. This semiconductor integrated circuit device employs an SSCG (Spread Spectrum Clock Generation) system that reduces electromagnetic radiation noise by diffusing the spectrum of a clock signal. For example, electronic devices such as mobile phones and liquid crystal televisions. And used to drive a liquid crystal display panel.

  As shown in FIG. 1, the semiconductor integrated circuit device includes a clock signal generation circuit 10, a delay circuit 20, a selection circuit 30, a clock stop detection circuit 40, a timing signal generation circuit 50, a control circuit 60, The logic circuit 70, the functional block 80, the synchronization block 90, the driver circuit 100, and a plurality of input terminals and output terminals are included.

  The clock signal generation circuit 10 generates a clock signal having a predetermined frequency (hereinafter also referred to as “reference clock signal”) using a crystal resonator or the like. Note that the clock signal generation circuit 10 may not be provided in the semiconductor integrated circuit device, but a reference clock signal may be input from the outside to the clock signal terminal CK.

  The delay circuit 20 to the control circuit 60 constitute an SSCG circuit block (SS macro) that generates a modulated clock signal having a modulated frequency by frequency-modulating the reference clock signal. In the present embodiment, a clock stop detection circuit 40 and a timing signal generation circuit 50 are provided in order to initialize the control circuit 60 at regular intervals and restore the SSCG circuit from deadlock or malfunction.

  The delay circuit 20 outputs a multiphase clock signal having a plurality of different phases based on the reference clock signal. The selection circuit 30 generates a modulated clock signal having a modulated frequency by selecting one of the multiphase clock signals output from the delay circuit 20 in accordance with the selection signal.

  The clock stop detection circuit 40 outputs a reset signal (for example, high active) when the generation of the modulation clock signal by the selection circuit 30 is stopped. The timing signal generation circuit 50 is reset by the reset signal output from the clock stop detection circuit 40 and counts the number of pulses included in the modulation clock signal generated by the selection circuit 30 to thereby perform timing periodically. A signal (eg, high active) is generated.

  In response to the timing signal generated by the timing signal generation circuit 50, the control circuit 60 generates a selection signal so as to increase or decrease the frequency of the modulation clock signal in a predetermined modulation period. Since the control circuit 60 is initialized at fixed intervals by a periodically generated timing signal, it can easily recover from a deadlock or malfunction.

  When the reset signal (internal reset signal) output from the clock stop detection circuit 40 and the external reset signal input to the external reset signal input terminal RST are high active, an OR circuit is used as the logic circuit 70. . The logic circuit 70 obtains a logical sum of the internal reset signal and the external reset signal and supplies a reset signal representing the logical sum to the timing signal generation circuit 50 and the control circuit 60.

  Therefore, the timing signal generation circuit 50 and the control circuit 60 are reset when the generation of the modulation clock signal by the selection circuit 30 is stopped and when the external reset signal becomes active due to a power-on reset or the like. Become. When reset, the control circuit 60 may generate a selection signal so as to increase or decrease the frequency of the modulation clock signal in a predetermined modulation period.

  The functional block 80 inputs image data from the outside via the data input terminal DIN, and processes image data in synchronization with the modulation clock signal, thereby realizing functions such as image processing. The synchronization block 90 outputs the image data input from the function block 80 in synchronization with the reference clock signal. The driver circuit 100 operates in synchronization with the reference clock signal, generates a plurality of drive signals for driving the liquid crystal display panel based on the image data input from the synchronization block 90, and outputs these drive signals. Supply to terminals S1 to SJ.

Next, each circuit constituting the SSCG circuit block will be described in detail.
FIG. 2 is a block diagram showing a configuration example of the delay circuit shown in FIG. The delay circuit 20 includes a buffer 21 to which a reference clock signal is input and a plurality of serially connected delay circuits 22, 23, 24, which sequentially delay the clock signal CK (t) output from the buffer 21 by each delay amount. ... and so on. Here, the buffer may be configured by connecting two inverters in series. Each delay circuit may be realized by a gate delay of one buffer or a plurality of buffers connected in series.

As shown in FIG. 2, [Delta] T ₁ the delay amount in the first delay circuit 22 to the 2K-th delay circuit _{25, ΔT 2, ···, ΔT} K, ···, is represented by [Delta] T _2K (K Is a natural number), and at time t, multiphase clock signals CK (t), CK (t−T ₁ ), CK (t−T ₂ ),..., CK (t−T _K ),. (T−T _2K ) is output from the delay circuit 20. _{However, T 1 = ΔT 1, T} 2 = ΔT 1 + ΔT 2, ···, is a _{T K = ΔT 1 + ΔT 2} + ··· + ΔT K, T 2K = ΔT 1 + ΔT 2 + ··· + ΔT 2K.

Here, when the clock signal CK (t−T _K ) is considered as a phase reference, there are K clock signals having a phase advanced from that and K clock signals having a phase delayed from that. It will be. Accordingly, by sequentially selecting one clock signal from among (2K + 1) multiphase clock signals CK (t) to CK (t−T _2K ), the phase of the clock signal CK (t−T _K ) is centered. A modulated clock signal whose phase increases or decreases can be generated.

For example, if the phase difference is set at equal intervals such as ΔT ₁ = ΔT ₂ = ΔT ₃ =..., Clock signals CK (t), CK (t−T ₁ ), and CK (t−T) whose phases are gradually delayed. ₂ ) In a period in which... Are sequentially selected, frequency modulation having a constant negative frequency shift can be realized. On the other hand, in a period in which the clock signals CK (t−T _2K ), CK (t−T _2K−1 ), CK (t−T _{2K− 2} ) _,. A frequency modulation with a positive frequency deviation of can be realized.

Alternatively, when ΔT is a constant delay amount, if the phase difference is cumulative as ΔT ₁ + ΔT = ΔT ₂ , ΔT ₂ + ΔT = ΔT ₃ ,..., Clock signals CK (t), CK In a period in which (t−T ₁ ), CK (t−T ₂ ),... Are sequentially selected, it is possible to realize frequency modulation in which the instantaneous frequency changes linearly with time.

FIG. 3 is a diagram for explaining the selection operation of the multiphase clock signal output from the delay circuit shown in FIG. Here, as an example, a case where three clock signals CK (t), CK (t−T ₁ ), and CK (t−T ₂ ) are used will be described. As indicated by (1) to (5) in FIG. 3, by sequentially selecting one clock signal from these clock signals, a low instantaneous frequency and a high instantaneous frequency are alternated every predetermined modulation period. A modulation clock signal MCK (t) having the same can be generated.

  FIG. 4 is a block diagram showing a configuration example of the clock stop detection circuit shown in FIG. The clock stop detection circuit 40 includes a counter 41, a frequency dividing circuit 42, an edge detection circuit 43, a comparison circuit 44, and a threshold setting unit 45.

  The counter 41 includes a plurality of D flip-flops and a logic circuit such as an EXOR circuit and an AND circuit, and has a reset terminal RST used for resetting the count value. The counter 41 counts the number of pulses included in the reference clock signal and outputs the count value to the comparison circuit 44.

  The frequency dividing circuit 42 includes one or a plurality of D flip-flops, divides the modulated clock signal by a predetermined frequency dividing ratio, and outputs the divided modulated clock signal (divided signal). Note that the frequency dividing circuit 42 can output a frequency-divided signal having a waveform close to a rectangular wave even when the waveform of the modulated clock signal is disturbed.

  The edge detection circuit 43 includes, for example, a delay circuit configured by a buffer and an EXOR circuit that obtains an exclusive OR of an input signal and an output signal of the delay circuit, and the frequency division output from the frequency division circuit 42 The edge of the signal is detected, and an edge detection signal that becomes active at the edge portion of the divided signal is supplied to the reset terminal RST of the counter 41. The count value in the counter 41 is reset to zero by this edge detection signal.

  The comparison circuit 44 compares the count value output from the counter 41 with the threshold value set in the threshold value setting unit 45, and outputs a reset signal when the count value reaches or exceeds the threshold value.

  When the modulated clock signal is generated, the frequency-divided signal transitions between the low level and the high level, so that the edge detection signal is periodically activated and the counter 41 is periodically reset. Thereby, since the count value output from the counter 41 does not exceed the threshold value, the comparison circuit 44 does not output a reset signal. For example, when the modulation rate of the modulation clock signal is 25%, the frequency dividing circuit 42 divides the modulation clock signal by 4, and the threshold value set in the threshold value setting unit 45 is 10, output from the counter 41 Since the counted value is less than 10, no reset signal is output.

  On the other hand, when the generation of the modulation clock signal is stopped, the frequency-divided signal is fixed at the low level or the high level, and the edge detection signal is not activated, so that the counter 41 is not reset. As a result, the count value output from the counter 41 gradually increases and becomes equal to the threshold value. The comparison circuit 44 outputs a reset signal when the count value becomes equal to the threshold value.

  FIG. 5 is a block diagram showing a first configuration example of the timing signal generation circuit shown in FIG. The timing signal generation circuit 50 includes a modulation period table 51, an addition circuit 52, a comparison circuit 53, and a logic circuit 54.

  The modulation period table 51 is configured by a register or the like. As shown in FIG. 1, the semiconductor integrated circuit device has an input terminal SET for inputting a cycle setting signal, and the timing signal generation circuit 50 has a cycle setting value according to the cycle setting signal input to the input terminal SET. Is stored in the modulation period table 51.

  The adder circuit 52 includes a plurality of D flip-flops and a logic circuit such as an EXOR circuit and an AND circuit, and has a reset terminal RST used for resetting the count value. The adder circuit 52 functions as a counter that counts the number of pulses included in the modulated clock signal by incrementing the count value by one in synchronization with the modulated clock signal.

  The comparison circuit 53 compares the count value output from the adder circuit 52 with the set value stored in the modulation cycle table 51, and outputs a timing signal when the count value reaches or exceeds the set value. To do. The timing signal output from the comparison circuit 53 and the reset signal output from the logic circuit 70 (FIG. 1) are input to the logic circuit 54.

  When the timing signal and the reset signal are high active, an OR circuit is used as the logic circuit 54. The logic circuit 54 obtains a logical sum of the timing signal and the reset signal and supplies a signal representing the logical sum to the reset terminal RST of the adder circuit 52.

  Therefore, the adder circuit 52 is reset when the count value becomes equal to the set value and when the reset signal becomes active. When the reset signal is inactive, the cycle in which the timing signal generation circuit 50 generates the pulsed timing signal is set according to the cycle setting signal input to the input terminal SET (FIG. 1).

  As described above, the reason for operating the timing signal generation circuit 50 based on the modulation clock signal instead of the reference clock signal is that the selection circuit 30 synchronizes the timing for selecting the multiphase clock signal with the modulation clock signal. This is to prevent the waveform of the modulated clock signal generated by 30 from being disturbed.

  FIG. 6 is a block diagram showing a second configuration example of the timing signal generation circuit shown in FIG. In the second configuration example, a comparison circuit 55 is added to the first configuration example. The comparison circuit 55 compares the count value output from the addition circuit 52 with the first set value, and outputs a timing signal when the count value becomes the first set value or higher. If the first set value is set to “0”, the timing signal is output when the count value in the adder circuit 52 is “0”.

  On the other hand, the comparison circuit 53 compares the count value output from the addition circuit 52 with the second set value stored in the modulation cycle table 51, so that the count value becomes the second set value or higher. When this happens, the count value reset signal is output. The count value reset signal output from the comparison circuit 53 and the reset signal output from the logic circuit 70 (FIG. 1) are input to the logic circuit 54.

  When the count value reset signal and the reset signal are high active, an OR circuit is used as the logic circuit 54. The logic circuit 54 obtains a logical sum of the count value reset signal and the reset signal, and supplies a signal representing the logical sum to the reset terminal RST of the adder circuit 52.

  Therefore, the addition circuit 52 is reset when the count value becomes equal to the second set value and when the reset signal becomes active. When the reset signal is inactive, the cycle in which the timing signal generation circuit 50 generates the pulsed timing signal is set by the cycle setting signal input to the input terminal SET (FIG. 1).

  Referring again to FIG. 1, in response to the timing signal generated by the timing signal generation circuit 50, the control circuit 60 generates a selection signal so as to increase or decrease the frequency of the modulation clock signal in a predetermined modulation period. Here, the control circuit 60 sets the modulation period for increasing or decreasing the frequency of the modulation clock signal in accordance with the period setting signal input to the input terminal SET (FIG. 1).

  The control circuit 60 includes a counter or a shift register. Below, the case where a counter is used is demonstrated. For example, the control circuit 60 sets the first threshold value to the third threshold value according to the cycle setting signal. The control circuit 60 is initialized by the timing signal, resets the count value to zero, and then counts the number of pulses included in the modulated clock signal to generate the count value.

The control circuit 60 determines that the phase of the clock signal selected by the selection circuit 30 is from the clock signal CK (t−T _K ) shown in FIG. A selection signal is generated so as to proceed sequentially like CK (t−T ₂ ), CK (t−T ₁ ), and CK (t).

  Further, the control circuit 60 generates a selection signal so that the phase of the clock signal selected by the selection circuit 30 is sequentially delayed during the period from when the count value exceeds the first threshold value until the second threshold value is reached. The selection signal is generated so that the phase of the clock signal selected by the selection circuit 30 is sequentially advanced during the period from when the count value exceeds the second threshold value until the third threshold value is reached. When the count value reaches the third threshold value, the modulation operation for one modulation period is completed, and the control circuit 60 maintains the selection signal at the initial value.

  FIG. 7 is a diagram illustrating the relationship between the timing signal of one pulse and the frequency of the modulation clock signal. The selection circuit 30 sequentially selects one of the multiphase clock signals according to the selection signal generated by the control circuit 60, whereby the frequency of the modulation clock signal changes as shown in FIG.

In the example shown in FIG. 7, the frequency of the modulation clock signal is increased or decreased in one modulation period in response to one pulse of the timing signal. For example, the center frequency f ₀ of the modulation clock signal is 20 MHz, the minimum frequency f ₁ of the modulation clock signal is 15 MHz, and the maximum frequency f ₂ of the modulation clock signal is 25 MHz. Before and after the modulation period, the frequency of the modulation clock signal is set to a constant value (for example, the center frequency f ₀ ). Note that the frequency of the modulation clock signal may be increased or decreased in a plurality of modulation periods in response to one pulse of the timing signal.

  FIG. 8 is a diagram illustrating the relationship between the periodically generated timing signal and the frequency of the modulated clock signal. Since the timing signal generation circuit 50 periodically generates a plurality of pulses of the timing signal, the control circuit 60 is periodically initialized. After the frequency of the modulation clock signal is increased or decreased in the first modulation period in response to the first pulse of the timing signal, the frequency of the modulation clock signal is changed to the second modulation period in response to the second pulse of the timing signal. In this way, the frequency of the modulated clock signal is continuously modulated.

  As described above, the control circuit 60 performs a complex operation. Even if the control circuit 60 is deadlocked or continuously malfunctions, the control circuit 60 performs a certain period of time by the timing signal periodically generated by the timing signal generation circuit 50. Therefore, it is always possible to return to the normal state after a certain period of time. On the other hand, the timing signal generation circuit 50 that generates the timing signal is a small-scale circuit composed of only the D flip-flop and the basic combinational logic circuit, and therefore has a low possibility of deadlock and malfunction and operates reliably. Can be proved easily.

  However, since the timing signal generation circuit 50 operates in synchronization with the modulation clock signal, the timing signal cannot be generated when the generation of the modulation clock signal is stopped. Therefore, by providing the clock stop detection circuit 40 that generates the reset signal when the generation of the modulation clock signal is stopped, the timing signal generation circuit 50 is reset when the generation of the modulation clock signal is stopped. Will be generated. Similarly to the timing signal generation circuit 50, the clock stop detection circuit 40 is a small-scale circuit composed of only a D flip-flop and a basic combinational logic circuit. You can prove it easily.

  DESCRIPTION OF SYMBOLS 10 ... Clock signal generation circuit, 20 ... Delay circuit, 21 ... Buffer, 22-25 ... Delay circuit, 30 ... Selection circuit, 40 ... Clock stop detection circuit, 41 ... Counter, 42 ... Frequency division circuit, 43 ... Edge detection circuit , 44 ... comparison circuit, 45 ... threshold value setting unit, 50 ... timing signal generation circuit, 51 ... modulation period table, 52 ... addition circuit, 53, 55 ... comparison circuit, 54 ... logic circuit, 60 ... control circuit, 70 ... logic Circuit 80 ... Function block 90 ... Synchronization block 100 ... Driver circuit

Claims (4)

A semiconductor integrated circuit device for frequency-modulating a clock signal,
A modulation clock generation circuit for generating a modulation clock signal having a modulated frequency;
The count value is incremented in synchronization with the modulation clock signal generated by the modulation clock generation circuit, a timing signal is output when the count value reaches the first set value, and the count value is set to the second set value. A timing signal generation circuit that periodically generates a timing signal by resetting the count value when
A control circuit that increases or decreases the frequency of the modulation clock signal in a predetermined modulation period in response to the timing signal generated by the timing signal generation circuit;
A semiconductor integrated circuit device comprising: A delay circuit that outputs a multiphase clock signal having a plurality of different phases based on a clock signal having a predetermined frequency;
A clock stop detection circuit that outputs a reset signal for resetting the timing signal generation circuit when generation of the modulation clock signal by the modulation clock generation circuit is stopped;
Including
The modulation clock generation circuit generates the modulation clock signal having a modulated frequency by selecting one of multiphase clock signals output from the delay circuit according to a selection signal. Semiconductor integrated circuit device. A clock signal to a semi-conductor integrated circuit device you frequency modulation,
A delay circuit that outputs a multiphase clock signal having a plurality of different phases based on a clock signal having a predetermined frequency;
A selection circuit that generates a modulated clock signal having a modulated frequency by selecting one of the multiphase clock signals output from the delay circuit according to the selection signal;
A clock stop detection circuit that outputs a reset signal when generation of a modulation clock signal by the selection circuit stops;
Timing signal generation that generates a timing signal periodically by counting the number of pulses that are reset by the reset signal output from the clock stop detection circuit and included in the modulation clock signal generated by the selection circuit Circuit,
A control circuit for generating the selection signal so as to increase or decrease the frequency of the modulation clock signal in a predetermined modulation period in response to the timing signal generated by the timing signal generation circuit;
An input terminal for inputting a cycle setting signal;
Equipped with,
The timing signal generation circuit sets a period for generating a timing signal according to a period setting signal input to the input terminal,
The control circuit sets a modulation period for increasing or decreasing the frequency of the modulation clock signal in accordance with a period setting signal input to the input terminal;
Semiconductor integrated circuit device.   An electronic apparatus comprising the semiconductor integrated circuit device according to claim 1.

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