KR20090074511A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
KR20090074511A
KR20090074511A KR1020080000320A KR20080000320A KR20090074511A KR 20090074511 A KR20090074511 A KR 20090074511A KR 1020080000320 A KR1020080000320 A KR 1020080000320A KR 20080000320 A KR20080000320 A KR 20080000320A KR 20090074511 A KR20090074511 A KR 20090074511A
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South Korea
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insulating film
forming
film
metal film
semiconductor device
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KR1020080000320A
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Korean (ko)
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김성준
박형순
신종한
박점용
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주식회사 하이닉스반도체
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Priority to KR1020080000320A priority Critical patent/KR20090074511A/en
Publication of KR20090074511A publication Critical patent/KR20090074511A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means

Abstract

A method for manufacturing a semiconductor device is provided to selectively form an insulating layer on a chemically and mechanically polished metal film in order to suppress the diffused reflection caused by a metal film residue. A method for manufacturing a semiconductor device comprises the following steps of: forming an interlayer insulating layer(102) having a wiring formation region on a semiconductor substrate; forming a metal film(106) to pad the wiring formation region; and chemically mechanically polishing the metal film in order to expose the interlayer insulating layer. An insulating layer(108a) is selectively formed on the metal film. A test is performed to determine whether a minute bridge is generated on the semiconductor substrate.

Description

반도체 소자의 제조방법{METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}

본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, CMP(Chemical Mechanical Polishing)후에 발생된 미세 브리지(Bridge) 검사 공정의 정확도를 개선하여 제조 수율을 향상시킬 수 있는 반도체 소자의 제조방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of improving the manufacturing yield by improving the accuracy of a microbridge inspection process generated after chemical mechanical polishing (CMP). It is about.

일반적으로, 반도체 소자에는 소자와 소자 간, 또는, 배선과 배선 간을 전기적으로 연결하기 위해 금속배선이 형성되며, 상부 금속배선과 하부 금속배선 간의 연결을 위해 콘택 플러그가 형성된다.In general, a metal element is formed in the semiconductor element to electrically connect the element and the element, or the interconnection and the interconnection, and a contact plug is formed to connect the upper metal interconnection and the lower metal interconnection.

상기 금속배선의 재료로는 전기 전도도가 우수한 알루미늄(Al) 및 텅스텐(W)이 주로 이용되어 왔으며, 최근에는 상기 알루미늄 및 텅스텐보다 전기 전도도가 월등히 우수하고 저항이 낮아 고집적 고속동작 소자에서 RC 신호 지연 문제를 해결할 수 있는 구리(Cu)를 차세대 금속배선 물질로 사용하고자 하는 연구가 진행되고 있다. 그런데, 상기 구리의 경우 배선 형태로 건식 식각되는 것이 용이하지 않기 때문에, 구리로 금속배선을 형성하기 위해서는 다마신(Damascene)이라는 새로운 공정 기술이 이용된다. Aluminum (Al) and tungsten (W), which have excellent electrical conductivity, have been mainly used as the material for the metallization, and in recent years, the RC signal delay in high-integrated high-speed operation devices has much higher electrical conductivity and lower resistance than the aluminum and tungsten. Research into using copper (Cu) as a next-generation metallization material that can solve the problem is being conducted. However, since the copper is not easily etched in the form of a wiring, a new process technology called damascene is used to form metal wiring with copper.

상기 다마신 금속배선 공정은 반도체 기판 상에 형성된 층간절연막을 식각해서 다마신 패턴을 형성하고, 상기 다마신 패턴을 도전막으로 매립하여 금속배선을 형성하는 기술이며, 싱글-다마신 공정과 듀얼-다마신 공정으로 나눌 수 있다.The damascene metal interconnection process is a technique of forming a damascene pattern by etching an interlayer insulating layer formed on a semiconductor substrate, and forming the metal interconnection by embedding the damascene pattern into a conductive layer. It can be divided into damascene process.

이하에서는, 다마신 공정을 적용한 종래 기술에 따른 반도체 소자의 제조방법을 간략하게 설명하도록 한다. Hereinafter, a manufacturing method of a semiconductor device according to the related art to which the damascene process is applied will be briefly described.

먼저, 반도체 기판 상에 절연막을 형성한 후, 상기 절연막을 식각하여 배선 형성 영역을 형성한다. 상기 배선 형성 영역의 표면을 포함한 절연막 상에 확산방지막을 형성한 다음, 상기 확산방지막 상에 상기 배선 형성 영역을 매립하도록 금속막, 예컨대, 구리막을 증착한다. 상기 구리막을 CMP(Chemical Mechanical Polishing)하여 금속배선을 형성한다.First, after forming an insulating film on a semiconductor substrate, the insulating film is etched to form a wiring formation region. After forming a diffusion barrier on the insulating film including the surface of the wiring forming region, a metal film, for example, a copper film is deposited to fill the wiring forming region on the diffusion barrier. CMP (Chemical Mechanical Polishing) to form a metal wiring.

한편, 상기 CMP 공정 후에 절연막 및 금속막의 표면에 스크래치(Scratch)나 파티클(Particle) 등이 잔류되거나, CMP 공정이 충분한 시간 동안 수행되지 않으면 상기 금속배선 간에 미세 브리지(Bridge)가 발생한다. 이러한 미세 브리지는 도전 패턴들 간의 쇼트(Short)를 유발하여 소자 특성 저하를 야기한다. 그러므로, 상기 CMP 공정 후에 미세 브리지의 발생 여부를 판별하기 위한 검사 공정이 필요하다.Meanwhile, scratches or particles remain on the surfaces of the insulating film and the metal film after the CMP process, or when the CMP process is not performed for a sufficient time, fine bridges are generated between the metal wires. Such fine bridges cause shorts between conductive patterns, leading to deterioration of device characteristics. Therefore, an inspection process for determining whether a fine bridge is generated after the CMP process is required.

그러나, 전술한 종래 기술의 경우에는 상기 CMP 공정 후에 잔류된 금속막 찌꺼기나 구리막 성분들에 의해 난반사가 유발되어 상기 검사 공정을 제대로 진행할 수 없으며, 그 결과, 상기 검사 공정을 통해 미세 브리지의 발생 여부를 정확하게 판별할 수 없다. 이에 따라, 반도체 소자의 불량률이 증가하여 제조 수율이 저하된다.However, in the above-described prior art, diffused reflection is caused by metal film residue or copper film components remaining after the CMP process, so that the inspection process cannot be performed properly. As a result, fine bridge is generated through the inspection process. It can't be determined accurately. Thereby, the defective rate of a semiconductor element increases and manufacturing yield falls.

본 발명은 CMP(Chemical Mechanical Polishing)후에 발생된 미세 브리지(Bridge) 검사 공정의 정확도를 개선할 수 있는 반도체 소자의 제조방법을 제공한다.The present invention provides a method for manufacturing a semiconductor device that can improve the accuracy of the inspection process of the bridge generated after CMP (Chemical Mechanical Polishing).

또한, 본 발명은 반도체 소자의 불량률을 감소시켜 제조 수율을 향상시킬 수 있는 반도체 소자의 제조방법을 제공한다.In addition, the present invention provides a method for manufacturing a semiconductor device that can improve the manufacturing yield by reducing the defective rate of the semiconductor device.

본 발명의 실시예에 따른 반도체 소자의 제조방법은, 반도체 기판 상에 배선 형성 영역을 갖는 층간절연막을 형성하는 단계; 상기 배선 형성 영역을 매립하도록 금속막을 형성하는 단계; 상기 금속막을 상기 층간절연막이 노출되도록 CMP하는 단계; 상기 금속막 상에 선택적으로 절연막을 형성하는 단계; 및 상기 절연막이 형성된 반도체 기판에 대해 미세 브리지 발생 여부를 판별하기 위한 검사 공정을 수행하는 단계;를 포함한다.A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming an interlayer insulating film having a wiring formation region on a semiconductor substrate; Forming a metal film to fill the wiring forming region; CMP the metal film to expose the interlayer insulating film; Selectively forming an insulating film on the metal film; And performing an inspection process for determining whether a fine bridge is generated on the semiconductor substrate on which the insulating film is formed.

상기 배선 형성 영역을 갖는 층간절연막을 형성하는 단계 후, 그리고, 상기 배선 형성 영역을 매립하도록 금속막을 형성하는 단계 전, 상기 배선 형성 영역을 포함한 층간절연막 상에 상기 층간절연막의 표면을 따라 확산방지막을 형성하는 단계;를 더 포함한다.After forming the interlayer insulating film having the wiring forming region, and before forming the metal film to fill the wiring forming region, spreading the diffusion barrier along the surface of the interlayer insulating film on the interlayer insulating film including the wiring forming region. Forming; It further comprises.

상기 금속막은 구리막을 포함한다.The metal film includes a copper film.

상기 금속막 상에 선택적으로 절연막을 형성하는 단계는, 상기 CMP된 금속막 및 층간절연막 상에 절연막을 형성하는 단계; 상기 절연막 상에 배선 형성 영역을 가리는 감광막 패턴을 형성하는 단계; 상기 감광막 패턴에 의해 노출된 절연막 부분을 선택적으로 식각하는 단계; 및 상기 감광막 패턴을 제거하는 단계;를 포함한다.Selectively forming an insulating film on the metal film, forming an insulating film on the CMP metal film and the interlayer insulating film; Forming a photoresist pattern covering the wiring formation region on the insulating layer; Selectively etching the insulating film portion exposed by the photosensitive film pattern; And removing the photoresist pattern.

상기 절연막은 50∼500Å의 두께를 갖도록 형성한다.The insulating film is formed to have a thickness of 50 to 500 kPa.

본 발명은 금속막의 CMP(Chemical Mechanical Polishing)가 수행된 반도체 기판의 상기 금속막 상에만 선택적으로 절연막을 형성함으로써, 상기 CMP후에 잔류된 금속막 찌꺼기나 구리막 성분들에 의해 난반사가 유발되는 것을 방지할 수 있으며, 이에 따라, 미세 브리지의 발생 여부를 판별하기 위한 검사 공정의 정확도를 개선할 수 있다.The present invention selectively forms an insulating film only on the metal film of the semiconductor substrate subjected to CMP (Chemical Mechanical Polishing) of the metal film, thereby preventing the diffuse reflection caused by the metal film residue or copper film components remaining after the CMP. In this way, it is possible to improve the accuracy of the inspection process for determining whether the fine bridge is generated.

또한, 본 발명은 반도체 소자의 불량률이 감소시켜 제조 수율을 향상시킬 수 있다.In addition, the present invention can reduce the defective rate of the semiconductor device to improve the manufacturing yield.

이하에서는 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

도 1a 내지 도 1f는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도이다.1A to 1F are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

도 1a를 참조하면, 소정의 하부 구조물(도시안됨)이 형성된 반도체 기판(100) 상에 상기 하부 구조물을 덮도록 층간절연막(102)을 형성한다. 상기 층간 절연막(102)을 식각하여 배선 형성 영역(D)을 형성한다. 상기 배선 형성 영역(D)은 싱글 다마신 공정 또는 듀얼 다마신 공정에 따라 트렌치 구조, 또는, 트렌치 및 상기 트렌치와 연결되는 적어도 하나 이상의 비아홀을 포함하는 트렌치 및 비아홀 구조로 형성할 수 있다.Referring to FIG. 1A, an interlayer insulating layer 102 is formed on a semiconductor substrate 100 on which a predetermined lower structure (not shown) is formed to cover the lower structure. The interlayer insulating layer 102 is etched to form a wiring forming region D. The wiring forming region D may be formed in a trench structure or a trench and via hole structure including a trench and at least one via hole connected to the trench according to a single damascene process or a dual damascene process.

도 1b를 참조하면, 상기 배선 형성 영역(D)의 표면을 포함한 층간절연막(102) 상에 상기 층간절연막(102)의 표면을 따라 확산방지막(104)을 형성한다. 상기 확산방지막(104)은, 예컨대, 금속막으로 형성한다. 상기 확산방지막 상에 씨드막(도시안됨)을 형성하는 것도 가능하며, 이때, 상기 씨드막은, 바람직하게, 구리막으로 형성한다. 상기 확산방지막(104) 상에 상기 배선 형성 영역(D)을 매립하도록 금속막(106)을 형성한다. 상기 금속막(106)은, 바람직하게, 구리막으로 형성하며, 상기 구리막은, 예컨데, 전기화학 도금 방식으로 형성한다.Referring to FIG. 1B, a diffusion barrier film 104 is formed along the surface of the interlayer insulating film 102 on the interlayer insulating film 102 including the surface of the wiring formation region D. Referring to FIG. The diffusion barrier film 104 is formed of, for example, a metal film. It is also possible to form a seed film (not shown) on the diffusion barrier, wherein the seed film is preferably formed of a copper film. A metal film 106 is formed on the diffusion barrier film 104 to fill the wiring forming region D. The metal film 106 is preferably formed of a copper film, and the copper film is formed by, for example, an electrochemical plating method.

도 1c를 참조하면, 상기 금속막(106)의 표면이 평탄화되도록 CMP(Chemical Mechanical Polishing)한다. 상기 CMP는 상기 확산방지막(104)이 노출되도록 수행함이 바람직하다. 이때, 상기 CMP 후에, 반도체 기판(100)의 미세 패턴 사이에 금속막의 찌꺼기나 구리막 성분과 같은 잔류물(106)이 잔류된다.Referring to FIG. 1C, chemical mechanical polishing (CMP) is performed to planarize the surface of the metal layer 106. The CMP is preferably performed so that the diffusion barrier 104 is exposed. At this time, after the CMP, residues 106 such as metal film residue or copper film components remain between the fine patterns of the semiconductor substrate 100.

도 1d를 참조하면, 상기 금속막(106)과 잔류물(106a) 및 층간절연막(102) 상에 절연막(108)을 형성한다. 상기 절연막(108)은 50∼500Å의 두께, 바람직하게, 100∼200Å의 두께를 갖도록 형성한다. 상기 절연막(108) 상에 감광막을 형성한 다음, 미세 패턴용 레티클을 사용하는 포토(Photo) 공정을 수행하여 상기 배선 형성 영역(D)을 가리는 감광막 패턴(110)을 형성한다.Referring to FIG. 1D, an insulating film 108 is formed on the metal film 106, the residue 106a, and the interlayer insulating film 102. The insulating film 108 is formed to have a thickness of 50 to 500 kPa, preferably 100 to 200 kPa. After the photoresist layer is formed on the insulating layer 108, a photo process using a reticle for a fine pattern is performed to form the photoresist pattern 110 covering the wiring formation region D.

도 1e를 참조하면, 상기 감광막 패턴에 의해 노출된 절연막(108) 부분을 선택적으로 식각하여 상기 금속막(106) 상에 절연막 패턴(108a)을 형성한다. 상기 감광막 패턴을 제거한다. Referring to FIG. 1E, a portion of the insulating film 108 exposed by the photosensitive film pattern is selectively etched to form an insulating film pattern 108a on the metal film 106. The photosensitive film pattern is removed.

도 1f를 참조하면, 상기 절연막이 형성된 반도체 기판에 대해 미세 브리지 발생 여부를 판별하기 위한 검사 공정을 수행한다. 이때, 상기 검사 공정은 상기 금속막 상에 선택적으로 절연막이 형성된 상태에서 수행되므로, 상기 검사 공정시 금속막의 찌꺼기나 구리막 성분과 같은 잔류물(106)로 인해 발생되는 난반사를 방지할 수 있다.Referring to FIG. 1F, an inspection process for determining whether a fine bridge is generated is performed on the semiconductor substrate on which the insulating layer is formed. In this case, since the inspection process is performed in a state where an insulating film is selectively formed on the metal film, it is possible to prevent diffuse reflection caused by residue 106 such as residues or copper film components of the metal film during the inspection process.

이후, 도시하지는 않았지만 공지된 일련의 후속 공정들을 차례로 수행하여 본 발명의 실시예에 따른 반도체 소자의 제조를 완성한다.Thereafter, although not shown, a series of subsequent known processes are sequentially performed to complete the manufacture of the semiconductor device according to the embodiment of the present invention.

여기서, 본 발명은 금속막 상에 선택적으로 절연막을 형성함으로써, 미세 브리지의 발생 여부를 판별하기 위한 검사 공정시 금속막의 찌꺼기나 구리막 성분에 의한 난반사를 방지할 수 있으며, 이를 통해, 상기 검사 공정시 정확도를 개선하여 미세 브리지의 발생 여부를 정확하게 판별할 수 있다.Here, the present invention can selectively prevent the reflection by the metal film residues and copper film components during the inspection process for determining whether the fine bridge is generated by selectively forming an insulating film on the metal film, through this, the inspection process Accuracy can be improved to accurately determine whether a fine bridge has occurred.

따라서, 본 발명은 상기 미세 브리지에 의해 유발되는 도전 패턴들 간의 쇼트(Short)를 방지하여 소자 특성을 개선할 수 있으며, 또한, 반도체 소자의 불량률을 감소시켜 제조 수율을 향상시킬 수 있다.Therefore, the present invention can improve device characteristics by preventing short between conductive patterns caused by the fine bridge, and also improve manufacturing yield by reducing defect rates of semiconductor devices.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

도 1a 내지 도 1f는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도.1A to 1F are cross-sectional views of processes for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

100 : 반도체 기판 102 : 층간절연막100 semiconductor substrate 102 interlayer insulating film

D : 배선 형성 영역 104 : 확산방지막D: wiring formation region 104: diffusion barrier

106 : 금속막 106a : 잔류물106 metal film 106a residue

108 : 절연막 110 : 감광막 패턴108: insulating film 110: photosensitive film pattern

Claims (5)

반도체 기판 상에 배선 형성 영역을 갖는 층간절연막을 형성하는 단계; Forming an interlayer insulating film having a wiring formation region on the semiconductor substrate; 상기 배선 형성 영역을 매립하도록 금속막을 형성하는 단계; Forming a metal film to fill the wiring forming region; 상기 금속막을 상기 층간절연막이 노출되도록 CMP하는 단계; CMP the metal film to expose the interlayer insulating film; 상기 금속막 상에 선택적으로 절연막을 형성하는 단계; 및Selectively forming an insulating film on the metal film; And 상기 절연막이 형성된 반도체 기판에 대해 미세 브리지 발생 여부를 판별하기 위한 검사 공정을 수행하는 단계;Performing an inspection process for determining whether a fine bridge is generated on the semiconductor substrate on which the insulating film is formed; 를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서, The method of claim 1, 상기 배선 형성 영역을 갖는 층간절연막을 형성하는 단계 후, 그리고, 상기 배선 형성 영역을 매립하도록 금속막을 형성하는 단계 전, After the step of forming the interlayer insulating film having the wiring forming region and before the forming of the metal film to fill the wiring forming region, 상기 배선 형성 영역을 포함한 층간절연막 상에 상기 층간절연막의 표면을 따라 확산방지막을 형성하는 단계;Forming a diffusion barrier along the surface of the interlayer insulating film on the interlayer insulating film including the wiring forming region; 를 더 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device further comprising. 제 1 항에 있어서, The method of claim 1, 상기 금속막은 구리막을 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.The metal film is a manufacturing method of a semiconductor device, characterized in that the copper film. 제 1 항에 있어서, The method of claim 1, 상기 금속막 상에 선택적으로 절연막을 형성하는 단계는, Selectively forming an insulating film on the metal film, 상기 CMP된 금속막 및 층간절연막 상에 절연막을 형성하는 단계; Forming an insulating film on the CMP metal film and the interlayer insulating film; 상기 절연막 상에 배선 형성 영역을 가리는 감광막 패턴을 형성하는 단계; Forming a photoresist pattern covering the wiring formation region on the insulating layer; 상기 감광막 패턴에 의해 노출된 절연막 부분을 선택적으로 식각하는 단계; 및 Selectively etching the insulating film portion exposed by the photosensitive film pattern; And 상기 감광막 패턴을 제거하는 단계;Removing the photoresist pattern; 를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서, The method of claim 1, 상기 절연막은 50∼500Å의 두께를 갖도록 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.And the insulating film is formed to have a thickness of 50 to 500 kV.
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