KR20090073538A - Model equivalent circuit of phase change memory device - Google Patents

Abstract

A spice modeling equivalent circuit of the phase change memory device is provided to effectively process the operation margin in the read mode and the write mode. A phase change detection unit detects the phase change of the phase change resistance device based on the set of reset condition in advance according to the input power source which is applied to the phase change resistance device, and outputs the reset control signal(PCD_RESET). The resistance selection driving unit differently sets up the equivalent resistance between the top electrode(TE) of the phase change resistance device and the bottom electrode(BE) according to the reset control signal and the mode selection signal(MS). The resistance selection driving unit differently sets up the set resistance and the reset resistance at the read mode.

Description

Model equivalent circuit of phase change memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a model equivalent circuit of a phase change memory device, and is a technique for implementing a spice modeling equivalent circuit required for implementing a simulation of a phase change memory device.

In general, nonvolatile memories such as magnetic memory and phase change memory (PCM) have data processing speeds of about volatile random access memory (RAM) and preserve data even when the power is turned off. Has the property of being.

1A and 1B are diagrams for explaining a conventional phase change resistor (PCR) element 4.

When the phase change resistance element 4 applies a voltage and a current by inserting a phase change material (PCM) 2 between the top electrode 1 and the bottom electrode 3, a phase is applied. The high temperature is induced in the change layer 2 to change the electrical conduction state due to the change in resistance.

Here, AglnSbTe is mainly used as the material of the phase change layer 2. The phase change layer 2 uses a chalcogenide (chalcogenide) as a main component of a chalcogen element (S, Se, Te), specifically, a germanium antimony tellurium alloy material composed of Ge-Sb-Te ( Ge2Sb2Te5) is used.

2A and 2B are diagrams for explaining the principle of a conventional phase change resistance element.

As shown in FIG. 2A, when a low current of less than or equal to a threshold flows through the phase change resistance element 4, the phase change layer 2 is at a temperature suitable for crystallization. As a result, the phase change layer 2 is in a crystalline phase to become a material having a low resistance state.

On the other hand, as shown in FIG. 2B, when a high current of more than a threshold flows through the phase change resistance element 4, the temperature of the phase change layer 2 becomes higher than the melting point. As a result, the phase change layer 2 is in an amorphous state and becomes a material of a high resistance state.

As described above, the phase change resistive element 4 can non-volatilely store data corresponding to the states of the two resistors. That is, when the phase change resistance element 4 is in the low resistance state, the data is "1", and in the high resistance state is the data "0", the logic state of the two data can be stored.

3 is a view for explaining a write operation of a conventional phase change resistance cell.

When a current flows between the top electrode 1 and the bottom electrode 3 of the phase change resistance element 4 for a predetermined time, high heat is generated. Thereby, the state of the phase change layer 2 changes into a crystalline phase and an amorphous phase by the temperature state applied to the top electrode 1 and the bottom electrode 3.

At this time, when a low current flows for a predetermined time, a crystal phase is formed by a low temperature heating state, and the phase change resistance element 4, which is a low resistance element, is set. On the contrary, when a high current flows for a predetermined time, an amorphous phase is formed by a high temperature heating state, and the phase change resistance element 4, which is a high resistance element, is reset. Thus, these two phase differences are represented by electrical resistance change.

Accordingly, a low voltage is applied to the phase change resistance element 4 for a long time to write the set state in the write operation mode. On the other hand, in the write operation mode, a high voltage is applied to the phase change resistance element 4 for a short time to write the reset state.

The present invention implements a spice modeling equivalent circuit required to implement simulation in a phase change memory device and sets independent resistance states in read mode and write mode, thereby operating margin in read mode and operation in write mode. The purpose is to make margins available.

In the model equivalent circuit of the phase change memory device of the present invention for achieving the above object, an input power source equivalent to a power source applied to a phase change resistance element is applied, and the phase equivalent memory is based on a preset set and reset state condition. Phase change detection means for detecting a phase change of the change resistance element and outputting a reset control signal; And resistance selection driving means for differently setting the resistance applied between the top electrode and the bottom electrode of the phase change resistance element in the read mode and the write mode according to the reset control signal and the mode selection signal.

The present invention implements a spice modeling equivalent circuit required to implement simulation in a phase change memory device and sets independent resistance states in read mode and write mode, thereby operating margin in read mode and operation in write mode. It provides the effect of effectively processing margins.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

4 is a diagram for describing an operating characteristic of a model equivalent circuit of the phase change memory device according to the present invention.

The region (C) of FIG. 4 corresponds to a lead region because the level of the current I is small, and corresponds to a region capable of reading data in a set state or data in a reset state. Here, the voltage Vh corresponds to a reference parameter for calculating the write resistance and corresponds to a reference value for determining the resistance that changes according to the change of the device voltage and the current. For example, when the voltage Vh is set to a large voltage, the write resistance value becomes small, and when the voltage Vh is set to be close to a small voltage, that is, zero, the write resistance value becomes large.

In the lead region C, no current flows when the device voltage V is less than or equal to the snapback voltage Vth. And, when the device voltage (V) becomes the snap back voltage Vth or more current begins to flow.

In addition, the current I / Ireset is applied to determine the current I under the same standard value based on the reset current Ireset even under different cell sizes.

In addition, region (D) of FIG. 4 corresponds to a region of a SET current regime, and region (E) corresponds to a region of a reset current regime.

In the graph of FIG. 4, the parameters of the device voltage and the current I are illustrated in consideration of the time domain and the slope condition.

The basic parameters of the phase change resistance element reflected in the Spice modeling of the present invention may be divided into three types as follows.

First, the set and reset resistors in the read mode.

Secondly, the reset resistor before the snapback phenomenon in the light mode.

Third, the resistance setting of the phase change resistance element in the write heating mode after the snap back phenomenon in the light mode.

Here, the set state resistance in the read mode is set to 20 Kohm, and the reset state resistance is set to 100 Kohm. And, the set state resistance in the light mode starts at 1Kohm. In addition, the reset state resistance in the write mode starts at 200Kohm in the voltage state before the snap back mode, and implements a model equivalent circuit that can set the phase change resistance state to 1Kohm in the light heating period.

As described above, the present invention sets the independent resistance states in the read mode and the write mode so that the operation margin in the read mode and the operation margin in the write mode can be effectively processed.

5 is a circuit diagram of a resistance selection driving means in a model equivalent circuit of a phase change memory device according to the present invention.

The resistance selection driving means of the present invention includes a lead resistance selection unit 100, a write resistance selection unit 110, a snap back detection unit 120, and a snap back adjustment unit 130.

The lead resistance selector 100 includes resistors R1 and R2 and switches SW1 and SW2 and AND gates AND1 and AND2. In the phase change memory device, when the top electrode of the phase change resistance element PCR is defined as "TE" and the bottom electrode is defined as "BE", an input signal input is applied between the top electrode TE node and the bottom electrode BE node.

The resistor R1 and the switch SW1 are connected in series between the top electrode TE node and the bottom electrode BE node. The resistor R2 and the switch SW2 are connected in series between the top electrode TE node and the bottom electrode BE node.

Here, the resistance value of the resistor R1 is preferably set to 20 Kohm. The resistance value of the resistor R2 is preferably set to 100 Kohm.

The switch SW1 is controlled by the set read signal sw_set_read which is an output of the AND gate AND1. The switch SW2 controls the switching operation by the reset read signal sw_reset_read which is the output of the AND gate AND2.

The AND gate AND1 performs an AND operation on the mode selection signal MS and the set control signal PCD_SET. Here, the mode selection signal MS is a signal input at the high level in the read mode and at the low level in the write mode.

The AND gate AND2 performs an AND operation on the mode selection signal MS and the reset control signal PCD_RESET. Here, the set control signal PCD_SET is a signal in which the reset control signal PCD_RESET is inverted by the inverter IV3. The reset control signal PCD_RESET is a signal input at a high level when the phase change resistance element PCR is in a reset state and at a low level in the set state.

The write resistance selector 110 includes resistors R3 to R5, switches SW3 to SW5, and AND gates AND3 and AND4. The resistor R3 and the switch SW3 are connected in series between the top electrode TE node and the bottom electrode BE node. The resistor R4 and the switch SW4 are connected in series between the top electrode TE node and the bottom electrode BE node. The resistor R5 is connected between the top electrode TE node and the switch SW5.

Here, the resistance value of the resistor R3 is preferably set to 1 Kohm. The resistance value of the resistor R4 is preferably set to 200 Kohm. In addition, the resistance value of the resistor R5 is preferably set to 1 Kohm.

The switch SW3 is controlled by the set write signal sw_set_write which is an output of the AND gate AND3. The switch SW4 controls the switching operation by the reset write signal sw_reset_write which is the output of the AND gate AND4. In addition, the switch SW5 is connected between the resistor R5 and the switch SW4 so that the switching operation is controlled by the snap back signal SB.

The AND gate AND3 performs an AND operation on the write enable signal WE and the set control signal PCD_SET. The AND gate AND4 performs an AND operation on the write enable signal WE and the reset control signal PCD_RESET. Here, the write enable signal WE is a signal in which the mode selection signal MS is inverted by the inverter IV2.

In addition, the snap back detector 120 includes an amplifier A1 and a threshold voltage detection means VD1. In the amplifier A1, a positive (+) terminal is connected to the top electrode TE node, and a negative (-) terminal is connected to the threshold voltage sensing means VD1. The amplifier A1 compares and amplifies the output of the top electrode TE node and the threshold voltage Vth of the threshold voltage sensing means VD1 to output the snapback detection signal SB_DET.

That is, the snapback detector 120 sets the threshold voltage Vth which is a snapback voltage based on the bottom electrode BE node. The amplifier A1 compares the voltage difference between the top electrode TE node and the bottom electrode BE node, and outputs the snapback detection signal SB_DET at a high voltage level when the threshold voltage Vth is exceeded.

The snap back adjustment unit 130 includes an inverter IV1 and a noah gate NOR1 and NOR2 having a latch structure. Here, the NOR gate NOR1 performs a NO operation on the snap back detection signal SB_DET and the output of the NOR gate NOR2. The NOR gate NOR2 performs a NO operation on the output of the NOR gate NOR1, the set control signal PCD_SET, and the mode selection signal MS. Inverter IV1 inverts the output of NOR gate NOR1 and outputs a snapback signal SB.

6 is a circuit diagram of a phase change detecting means in a model equivalent circuit of the phase change memory device according to the present invention.

The phase change detection means of the present invention includes an input power supply equivalent IP, resistors R6 and R7, integrators 200 and 210, threshold voltage detection means VD2 to VD4, amplifiers A3, A4, A6, and AND AND5, and a set. A power supply equivalent SET_P and latch means 230.

Here, the input power source equivalent part IP represents an input power source equivalent to the power applied between the top electrode TE node and the bottom electrode BE node of the phase change resistance element PCR. Resistor R6 is connected between the power input terminal Powerin and the power terminal power. Resistor R6 corresponds to a variable resistor for matching the output of node Temp with the threshold voltage Tm.

The integrator 200 includes a capacitor C1 and an amplifier A2. Here, the capacitor C1 is connected between the power supply terminal Power and the node Temp. In the amplifier A2, the negative terminal is connected to the node power, and the positive terminal is connected to the ground voltage terminal. The amplifier A2 compares and amplifies the output of the node power and the voltage of the ground voltage terminal and outputs the result to the node temp.

The amplifier A3 has a negative terminal connected to the threshold voltage detecting means VD2, and a positive terminal connected to the node Temp. The amplifier A3 compares and amplifies the output of the node Temp and the output of the threshold voltage sensing means VD2 and outputs the result to the node Vm.

That is, the amplifier A3 sets the threshold voltage Tm based on the ground voltage terminal. The amplifier A3 compares the voltage difference between the node Temp and the ground voltage terminal, and outputs the node Vm at a high voltage level when the threshold voltage Tm is exceeded.

In the amplifier A4, the negative terminal is connected to the threshold voltage detecting means VD3, and the positive terminal is connected to the node Temp. The amplifier A4 compares and amplifies the output of the node Temp and the output of the threshold voltage sensing means VD3 and outputs the result to the node Time1.

Then, resistor R7 is connected between node Time1 and node Time2. Resistor R7 corresponds to a variable resistor to adjust the pulse width at the output of node Temp1.

That is, the amplifier A4 sets the threshold voltage Tx based on the ground voltage terminal. The amplifier A4 compares the voltage difference between the node Temp and the ground voltage terminal, and outputs the node Time1 at a high voltage level when the threshold voltage Tx is exceeded. Here, the threshold voltage Tm preferably has a level higher than the threshold voltage Tx.

Integrator 210 also includes capacitor C2, amplifier A5, and switch SW6. Here, capacitor C2 is connected between node Time2 and node SET_T. In the amplifier A5, a negative terminal is connected to the node Time2, and a positive terminal is connected to the ground voltage terminal.

The amplifier A5 compares and amplifies the voltages of the node Time2 and the ground voltage terminal and outputs them to the node SET_T. The switch SW6 is connected between the node Time2 and the node SET_T so that the switching operation is selectively controlled according to the voltage of the node Vm. That is, when the output of the node Vx becomes high, the switch SW6 is turned on so that the integrator 210 operates. When the switch SW6 is turned on, it operates according to the reset condition except for the set condition.

The set power supply equivalent unit SET_P indicates a set power supply that is equivalent to the power applied when the set (SET) data is written. That is, when the output of the node SET_T becomes high, the set power supply equivalent SET_P increases in current, and the voltage of the node Cx increases.

In the amplifier A6, the negative terminal is connected to the threshold voltage detecting means VD4, and the positive terminal is connected to the node Cx. The amplifier A6 compares and amplifies the output of the node CT and the output of the node Cx and outputs the result to the node nCrystal. That is, when the voltage level of the node Cx becomes higher than the node CT, the node nCrystal becomes a high voltage level. The AND gate AND5 performs an AND operation on the outputs of the node Time1 and the node nCrystal and outputs the result to the node Vx.

That is, the amplifier A6 sets the threshold voltage CT based on the ground voltage terminal. The amplifier A6 compares the voltage difference between the node Cx and the ground voltage terminal, and outputs the node cCrystal at a high voltage level when the threshold voltage CT is exceeded.

The latch means 230 comprises the noah gates NOR3, NOR4 of the latch structure, the noah gate NOR5, and the inverter IV4. Here, the NOR gate NOR3 performs a NO operation on the output of the node Vm and the output of the NOA gate NOR4 and outputs the result to the NOA gate NOR4. The NOA gate NOR4 performs a NO operation on the output of the NOA gate NOR3 and the output of the NOA gate NOR5, and outputs a reset control signal PCD_RESET. Noah gate NOR5 nodes the output of node Vm and the output of node Vx inverted by inverter IV4.

That is, the reset control signal PCD_RESET is output at the high level during the write operation of the reset data and is output at the low level during the write operation of the set data. In addition, the latch unit 230 maintains the state when the node Vm maintains the high voltage level even when the power is turned off. When the input state of the node Vx is changed, the state of the reset control signal PCD_RESET is changed.

The operation of the phase change detecting means having such a configuration will be described with reference to the operation timing diagram of FIG. In the operation timing diagram of FIG. 7, odd sections t1, t3, t5, t7, and t9 correspond to write sections, and even sections t0, t2, t4, t6, t8, and t10 correspond to read sections.

The phase change detecting means is a circuit for determining whether the phase change resistance element PCR is in the set write state or the reset write state in the write mode.

That is, the threshold voltage required for the write operation of the set data is applied through the input power equivalent IP. Thereafter, after a predetermined time has elapsed, it is set to a set state and the reset control signal PCD_RESET is output at a low voltage level.

On the other hand, the threshold voltage required for the write operation of the reset data is applied through the input power equivalent IP. Thereafter, after a predetermined time has elapsed, it is set to a reset state and the reset control signal PCD_RESET is output at a high voltage level.

First, in the read period t0, the input voltage input is not applied between the top electrode TE node and the bottom electrode BE node to maintain a low voltage level. Accordingly, the mode selection signals MS, the nodes Temp, Cx, Vm, and Vx maintain the low voltage level, and the reset control signal PCD_RESET is output at the low voltage level.

Subsequently, in the write period t1, the input voltage input transitions to the reset voltage level between the top electrode TE node and the bottom electrode BE node. At this time, the mode selection signal MS maintains a low voltage level. The integrator 200 then causes the output of the node Temp to reach a high voltage level.

Here, the voltage level of the node Temp represents the heating temperature of the phase change resistance element PCR in the write period. In the t1 section, the input voltage input is applied at a high reset voltage level, thereby increasing the voltage level of the node Temp indicating the heating temperature. That is, when the voltage level of the input power equivalent IP is high, the voltage level of the output node Temp of the integrator 200 becomes high.

Further, the nodes Cx and Vx become the low voltage level, the node Vm becomes the high voltage level, and the reset control signal PCD_RESET is output at the high voltage level. Here, the voltage level of the node Cx represents the degree of crystallization over time at the set temperature.

That is, the voltage level of the node Cx changes according to the voltage level of the set power supply equivalent part SET_P. Accordingly, the voltage level of the node Cx is maintained at the high level in the read period or in the write period (eg, t3, t5) where the reset voltage is applied at a low level.

In addition, the signal of the node Vm is a signal that transitions to a high level above the melting temperature. That is, the transition to the high voltage level in the light section (for example, t1, t7) to which the reset voltage level above the melting point temperature is applied.

Further, the signal of the node Vx is a signal that is activated after the target crystallization state. That is, the signal of the node Vx transitions to the high voltage level when the output of the node Time1 and the output of the node nCrystal are applied at the high voltage level.

Subsequently, in the read period t2, the input voltage input transitions to the set voltage level between the top electrode TE node and the bottom electrode BE node. At this time, the mode selection signal MS maintains a high voltage level. The integrator 200 then causes the output of the node Temp to reach a low voltage level.

In addition, when the nodes Cx, Vm, and Vx become low voltage levels, the phase change resistance element PCR is in an amorphous state. Accordingly, the control signal PCD_RESET maintains the high voltage level.

Subsequently, in the write period t3, the input voltage input transitions to the reset voltage level between the top electrode TE node and the bottom electrode BE node. Here, the input voltage Input applied in the write section t3 has a lower voltage than the input voltage Input applied in the write section t1. In the period t3, the input voltage input is applied at a low reset voltage level, thereby lowering the voltage level of the node Temp indicating the heating temperature.

At this time, the mode selection signal MS maintains a low voltage level. The integrator 200 then causes the output of the node Temp to reach a high voltage level. Further, the nodes Cx and Vx become the high voltage level, the node Vm becomes the low voltage level, and the control signal PCD_RESET is output at the high voltage level.

Next, in the read period t4, the input voltage Input transitions to the set voltage level between the top electrode TE node and the bottom electrode BE node. At this time, the mode selection signal MS maintains a high voltage level. The integrator 200 then causes the output of the node Temp to reach a low voltage level. Further, the node Cx becomes the high voltage level, the nodes Vm and Vx become the low voltage level, and the control signal PCD_RESET transitions to the low voltage level.

Subsequently, in the write period t5, the input voltage input transitions to the reset voltage level between the top electrode TE node and the bottom electrode BE node. Here, the input voltage Input applied in the write section t5 has a lower voltage than the input voltage Input applied in the write section t1.

At this time, the mode selection signal MS maintains a low voltage level. The integrator 200 then causes the output of the node Temp to reach a high voltage level. Further, the nodes Cx and Vx become the high voltage level, the node Vm becomes the low voltage level, and the control signal PCD_RESET is output at the low voltage level.

Next, in the read period t6, the input voltage Input transitions to the set voltage level between the top electrode TE node and the bottom electrode BE node. At this time, the mode selection signal MS maintains a high voltage level. The integrator 200 then causes the output of the node Temp to reach a low voltage level. Further, the node Cx becomes the high voltage level, the nodes Vm and Vx become the low voltage level, and the control signal PCD_RESET transitions to the low voltage level.

Subsequently, in the write period t7, the input voltage input transitions to the reset voltage level between the top electrode TE node and the bottom electrode BE node. At this time, the mode selection signal MS maintains a low voltage level. The integrator 200 then causes the output of the node Temp to reach a high voltage level. In addition, the node Cx transitions to a low voltage level, the nodes Vm and Vx transition to a high voltage level, and the control signal PCD_RESET transitions to a high voltage level.

Subsequently, in the read period t8, the input voltage input transitions to the set voltage level between the top electrode TE node and the bottom electrode BE node. At this time, the mode selection signal MS maintains a high voltage level. The integrator 200 then causes the output of the node Temp to reach a low voltage level. Further, the nodes Cx, Vm, and Vx become low voltage levels, so that the control signal PCD_RESET maintains the high voltage level.

Subsequently, in the write period t9, the input voltage input transitions to the reset voltage level between the top electrode TE node and the bottom electrode BE node. Here, the input voltage Input applied in the write section t9 has a lower voltage than the input voltage Input applied in the write section t1.

At this time, the mode selection signal MS maintains a low voltage level. The integrator 200 then causes the output of the node Temp to reach a high voltage level. Further, the nodes Cx and Vx become the high voltage level, the node Vm becomes the low voltage level, and the control signal PCD_RESET is output at the high voltage level.

Next, in the read period t10, the input voltage Input transitions to the set voltage level between the top electrode TE node and the bottom electrode BE node. At this time, the mode selection signal MS maintains a high voltage level. The integrator 200 then causes the output of the node Temp to reach a low voltage level. Further, the node Cx becomes the high voltage level, the nodes Vm and Vx become the low voltage level, and the control signal PCD_RESET transitions to the low voltage level.

Referring to the operation of the resistance selection drive means of the present invention having such a configuration as follows.

First, the mode selection signal MS is input at the low level in the write mode. The write enable signal WE is at a high level. As a result, the inputs of the AND gates AND1 and AND2 are at a low level so that the read resistance selector 100 does not operate.

On the other hand, when the inputs of the AND gates AND3 and AND4 are at a high level, the write resistance selector 110 operates according to the set control signal PCD_SET and the reset control signal PCD_RESET.

That is, when the reset control signal PCD_RESET is input at the high level, the output of the AND gate AND4 is at the high level. Accordingly, the reset write signal sw_reset_write is activated and the switch SW4 is turned on as shown in FIG. 8. Therefore, as in the state (A) of FIG. 4, the write current flows through the resistor R4 (200 Kohm) of the light resistance selecting unit 110.

When the set control signal PCD_SET is input at a high level, the output of the AND gate AND3 is at a high level. Accordingly, the set write signal sw_set_write is activated and the switch SW3 is turned on as shown in FIG. 9. Therefore, the write current flows through the resistor R3 (1 Kohm) of the light resistance selector 110.

Here, when the reset control signal PCD_RESET is input at the high level and the mode selection signal MS is input at the low level, the snap back signal SB is output at the high level. When the snap back signal SB signal becomes high level, the switch SW5 is turned on as shown in FIG. 8. Therefore, as in the state (B) of FIG. 4, the snap back current flows through the resistor R5 (1 Kohm) of the light resistance selecting unit 110.

The snapback detector 120 sets a threshold voltage Vth which is a snapback voltage based on the bottom electrode BE terminal. Accordingly, when the voltage between the top electrode TE node and the bottom electrode BE node does not exceed the threshold voltage Vth, the snap back detection signal SB_DET is output at a low level.

At this time, even when the mode selection signal MS is at the low level and the reset control signal PCD_RESET is input at the high level, the snap back signal SB is output at the low level. Therefore, the snap back signal SB becomes low level and the switch SW5 is turned off.

On the other hand, the reset write signal sw_reset_write becomes high and the switch SW4 is turned on. Accordingly, the write current before the snap back flows through the resistor R4 (200 Kohm) of the light resistance selector 110.

As described above, in the resistance selection driving means of the present invention, activation of the read resistance selection unit 100 and the write resistance selection unit 110 is determined according to the mode selection signal MS and the reset control signal PCD_RESET.

That is, in the read mode, the mode selection signal MS becomes high level. Accordingly, the inputs of the AND gates AND3 and AND4 are at a low level, and the write resistance selector 110 does not operate.

On the other hand, when the inputs of the AND gates AND1 and AND2 are at a high level, the read resistance selector 100 operates according to the set control signal PCD_SET and the reset control signal PCD_RESET.

That is, when the reset control signal PCD_RESET is input at the high level, the output of the AND gate AND2 is at the high level. Accordingly, the reset read signal sw_reset_read is activated and the switch SW2 is turned on as shown in FIG. 10. Therefore, the read current flows through the resistor R2 (100 Kohm) of the read resistance selector 100.

When the set control signal PCD_SET is input at the high level, the output of the AND gate AND1 is at the high level. Accordingly, the set read signal sw_set_read is activated and the switch SW1 is turned on as shown in FIG. 11. Therefore, the read current flows through the resistor R1 (20 Kohm) of the read resistance selector 100.

1A and 1B are diagrams for explaining a conventional phase change resistance element.

2A and 2B are diagrams for explaining the principle of a conventional phase change resistance element.

3 is a view for explaining a write operation of a conventional phase change resistance cell.

4 is a view for explaining operating characteristics in a model equivalent circuit of a phase change memory device according to the present invention;

5 is a circuit diagram of a resistance selection driving means in a model equivalent circuit of a phase change memory device according to the present invention;

6 is a circuit diagram of a phase change detecting means in a model equivalent circuit of a phase change memory device according to the present invention;

FIG. 7 is an operation timing diagram relating to the phase change detection means of FIG. 6.

8 to 11 are diagrams for explaining the operation of the resistance selection driving means of FIG.

Claims (21)

Phase change detection means for detecting a phase change of the phase change resistance element based on a preset set and reset state condition according to input power applied to the phase change resistance element and outputting a reset control signal; And And a resistance selection driving means for setting an equivalent resistance between the top electrode and the bottom electrode of the phase change resistance element differently in the read mode and the write mode according to the reset control signal and the mode selection signal. Model equivalent circuit of the memory device. The model equivalent circuit of a phase change memory device as claimed in claim 1, wherein the resistance selection driving means sets the set resistor and the reset resistor differently in the read mode. 3. The model equivalent circuit of a phase change memory device according to claim 2, wherein the set resistance in the read mode is smaller than the reset resistance. The model equivalent circuit of a phase change memory device as claimed in claim 1, wherein the resistance selection driving means sets the set resistance before the snap back and the reset resistor and the write resistance after the snap back differently in the write mode. 5. The model equivalent circuit of claim 4, wherein the set resistor before the snap back and the write resistor have the same resistance value, and the reset resistor is larger than the set resistor. The method of claim 1, wherein the resistance selection drive means A read resistance selector configured to set a reset resistor and a set resistor differently in read mode according to the mode selection signal and the reset control signal; A write resistor selector configured to set a reset resistor and a set resistor differently in a write mode according to the mode selection signal and the reset control signal; A snap back detector configured to sense a snap back voltage applied between the top electrode and the bottom electrode; And And a snap back adjuster configured to adjust a resistance of the write resistance selector according to an output of the snapback detector and a set control signal and the mode selection signal. 7. The model equivalent circuit of claim 6, wherein the set control signal is an inverted signal of the reset control signal. The method of claim 6, wherein the lead resistance selector First logic combining means for activating a set read signal when both the mode selection signal and the set control signal are applied at a high level; Second logical combining means for activating a reset read signal when both the mode selection signal and the reset control signal are applied at a high level; First switching means for selecting a first resistor in accordance with the set read signal; And And second switching means for selecting a second resistor in accordance with said reset read signal. 9. The model equivalent circuit of claim 8, wherein the first resistor has a smaller value than the second resistor. The method of claim 6, wherein the light resistance selector Third logical combining means for activating a set write signal when both the set control signal and the write enable signal are applied at a high level; Fourth logic combining means for activating a reset write signal when both the reset control signal and the write enable signal are applied at a high level; Third switching means for selecting a third resistor according to the set write signal; Fourth switching means for selecting a fourth resistor in accordance with the reset write signal; And And a fifth switching means for selecting a fifth resistor in accordance with the output of said snap back adjustment section. The model equivalent circuit of claim 10, wherein the write enable signal is an inverted signal of the mode selection signal. The method of claim 10, wherein the write resistance selector And the fourth switching means is turned on before the snap back in the write mode of the reset data, and the fifth switching means is turned on after the snap back. The method of claim 10, wherein the write resistance selector And the third switching means is turned on in the write mode of the set data. 12. The model equivalent circuit of claim 10, wherein the third resistor is smaller than the fourth resistor and has the same resistance value as the fifth resistor. The method of claim 6, wherein the snap back detection unit First threshold voltage sensing means for sensing the snapback voltage based on the bottom electrode; And And a first amplifier for comparing and amplifying a voltage of the first threshold voltage sensing means with a voltage of the top electrode. The method of claim 6, wherein the snap back adjustment unit And first latch means for latching an output of the snap back detector according to the mode selection signal and the set control signal. The method of claim 1, wherein the phase change detecting means An input power equivalent unit to which input power equalized to power applied to the phase change resistance element is applied; A first integrator for integrating the output of the input power equivalent unit; A second amplifier for comparing and amplifying the output of the first integrator and the output of the second threshold voltage sensing means; A third amplifier for comparing and amplifying the output of the first integrator and the output of the third threshold voltage sensing means; A second integrator controlled by the output of the second amplifier and integrating the output of the third amplifier; A set power equivalent unit controlled by an output of the second integrator and configured to equalize a power applied when writing set data; A fourth amplifier for comparing and amplifying an output of the set power equivalent unit with an output of a fourth threshold voltage sensing means; Fifth logical combining means for logically combining the output of the third amplifier and the output of the fourth amplifier; And And second latch means for latching an output of said second amplifier and an output of said fifth logical combining means to output said reset control signal. 18. The apparatus of claim 17, wherein the phase change detection unit outputs the reset control signal at a high voltage level when a threshold voltage corresponding to reset data is applied to the input power equivalent unit, and outputs the set data to the input power equivalent unit. And the reset control signal is output at a low voltage level when a corresponding threshold voltage is applied. 18. The apparatus of claim 17, wherein the first integrator is A fifth amplifier for comparing and amplifying the output voltage of the input power equivalent unit and a ground voltage; And And a first capacitor connected between an input terminal and an output terminal of the fifth amplifier. 18. The apparatus of claim 17, wherein the second integrator is A sixth amplifier for comparing and amplifying the output of the third amplifier and the ground voltage; A second capacitor connected between the input terminal and the output terminal of the sixth amplifier; And And switching means connected in parallel with said second capacitor and controlled by the output of said second amplifier. 18. The model equivalent circuit of claim 17, wherein the output of the second amplifier is a signal that transitions to a high level above the melting point temperature of the phase change resistance element.

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