KR20090068753A - Array substrate of liquid crystal display device - Google Patents

Abstract

An array substrate for a liquid crystal display device is provided to improve a contact property between a source/drain metal pattern and a gate driving circuit line. A plurality of gate driving circuit lines(270) and a plurality of driving transistors correspond a gate driving unit. A source/drain metal pattern(254) is designed to be overlapped in the gate driving circuit line. A contact hole passes a part of the overlapped part of the gate driving circuit line and the source/drain metal pattern. A transparent connecting pattern(284) connects the source/drain metal pattern and the gate driving circuit line through the contact hole.

Description

Array Substrate for Liquid Crystal Display Device

The present invention relates to an array substrate for a liquid crystal display device, and more particularly, to improve reliability of a gate driving circuit in an array substrate for a liquid crystal display device in which a gate driver is embedded in the array substrate.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization property of the liquid crystal. The liquid crystal has a long and thin structure, and thus has a directivity in the arrangement of molecules. Can be controlled.

Accordingly, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, active matrix LCDs (AM-LCDs) in which thin film transistors and pixel electrodes connected to the thin film transistors are arranged in a matrix manner have attracted the most attention because of their excellent resolution and video performance.

Hereinafter, a liquid crystal display array substrate according to the related art will be described with reference to the accompanying drawings.

1 is a plan view illustrating a conventional array substrate for a liquid crystal display device.

As illustrated, the array substrate 10 for a liquid crystal display according to the related art is divided into a display area AA that implements an image and a non-display area NAA that does not implement an image.

The display area AA on the substrate 10 perpendicularly crosses the first to m-th gate lines GL1 to GLm and the first to m-th gate lines GL1 to GLm receiving scan signals in one direction. As a result, a plurality of pixel regions P are defined, and the first to n th data lines DL1 to DLn receiving the data signal are arranged in a matrix form.

A plurality of thin film transistors T, which switch one-to-one corresponding to an intersection point of the first to mth gate lines GL1 to GLm and the first to nth data lines DL1 to DLn, are configured. The pixel electrode 80 in contact with the transistor T is configured to correspond to the pixel region P in a one-to-one correspondence.

Meanwhile, the first to mth gate lines GL1 to GLm and the first to nth data lines DL1 to DLn correspond to the first to mth gate link lines GLL1 to GLLm corresponding to the non-display area NAA. And the first to nth gate pads GP1 to GPm and the first to nth data pads DP1 to DPn through the first to nth data link wirings DLL1 to DLLn, respectively.

In this case, the first to m-th gate pads GP1 to GPm and the first to n-th data pads DP1 to DPn each include a first to m-th gate pad contact hole (not shown) and a portion thereof. First to mth gate pad electrodes (not shown) and first to nth data pad electrodes (not shown) made of the same material as the pixel electrode 80 through the first to nth data pad contact holes (not shown). Respectively).

The first to m th gate pad electrodes (not shown) and the first to n th data pad electrodes (not shown) may include gate and data drivers GDA and DDA and tabs positioned on one side of the substrate 10. Tape Automated Bonding (TAB) is attached through a mounting process, and the first to m th gate pad electrodes (not shown) and the first to n th data pad electrodes (not shown) are gate and data drivers GDA and DDA. Scan and data signals from the first to m th gate lines GL1 to GLm and the first to n th data lines DL1 to DLn, respectively.

However, the liquid crystal display array substrate having the above-described configuration has a tab mounting process for attaching each drive circuit designed for such a tab gate and data driver to a separate printed circuit board through a tape carrier package. There is a problem in that the manufacturing cost is increased according to the progress.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object thereof is to improve the reliability of a gate driving circuit in an array substrate for a liquid crystal display device in which a gate driver is embedded in an array substrate.

An array substrate for a liquid crystal display device according to an embodiment of the present invention for achieving the above object is a substrate; A plurality of gate driving circuit wirings and a plurality of driving transistors corresponding to the gate driving unit formed on the substrate; A source / drain metal pattern extending from the driving transistor and overlapping the gate driving circuit wiring; A contact hole penetrating the overlapped portion of the source / drain metal pattern and the gate driving circuit wiring line; And a transparent connection pattern connecting the source / drain metal pattern and the gate driving circuit wiring through the contact hole.

The source / drain metal pattern may be formed of one selected from the group of conductive metal materials including molybdenum, molybdenum alloy, copper, and aluminum.

The gate driving circuit wiring includes a gate off voltage wiring for applying a gate off voltage, a plurality of clock signal wirings, an initialization signal wiring for transferring the plurality of clock signal wirings and an initialization signal, and the like.

The gate driving circuit wiring is made of the same material as the gate wiring, and the source and drain metal patterns are made of the same material as the data wiring. The source and drain metal patterns may be in side contact with the transparent connection pattern.

An array substrate for a liquid crystal display device according to the present invention for achieving the above object is a substrate; Gate and data lines defining pixel regions vertically intersecting on the substrate; A thin film transistor positioned at the intersection of the gate and the data line; A pixel electrode connected to the thin film transistor; A data pad configured at one end of the data line; An island pattern positioned at an upper portion overlapping the data pad; The data pad electrode penetrates the island pattern and contacts the data pad.

The island pattern is made of the same material as the gate line, and a semiconductor pattern is further formed under the island pattern. The data pad is made of the same material as the gate wiring.

First, the contact characteristics between the gate driving circuit wiring and the source / drain metal pattern can be improved.

Second, the number of contact holes for connecting the gate driving circuit wiring and the source / drain metal pattern may be reduced.

Third, process defects can be minimized by improving step coverage.

Fourth, the degree of integration of the gate driver may be improved by reducing the number of contact holes.

--- Example ---

A first embodiment of the present invention is to provide an array substrate for a liquid crystal display device which can reduce the production cost by manufacturing a gate driving circuit together in the process of forming an array element.

Hereinafter, an array substrate for a liquid crystal display device according to the present invention will be described with reference to the accompanying drawings.

2 is a plan view illustrating an array substrate for a liquid crystal display device having a gate embedded type according to a first embodiment of the present invention.

As illustrated, the array substrate 100 for a liquid crystal display according to the first exemplary embodiment of the present invention is divided into a display area AA for implementing an image and a non-display area NAA for not implementing an image.

The display area AA on the substrate 100 perpendicularly crosses the first to m-th gate lines GL1 to GLm and the first to m-th gate lines GL1 to GLm receiving scan signals in one direction. As a result, a plurality of pixel regions P are defined, and the first to n th data lines DL1 to DLn receiving the data signal are arranged in a matrix form.

A plurality of thin film transistors T, which switch one-to-one corresponding to an intersection point of the first to mth gate lines GL1 to GLm and the first to nth data lines DL1 to DLn, are configured. The plurality of pixel electrodes 180 in contact with the transistor T are configured to correspond to the pixel region P in a one-to-one correspondence.

The first to m th gate lines GL1 to GLm may be gate drivers designed on the substrate 100 through the first to m th gate link lines GLL1 to GLLm corresponding to the non-display area NAA. Scan signal from the GDA).

The first to n th data lines DL1 to DLn are connected to the first to n th data pads DP1 to DPn through the first to n th data link lines DLL1 to DLLn, respectively.

The first to n-th data pads DP1 to DPn may be formed of the same material as the pixel electrode 180 through the first to n-th data pad contact holes (not shown) that expose portions of the first to n-th data pads DP1 to DPn. The n-th data pad electrode is in contact with each other.

The first to n th data pad electrodes (not shown) are attached through a data driving circuit unit (DDA) and a tab automated bonding (TAB) mounting process positioned at one side spaced apart from the substrate 100.

That is, in the first embodiment of the present invention, the manufacturing cost can be reduced by embedding the gate driver GDA in the array substrate 100.

3 is a plan view schematically illustrating a portion A of FIG. 2. In particular, an enlarged view of a portion of the gate driver will be described in detail with reference to the drawing.

As illustrated, the gate driving circuit 160 is designed to correspond to the gate driver GDA on the substrate 100. The gate driving circuit 160 includes a plurality of gate driving circuit wiring 170 configured in one direction and a plurality of driving transistors T1, T2, T3, and T4.

Although not shown in detail in the drawings, the plurality of gate driving circuit lines 170 may include a gate-off voltage line for applying a gate-off voltage, a plurality of clock signal lines, and an initialization for transmitting the plurality of clock signal lines and initialization signals. Signal wiring and the like.

In this case, gate driving signals applied through the plurality of gate driving circuit lines 170 may be controlled on / off through the plurality of driving transistors T1, T2, T3, and T4.

FIG. 4A is an enlarged view of a portion B of FIG. 3, and FIG. 4B is a cross-sectional view taken along line IV-IV of FIG. 4A and will be described in detail with reference to this.

As shown in FIGS. 4A and 4B, the gate driving circuit wiring 170 is configured in one direction corresponding to the gate driver GDA on the substrate 100. The gate driving circuit wiring 170 is made of the same material as the first to m-th gate wirings (GL1 to GLm in FIG. 2).

The gate insulating layer 145 is formed on the upper front surface of the gate driving circuit wiring 170 as one selected from a group of inorganic insulating materials including silicon oxide (SiO ₂ ) and silicon nitride (SiNx).

The semiconductor pattern 144 and the source / drain metal pattern 154 spaced apart from the gate driving circuit wiring 170 by a predetermined distance are sequentially stacked on the gate insulating layer 145. The semiconductor pattern 144 includes a first amorphous pattern (not shown) made of pure amorphous silicon (a-Si: H) and a second amorphous pattern made of amorphous silicon (n + a-Si: H) containing impurities. (Not shown).

The semiconductor pattern 144 is formed of a semiconductor layer (not shown), and the source / drain metal pattern 154 is made of the same material as the data line (DL1 to DLn of FIG. 2). In this case, the semiconductor pattern 144 and the source / drain metal pattern 154 may be patterned using one mask process as an example.

On the upper side of the semiconductor pattern 144 and the source / drain metal pattern 154, an inorganic insulating material group including silicon oxide (SiO ₂ ) and silicon nitride (SiNx) or photo acryl and benzocyclobutene The passivation layer 155 is formed of one selected from the group of organic insulating materials including).

A passivation layer 155 corresponding to each of the gate driving circuit wiring 170 and the source / drain metal pattern 154 to expose the gate driving circuit wiring 170 and the source / drain metal pattern 154. The first to fourth contact holes CH1, CH2, CH3, and CH4 are configured.

The transparent connection pattern 184 connecting the gate driving circuit wiring 170 and the source / drain metal pattern 154 on the passivation layer 155 including the first to fourth contact holes CH1, CH2, CH3, and CH4. This is made up. The transparent connection pattern 184 is made of the same material as the pixel electrode 180 of FIG. 2.

In general, when the gate driving circuit wiring 170 and the source / drain metal pattern 154 contact the transparent connection pattern 184, the contact resistance increases when the contact area is small, which adversely affects the reliability of the embedded circuit. The contact resistance is reduced by forming a plurality of contact holes CH1, CH2, CH3, and CH4.

In this case, when the space occupied by the area of the gate driver GDA is sufficient, the first to fourth contact holes CH1 may be spaced apart from the gate driver circuit wiring 170 and the source / drain metal pattern 154. , The number of CH2, CH3, CH4) is not a big problem.

However, as a technique of embedding the gate driver GDA on the array substrate 100, which has a significantly lower driving frequency than that of the data driver DDA, an effort to reduce the number of channels of the data driver DDA has been made in various angles. In progress.

In particular, when the number of channels of the data driver DDA is reduced and the number of channels of the gate driver GDA is increased, the internal density of the gate driver GDA is very high, such as 2 times, 3 times, and the like, resulting in a narrow internal space. there is a problem.

As such, when the internal density of the gate driver GDA increases, the area occupied by the first to fourth contact holes CH1, CH2, CH3, and CH4 occupies a relatively large area. Difficulties reduce the number of channels.

In addition, there is a problem in that the step coverage becomes worse due to a step generated in the process of designing the gate driving circuit wiring 170, the semiconductor pattern 144, and the source / drain metal pattern 154 apart from each other. Such step difference not only acts as a cause of impairing the contact characteristics of the transparent connection pattern 184, but may also cause problems such as short or disconnection.

In order to solve the above problems, a second embodiment of the present invention has been devised. Hereinafter, the second embodiment of the present invention will be described in detail with reference to the accompanying drawings.

--- Second Embodiment ---

The second embodiment of the present invention is characterized in that the degree of integration is improved by reducing the number of contact holes between the gate driving circuit wiring and the source / drain metal pattern. In addition, it is another feature to improve the reliability of the embedded circuit by improving the contact characteristics of the transparent connection pattern connecting the gate driving circuit wiring and the source / drain metal pattern.

FIG. 5 is a plan view illustrating unit pixels of an array substrate for a liquid crystal display device according to a second embodiment of the present invention, and FIG. 6 is a plan view showing a gate driver of an array substrate for a liquid crystal display device according to a second embodiment of the present invention. In detail, part B of FIG. 3 is enlarged. In particular, an array substrate for a liquid crystal display device manufactured by a four mask process is shown.

5 and 6, in the display area AA on the substrate 200, the pixel area P is defined by vertically crossing the gate line 220 and the gate line 220 in one direction. The data line 230 is constituted.

A thin film transistor T is formed at an intersection point of the gate line 220 and the data line 230. The thin film transistor T extends from the gate electrode 225 extending from the gate wiring 220, the semiconductor layer 240 on the gate electrode 225, and the data wiring 230. And a source electrode 232 in contact with the drain electrode and a drain electrode 234 spaced apart from the source electrode 232.

The semiconductor layer 240 is a double layer in which an active layer made of pure amorphous silicon (a-Si: H) and an ohmic contact layer made of amorphous silicon (n + a-Si: H) containing impurities are sequentially stacked. It may be composed of a single layer made of silicon.

The amorphous pattern 274 extending from the semiconductor layer 240 extends below the data line 230. The amorphous pattern 274 protrudes out of the data line 230.

The pixel electrode 280 in contact with the drain electrode 234 through the drain contact hole CH2 exposing a part of the drain electrode 234 is configured to correspond to the pixel region P. Referring to FIG. The pixel electrode 280 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

In this case, the pixel electrode 280 is designed to extend to overlap the gate wiring 220 of the front end, and the pixel wiring 280 of the front end is the first electrode, and the pixel electrode 280 overlapping the first electrode. Is a second electrode, and a storage capacitor (Cst) is formed by using an insulating film separated in an interposed space between the first and second electrodes as a dielectric layer.

Although not shown in detail in the drawing, the pixel electrode 280 is configured in a rod shape, and the pixel electrode 280 and the rod-shaped common electrode (not shown) that are alternately arranged in the pixel region P are further configured. The transverse electric field may be applied.

On the other hand, the gate driver GDA on the substrate 200 configures the gate driver circuit wiring 270 and the driving transistors (T1, T2, T3, and T4 of FIG. 3) in one direction. Although not shown in detail in the drawings, the plurality of gate driving circuit lines 270 may include a gate-off voltage line for applying a gate-off voltage, a plurality of clock signal lines, and an initialization for transmitting the plurality of clock signal lines and initialization signals. Signal wiring and the like.

A source / drain metal pattern 254 is formed on the upper portion overlapping the gate driving circuit wiring 270. The gate driving circuit wiring 270 and the source / drain metal pattern 254 electrically connect the gate driving circuit wiring 270 and the source / drain metal pattern 254 through the first and second contact holes CH1 and CH2. A transparent connection pattern 284 is connected to each other.

In this case, the source / drain metal pattern 254 is formed of one selected from the group of conductive metal materials including molybdenum, molybdenum alloy, copper, copper alloy, aluminum, and aluminum alloy.

The gate driving circuit wiring 270 is made of the same material as the gate wiring 220, and the source / drain metal pattern 254 is made of the same material as the data wiring 230. The transparent connection pattern 284 is made of the same material as the pixel electrode 280.

In the above configuration, the transparent connection pattern 284 is formed through the first and second contact holes CH1 and CH2 in a state in which the gate driving circuit wiring 270 and the source / drain metal pattern 254 are overlapped. It characterized in that the contact.

FIG. 7 is a cross-sectional view taken along the line VII-VII of FIG. 6, and will be described in detail with reference to this. FIG.

As illustrated, the gate driving circuit wiring 270 is formed in one direction corresponding to the gate driver GDA on the substrate 200. The gate driving circuit wiring 270 is made of the same material as the gate wiring 220 of FIG. 6.

The gate insulating layer 245 is formed on the upper front surface of the gate driving circuit wiring 270 with one selected from a group of inorganic insulating materials including silicon oxide (SiO ₂ ) and silicon nitride (SiNx).

The semiconductor pattern 244 and the source / drain metal pattern 254 are sequentially stacked on the gate insulating layer 245 and overlapped with the gate driving circuit wiring 270. The semiconductor pattern 244 may include a first amorphous pattern (not shown) made of pure amorphous silicon (a-Si: H), and a second amorphous pattern made of amorphous silicon (n + a-Si: H) containing impurities. Not shown).

The semiconductor pattern 244 is made of the same material as the semiconductor layer 240 of FIG. 5, and the source / drain metal pattern 254 is the same layer as the data line 230 of FIG. 5. In this case, the semiconductor pattern 244 and the source / drain metal pattern 254 are patterned using one mask process as an example.

On the upper portion of the semiconductor pattern 244 and the source / drain metal pattern 254, an inorganic insulating group including silicon oxide (SiO ₂ ) and silicon nitride (SiNx) or photo acryl and benzocyclobutene ( A protective film 255 is formed with one selected from the group of organic insulating materials including benzocyclobutene).

A passivation layer 255 corresponding to each of the gate driving circuit wiring 270 and the source / drain metal pattern 254 to expose the gate driving circuit wiring 270 and the source / drain metal pattern 254. The first contact hole CH1 and the second contact hole CH2 of FIG. 6 are formed.

A transparent connection pattern 284 is formed on the passivation layer 255 including the first contact hole CH1 and the second contact hole to connect the gate driving circuit wiring 270 and the source / drain metal pattern 254. The transparent connection pattern 284 is made of the same material as the pixel electrode 280 of FIG. 5.

In the second embodiment of the present invention, unlike the first embodiment, the source is disposed on the upper part of the gate driving circuit wiring 270 overlapping with the gate driving circuit wiring 270 so that there is no separation distance between the gate driving circuit wiring 270 and the source / drain metal pattern 254. The drain metal pattern 254 is designed to be extended.

In particular, in the process of patterning the first contact hole CH1 and the second contact hole by a dry etching process, the source / drain metal pattern 254 corresponding to the first contact hole CH1 and the second contact hole is formed. Pattern to penetrate.

That is, the source / drain metal pattern 254 may be formed of one selected from the group of conductive metal materials including molybdenum, molybdenum alloy, copper, and aluminum. In this case, it is preferable that the source / drain metal pattern 254 uses molybdenum or a molybdenum alloy which reacts well in a dry etching process.

In this case, since the gate driving circuit wiring 270 and the source / drain metal pattern 254 are overlapped with each other, the step coverage can be well designed. The source / drain metal pattern 254 is in side contact with the transparent connection pattern 284.

The above-described configuration reduces the number of contact holes by half by designing the first and second contact holes CH1 and CH2 only for the overlapped portions between the gate driving circuit wiring 270 and the source / drain metal pattern 254. In addition, it has the advantage of improving the reliability and embedded circuit density of the embedded circuit.

8A is a plan view showing a portion corresponding to the data pad unit, and FIG. 8B is a cross-sectional view taken along the line VII-VII of FIG. 8A, and will be described with reference to this.

8A and 8B, the data pad 362, the gate insulating film 345 disposed on the data pad 362, and the gate insulating film 345 corresponding to the data pad part DPA are provided. The semiconductor pattern 374 and the island pattern 354 spaced apart from each other on the sides of the semiconductor pattern 354 and the data pad contact hole disposed on the semiconductor pattern 344 and the island pattern 354 and exposing a part of the data pad 362. The data pad electrode 384 in contact with the data pad 362 via the DPH is sequentially configured.

In general, when the data pad 362 is made of the same material as the gate wiring (220 of FIG. 5), which has better electrical conductivity than the data wiring (230 of FIG. 5), the resistance can be greatly reduced. The data pad 362 is formed of the same material as the gate wiring.

In particular, the island pattern 354 is formed of the same material as the source / drain metal pattern 254 of FIG. 7, and the island pattern 354 may damage the data pad 362 during a dry etching process. Serves to prevent this from happening.

In detail with reference to FIG. 7, the first contact hole CH1 is formed to connect the gate driving circuit wiring 270 and the source / drain metal pattern 254 to the transparent connection pattern 284. The first contact hole CH1 is formed through the source / drain metal pattern 254 and the semiconductor pattern 244 by a dry etching process.

At the same time, a data pad contact hole DPH is formed to contact the data pad 362 corresponding to the data pad part DPA and the data pad electrode 384.

In this case, when the island pattern 354 is not inserted into the space between the data pad 362 and the data pad electrode 384, the etching ratio of the first contact hole CH1 and the data pad contact hole DPH is changed. The data pad contact hole DPH is formed before the first contact hole CH1, which may cause a problem that the data pad 362 exposed to the plasma for a long time is deformed.

However, the first contact hole CH1 and the data pad contact hole DPH may be inserted into the island pattern 354 by inserting the island pattern 354 into the space between the data pad 362 and the data pad electrode 384. ) Can be patterned at the same etching rate so that the data pad 362 can be exposed to plasma for a long time.

Therefore, in the second embodiment of the present invention, the integration degree of the gate driver may be improved by reducing the number of contact holes by half compared to the first embodiment.

However, the present invention is not limited to the above embodiments, and it will be apparent that various changes and modifications can be made without departing from the spirit and the spirit of the present invention.

1 is a plan view showing a conventional array substrate for a liquid crystal display device.

2 is a plan view illustrating an array substrate for a liquid crystal display device having a gate embedded type according to a first embodiment of the present invention.

3 is a plan view schematically illustrating a portion A of FIG. 2;

4A is an enlarged view of a portion B of FIG. 3.

4B is a cross-sectional view taken along the line IV-IV of FIG. 4A.

5 is a plan view illustrating unit pixels of an array substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

6 is a plan view illustrating a gate driver of an array substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

7 is a cross-sectional view taken along the line VII-VII of FIG. 6.

8A is a plan view showing a portion corresponding to the data pad portion.

FIG. 8B is a cross-sectional view taken along the line VII-VII of FIG. 8A; FIG.

* Explanation of symbols for the main parts of the drawings *

200: substrate 244: semiconductor pattern

254: source / drain metal pattern 270: gate driving circuit wiring

284: transparent connection pattern CH1, CH2: first and second contact holes

GDA: Gate Driver

Claims (10)

A substrate; A plurality of gate driving circuit wirings and a plurality of driving transistors corresponding to the gate driving unit formed on the substrate; A source / drain metal pattern extending from the driving transistor and overlapping the gate driving circuit wiring; A contact hole penetrating the overlapped portion of the source / drain metal pattern and the gate driving circuit wiring line; A transparent connection pattern connecting the source / drain metal pattern and the gate driving circuit wiring through the contact hole; Array substrate for a liquid crystal display device comprising a. The method of claim 1, And the source / drain metal pattern is one selected from the group of conductive metal materials including molybdenum, molybdenum alloy, copper, and aluminum. The method of claim 1, The gate driving circuit wiring includes a gate-off voltage wiring for applying a gate-off voltage, a plurality of clock signal wirings, an initialization signal wiring for transferring the plurality of clock signal wirings and an initialization signal, and the like. Array substrate for devices. The method of claim 1, And the gate driving circuit wiring is made of the same material as the gate wiring. The method of claim 1, And the source and drain metal patterns are made of the same material as the data line. The method of claim 1, And the source and drain metal patterns are in lateral contact with the transparent connection pattern. A substrate; Gate and data lines defining pixel regions vertically intersecting on the substrate; A thin film transistor positioned at the intersection of the gate and the data line; A pixel electrode connected to the thin film transistor; A data pad configured at one end of the data line; An island pattern positioned at an upper portion overlapping the data pad; A data pad electrode penetrating the island pattern and in contact with the data pad Array substrate for a liquid crystal display device comprising a. The method of claim 7, wherein And the island pattern is formed of the same material as that of the gate line. The method of claim 7, wherein And a semiconductor pattern is further formed below the island pattern. The method of claim 7, wherein And the data pad is formed of the same material as the gate line.

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