KR20090068617A - Method of copyback programming a non volatile memory device - Google Patents

Abstract

A copyback programming method of the non-volatile memory device is provided, which reduces the copyback time by identically performing the column scan and data output process. A copyback program instruction is input to the flash memory device(S210). The set copyback data is stuck out to the page buffer circuit(S230). The corresponding page buffer is set to pass in the program by performing scan by the column unit and finding the failed page buffer circuit. The simultaneously stuck out data is output to the outside. After correcting the error, outputted data is inputted again(S250). The data is stored to the page of the other address(S270).

Description

Method of copyback programming a nonvolatile memory device

The present invention relates to a copyback program of a nonvolatile memory device, and more particularly, to a copyback program method of a nonvolatile memory device capable of shortening a copyback time of a nonvolatile memory device including a multi-level cell.

The semiconductor memory device is a memory device that stores data and can be read when needed. Semiconductor memory devices can be roughly divided into random access memory (RAM) and read only memory (ROM). RAM is a so-called volatile memory that loses its stored data when the power is turned off. RAM includes a dynamic RAM (DRAM) and a static RAM (SRAM). ROM is non-volatile memory that does not lose its stored data even when its power is interrupted. The ROM includes PROM (Programmable ROM), EPROM (Erasable PROM), EEPROM (Electrically EPROM), and Flash Memory. Among nonvolatile memories, flash memory is widely used in computers and memory cards because it has a function of electrically erasing data of cells.

Flash memory is divided into NOR type and NAND type according to the connection state of cells and bit lines. NOR flash memory is a type in which two or more cell transistors are connected in parallel to one bit line. The NOR flash memory stores data using a channel hot electron method and uses the Fowler-Nordheim tunneling method. Clear the data. In the NAND flash memory, two or more cell transistors are connected in series to one bit line, and data is stored and erased using an F-N tunneling scheme. Generally, NOR flash memory is disadvantageous for high integration because of high current consumption, but it has an advantage that it can easily cope with high speed, and NAND flash memory uses less cell current than NOR flash memory, which is advantageous for high integration. There is this.

On the other hand, the NAND flash memory device supports a page copy-back operation. The page copyback operation refers to moving data stored in one page (or source page) to another page (or target page) without outputting data to the outside. For example, if a bad block occurs while writing data to a flash memory device, the block is marked as a bad block and is not used. It also reads previously stored data and stores them in another block. At this time, if the page copyback operation supported by the NAND flash memory device is performed, the time required for data movement is much reduced.

The general copyback program is as follows.

First, when the copyback program starts, data is read from the selected page and stored in the latch of the page buffer. The latch of the page buffer is a temporary latch, not a latch for the program.

After resetting the main latch to execute the program, the column scan is executed. The specific data is written into the normal page buffer and the failed page page buffer from the first column to the last column.

Finally, the data stored in the temporary latch is transferred to the main latch and the program is executed. The program page at this time is a page of a memory block other than the page from which data was first read.

Here, after resetting the main latch, performing a column scan and writing specific data into the normal page buffer and the failed page buffer, the reason why the normal page buffer and the failed page buffer This is to have different data.

The failed page buffer is a case where any one of memory cells of a cell string constituting a bit line connected to the corresponding page buffer has failed. In this case, the flash memory device repairs a column using separate redundancy memory cells. do. Therefore, there is a redundancy bit line and a redundancy page buffer instead of the bit line connected to the failed page buffer.

Unlike the general program operation, the above-described copyback program operation reads data from a page into a temporary latch, resets the main latch, performs a column scan, and transfers data of the temporary latch as data of the main latch. More needed. In other words, the copyback program operation has no external data input operation compared to the normal program operation, but it requires time for column scan instead.

Therefore, the copyback program and the general program do not occupy much time in the operation time. However, the copyback program has described the case of a flash memory device including a single level cell. The copyback program performs a different operation in the case of a flash memory device including a multi level cell.

When reading data from a page, a flash memory device including a multi-level cell has a larger error rate than a single-level cell. Therefore, once the read data is output to the outside, error correction is performed and the program is stored in the page buffer. The process of doing it is necessary.

Therefore, a copyback program of a flash memory device including a multi-level cell requires data readout, column scan, data output, error correction, data input, and program processing, which requires more data output and input time than the column scan time. More program time is required than a program. This increases the operating time of the flash memory device, causing performance to deteriorate. In addition, it is necessary to separately set the page buffer connected to the failed memory cell or the unused page buffer connected to the redundancy memory cell so that the unused page buffer does not interrupt the copyback program. Requires complex algorithms.

Accordingly, an aspect of the present invention is to provide a copyback program method of a nonvolatile memory device for performing a column scan process and a data output simultaneously in a copyback program operation of a nonvolatile memory device including a multi-level cell. .

In the copyback program method of a nonvolatile memory device according to an aspect of the present invention,

A data reading step of reading data of the first page; Outputting the read data while sequentially scanning column addresses to detect bad column addresses and unused column addresses; Performing error correction on the read data; And a program step of programming the error corrected data on a second page.

The data reading step may include reading data of the first page into a second latch of a page buffer; Transferring data read in the second latch to a first latch of the page buffer; And storing first logic level data in a third latch of the page buffer.

The first latch receives a data input, and the second latch performs program verification.

The data output scanning step may include outputting data of the first latch of the page buffer to the outside in column order; Setting second logic level data in a first latch of a first page buffer coupled to a normal memory cell; Setting a first latch of a second page buffer connected to a failed memory cell except the first page buffer and a third page buffer connected to an unused redundancy memory cell as first logic level data; And transmitting data of the first latch to the second latch, and inverting and transmitting the data of the first latch to the third latch.

The first to third page buffers may be determined by determining whether the column address is a repair address.

The program step may include transferring data of the third latch to the first latch, continuously transferring data of the second latch to the first latch, and performing a program.

A copyback program method of a nonvolatile memory device according to another aspect of the present invention,

A data reading step of reading data of the first page; Outputting the read data while sequentially scanning column addresses to detect bad column addresses and unused column addresses; And a program step of programming the output data on a second page.

The data reading step may include reading data of the first page into a second latch of a page buffer;

Transferring data read in the second latch to a first latch of the page buffer; And storing first logic level data in a third latch of the page buffer.

The data output scanning step may include outputting data of the first latch of the page buffer to the outside in column order; Setting second logic level data in a first latch of a first page buffer coupled to a normal memory cell; Setting a first latch of a second page buffer connected to a failed memory cell except the first page buffer and a third page buffer connected to an unused redundancy memory cell as first logic level data; And transmitting data of the first latch to the second latch, and inverting and transmitting the data of the first latch to the third latch.

The first to third page buffers may be determined by determining whether the column address is a repair address.

Error-correcting the output data and programming the second page.

Copyback program method of a nonvolatile memory device according to another aspect of the present invention,

A copyback program method of a nonvolatile memory device including a multilevel cell, comprising: a data reading step of reading data of a copyback page into a page buffer; Outputting data of the first latch of the page buffer to the outside in the order of the column address; Setting second logic level data in a first latch of a first page buffer connected to a normal memory cell among the memory cells; Setting a first latch of a second page buffer coupled to a failed memory cell except the first page buffer or an unused redundancy memory cell as first logic level data; Transferring data of the first latch to the second latch, and inverting and transmitting data of the first latch to the third latch; And programming the data stored in the page buffer to a page other than the copyback page.

The data reading step may include reading data of the copyback page into a second latch of a page buffer; Transferring data read in the second latch to a first latch of the page buffer; And storing first logic level data in a third latch of the page buffer.

The first latch receives a data input, and the second latch performs program verification.

The first or second page buffer may be determined by determining whether the column address is a repair address.

The data output in the order of the column address is characterized by performing error correction.

The error corrected data may be input to the first page buffer and programmed.

The program step may include transferring data of the third latch to the first latch, continuously transferring data of the second latch to the first latch, and performing a program.

As described above, the copyback program method of the nonvolatile memory device according to the present invention can improve the overall performance by shortening the copyback time by providing a process for performing a column scan and a data output process in the same manner. .

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

1A is a block diagram illustrating the structure of a flash memory device.

Referring to FIG. 1A, a flash memory device 100 may include a memory cell array 110, a page buffer unit 120, a Y decoder 130, an input / output controller 140, an X decoder 150, and a controller. 160.

In the memory cell array 110, multi-level memory cells for data storage are connected to a word line WL and a bit line BL, and the main cell unit 111 and the main cell unit 111 for data storage are connected to each other. A redundancy cell unit 112 including redundancy cells for operating in place of a column line including a fail-nan memory cell is included.

The page buffer unit 120 includes page buffers connected to a pair of bit lines of the memory cell array 110. In an embodiment of the present invention, the page buffer unit 120 and the redundancy cell unit connected to the normal memory cells of the main cell unit 111 may be used. The second page buffer 122 connected to a bit line including a memory cell in which a page buffer connected to the redundancy cell used in 1120 is normally operated, and a failing memory cell, and the A third page buffer 123, which is connected to a redundancy memory cell but is not actually used in redundancy, is representatively illustrated.

The Y decoder 130 provides a data input / output path between the page buffer unit 120 and the input / output control unit 140 according to a control signal of the control unit 160, and the input / output control unit 140 is provided by the Y decoder 130. Input / output data input from outside through data input / output path. The X decoder 150 selects a word line of the memory cell array 110 according to a control signal of the controller 160.

In addition, the controller 160 controls the memory cell array 110, the page buffer unit 120, the Y decoder 130, the input / output control unit 140, and the X decoder 150. The controller 160 includes an output signal generator 161 for generating a data output signal PASS for outputting data stored in the page buffer unit 120 to the outside through the input / output controller 140. The output signal generator 161 outputs data stored in the page buffer unit 120 to the outside according to the read control signal RE # while the copyback read completion signal CPBCK_READOK is input at a high level. Create (PASS).

The page buffer according to an embodiment of the present invention has three latches for program and read of a multi-level cell. A detailed circuit is as follows.

FIG. 1B is a circuit diagram of the page buffer of FIG. 1A.

Referring to FIG. 1B, the page buffer includes a bit line selector 124, a precharge unit 125, a latch unit 126, and a data input unit 127.

The bit line selector 124 selects one bit line from an even bit line and an odd bit line pair, and the precharge unit 125 precharges the sensing node SO.

The latch unit 126 latches data to be programmed in a memory cell and transmits the data to the bit line through the sensing node SO, or reads and stores data programmed in the memory cell through the sensing node SO.

The data input unit 127 stores data to be programmed in the memory cell in the latch unit 126.

The bit line selector 124 includes a first NMOS transistor N1, and the precharge unit 125 includes a first PMOS transistor P1. The latch unit 126 includes second to fourteenth NMOS transistors N2 to N14 and first to seventh inverters IN1 to IN7. The data input unit 127 includes the fifteenth and sixteenth NMOS transistors N15 and N16.

The bit line selector of FIG. 1B illustrates only a part connected to the even bit line BLe. The first NMOS transistor N1 is connected between the even bit line BLe and the sensing node SO, and the bit line selection signal BSL is input to the gate of the first NMOS transistor N1.

The first PMOS transistor P1 of the precharge unit 125 is connected between the power supply voltage node and the sensing node SO, and the precharge control signal PRECH_N is input to the gate of the first PMOS transistor P1.

The second NMOS transistor N2 of the latch unit 126 is connected between the sensing node SO and the node K1, and the first program signal LATCH1_PROG is input to the gate of the second NMOS transistor N2.

The first inverter IN1 is connected between the node K1 and the node LATCH1, and inverts the voltage level of the node LATCH1 and outputs the inverted voltage to the node K1. The second and third inverters IN2 and IN3 form a first latch L1 by a latch circuit, and the first latch L1 is connected between the node LATCH1 and the node LATCH1_N.

The third NMOS transistor N3 is connected between the node LATCH1 and the node K2, and the first reset signal LATCH1_RST is input to the gate of the third NMOS transistor N3. The fourth NMOS transistor N4 is connected between the node LATCH1_N and the node K2, and the first set signal LATCH1_SET is input to the gate of the fourth NMOS transistor N4.

The fifth NMOS transistor N5 is connected between the node K2 and the ground node, and the gate of the fifth NMOS transistor N5 is connected to the sensing node SO. The sixth NMOS transistor N6 is connected between the node K1 and the data output node DO, and the data output signal PASS is input to the gate of the sixth NMOS transistor N6.

The seventh NMOS transistor N7 is connected between the sensing node SO and the node LATCH2_N, and the second program signal LATCH2_PROG is input to the gate of the seventh NMOS transistor N7. The fourth and fifth inverters IN4 and IN5 form a second latch L2 by a latch circuit, and the second latch L2 is connected between the node LATCH2 and the node LATCH2_N.

The eighth NMOS transistor N8 outputs the power supply voltage as the verification signal VER_N in accordance with the voltage level of the node LATCH2. The ninth NMOS transistor N9 is connected between the node LATCH2 and the node K3, and the second reset signal LATCH2_RST is input to the gate of the ninth NMOS transistor N9.

The tenth NMOS transistor N10 is connected between the node LATCH2_N and the node K3, and the second set signal LATCH2_SET is input to the gate of the tenth NMOS transistor N10.

The eleventh NMOS transistor N11 is connected between the sensing node SO and the node LATCH3_N, and the third program signal LATCH3_PROG is input to the gate of the eleventh NMOS transistor N11.

The sixth and seventh inverters IN6 and IN7 form a third latch L3 by a latch circuit, and the third latch L3 is connected between the node LATCH3 and the node LATCH3_N. The twelfth NMOS transistor N12 is connected between the node LATCH3 and the node K3, and the third reset signal LATCH3_RST is input to the gate of the twelfth NMOS transistor N12.

The thirteenth NMOS transistor N13 is connected between a node LATCH3_N and a node K3, and a third set signal LATCH3_SET is input to a gate of the thirteenth NMOS transistor N13. The 14th NMOS transistor N14 is connected between the node K3 and the ground node, and the gate of the 14th NMOS transistor N14 is connected to the sensing node SO.

The fifteenth NMOS transistor N15 of the data input unit 127 is connected between the node LATCH1 and the ground node, and the first data input signal LOAD is input to the gate of the fifteenth NMOS transistor N15. The sixteenth NMOS transistor N16 is connected between the node LATCH1_N and the ground node, and the second data input signal LOAD_N is input to the gate of the sixteenth NMOS transistor N16. The first data input signal LOAD and the second data input signal LOAD_N are inverted with each other. When the data is output from the page buffer circuit, the sixth NMOS transistor N6 is turned on by the data output signal PASS. In the data input operation, the sixth NMOS transistor N6 is turned off, and then the data input unit ( Data is input to the first latch L1 by applying the first and second data input signals LOAD and LOAD_N of 127.

The page buffer configured as described above may include first to third latches L1 to L3, and the first latch L1 may receive data to be programmed or output read data, and may include a second latch ( L2) outputs a program verify signal.

The process of performing a copyback program through the page buffer circuit is as follows. As mentioned above, in the following description, the first page buffer 121 is connected to a normal memory cell, the second page buffer 122 is connected to a failed memory cell, and the third page 123 is a second page. It is connected to a repair memory cell of a fail-nan memory cell connected to the buffer 122.

FIG. 1C is a block diagram illustrating the output signal generator of FIG. 1A.

Referring to FIG. 1C, the output signal generator 161 includes a pass signal generator 162.

The pass signal generator 162 outputs data stored in the page buffer unit 120 to the outside according to the read control signal RE # while the copyback read completion signal CPBCK_READOK is input at a high level. Create (PASS).

2A is a flowchart illustrating a copyback program method according to an exemplary embodiment of the present invention.

Referring to FIG. 2A, the flash memory device 100 according to an exemplary embodiment receives a copyback program command (S210) and reads the set copyback data into the page buffer circuit (S230).

It scans by column to find the failed page buffer circuit, sets the corresponding page buffer to be a program pass, and outputs the read data to the outside. The output data is input again after error correction (S250). The data stored in step S250 is stored as a page of another address (S270).

The copyback program operation will be described in more detail as follows.

FIG. 2B is a detailed operation flowchart of the copyback data reading step of FIG. 2A.

First, the state of each node of the first to third page buffers 121 to 123 is a state initialized to have an arbitrary data state. That is, the nodes LATCH1_N to LATCH3_N (hereinafter referred to as LATCH11_N, LATCH12_N, and LATCH13_N) of the first to third latches L1 to L3 of the first page buffer 121 and the second page buffer 122 are formed. Nodes of the first to third latches L1 to L3 (LATCH1_N to LATCH3_N; hereinafter referred to as LATCH21_N, LATCH22_N, and LATCH23_N) and nodes of the first to third latches L1 to L3 of the third page buffer 123. The data states of LATCH1_N to LATCH3_N (hereinafter referred to as LATCH31_N, LATCH32_N, and LATCH33_N) are all 'X' states, which are arbitrary data states.

Referring to FIG. 2B, the data of the page selected according to the input address is first read to the node LATCH2_N of the second latch L2 of the page buffer circuit for the copyback data read operation, and the second latch L2 may be read. The data of the node LATCH2_N is transmitted to the node LATCH1_N of the first latch L1 (S233).

In operation S231, the precharge control signal PRECH_N is applied at a low level to turn on the first PMOS transistor P1 to precharge the sensing node SO. The bit line is precharged using the voltage precharged to the sensing node SO by applying the bit line selection signal BSL to the first voltage V1 level to turn on the first NMOS transistor N1. .

Subsequently, the bit line select signal BSL is changed to a low level to turn off the first NMOS transistor N1, and after the operating voltage is applied to the word line in the memory cell array 110, a read evaluation is performed. do. At this time, the operating voltage applied to the word line applies a read voltage to the word line of the page for copying back and applies a pass voltage to the remaining word lines.

After the read emotion, the precharge unit 125 precharges the sensing node SO to a high level and applies the bit line selection signal BSL to the second voltage V2 level according to the data state of the memory cell. The voltage level of the sensing node SO is changed. If the memory cell is programmed, the sensing node SO maintains a high level, and if the memory cell is not programmed, the sensing node SO changes to a low level.

The second set signal LATCH2_SET of the second latch L2 is applied at a high level to store data of the memory cell as the node LATCH2_N of the second latch L2.

By the read operation, data stored in a memory cell is stored in the node LATCH12_N of the second latch L2 of the first page buffer 121, and the node of the second latch L2 of the second page buffer 122 is stored. (LATCH22_N) maintains the '1' data state.

In addition, since the data read by the node LATCH32_N of the second latch L2 of the redundancy unit 112 of the third page buffer 123 is not related to the copyback program operation, an arbitrary 'X' data state is used. Is maintained.

The second page buffer 122 is a page buffer which is not used because it is a page buffer connected to the failed memory cell. The page buffer not used in the flash memory device 100 has a '1' data state because it is set to always prohibit program in the write operation.

In operation S233, the nodes LATCH11_N, LATCH21_N, and LATCH31_N of the first latch L1 are in the same state as the nodes LATCH12_N, LATCH22_N, and LATCH32_N of the second latch L2. The other nodes are in any X data state.

Finally, nodes LATCH13_N, LATCH23_N, and LATCH33_N of the third latch L3 are set to a '1' data state (S235). In this case, the third reset signal LATCH3_RST is used.

After setting the third latch L3, the controller 160 inputs the copyback read completion signal CPBCK_READOK to the output signal generator 161 at a high level (S237).

As described above, when the copyback data reading is completed, each latch is in a state as shown in Table 1 below. Next, a process of scanning data in units of columns and inputting / outputting to the outside (step S250 of FIG. 2A) is performed.

FIG. 2C is a detailed operation flowchart of the data scan and input / output steps of FIG. 2A.

Referring to FIG. 2C, first, data is output to the outside through the Y decoder 130 and the input / output controller 140 from the column address '0' to the end (S251). To this end, the read control signal RE # is applied at a low level so that the output signal generator 161 generates the data output signal PASS at a high level. As a result, the sixth NMOS transistor N6 of the page buffer circuit is turned on. By turning on, the data of the node LATCH1_N of the first latch L1 is output to the outside.

The control unit 160 applies the read control signal RE # to the high level (S253) so that the output signal generator 161 generates the data output signal PASS to the low level. As a result, the sixth NMOS transistor N6 of the page buffer circuit is turned off.

The controller 161 internally controls the first and second data input signals LOAD and LOAD_N to set the data state of the first latch L1 of each page buffer.

The controller 160 applies the second data input signal LOAD_N to input '0' data to the node LATCH11_N of the first latch L1 of the first page buffer 121 connected to the normally operating memory cell. Apply at high level.

Since the second page buffer 122 does not operate normally, no data is input and the last state of step S230 remains unchanged.

In addition, the controller 160 applies the first data input signal LOAD at a high level to input '1' data to the node LATCH31_N of the first latch L1 of the third page buffer 123.

In this case, the third page buffer 123 is distinguished using the repair column address. The controller 160 belongs to the first page buffer 121 when the order of the addresses becomes the repair column address, and the redundancy page buffer other than the repair column address is used as the third page buffer 123 as the first data input signal LOAD. Is input to a high level to set the node LATCH31_N of the first latch L1 to be in a '1' data state.

Upon completion of step S253, the nodes of each page buffer are in the state shown in Table 2 below.

After setting the page buffer, the data of the first latch L1 is transferred to the second latch L2 (S255), the data of the first latch L1 is inverted and transferred to the third latch L3. (S257).

In operation S255, data of the node LATCH1_N of the first latch L1 is transferred to the node LATCH2_N of the second latch L2 and is connected to the normal first page buffer 121 and the failed memory cell. The data of the second latch L2 of the two page buffer 122 is not changed. The node LATCH32_N of the second latch L2 of the third page buffer 123 connected to the unused redundancy memory cell is in a '1' data state.

In operation S257, the nodes LATCH23_N and LATCH33_N of the third latch L3 of the second and third page buffers 122 and 123 except for the third latch L3 of the first page buffer 121 may be formed. The data state is '0'.

Steps S251 to S257 are performed in column order according to the increase of the column counter, so that nodes of each page buffer are in the state shown in Table 3 below.

As described above, when data scanning and reading of all columns are completed, a copyback read completion signal CPBCK_READOK is output (S263).

Finally, a copyback program is executed.

FIG. 2D is a detailed operational flowchart of the copyback program step of FIG. 2A.

Referring to FIG. 2D, in order to proceed with the copyback program, data of the node LATCH3_N of the third latch L3 is transmitted to the node LATCH1_N of the first latch L1 (S271).

In order to perform step S271, the first set signal LATCH1_SET of the first latch L1 is applied to the high level to turn on the fourth NMOS transistor N4, and the third program signal LATCH3_PROG to the high level. And turns on the eleventh NMOS transistor N11.

Accordingly, data of the node LATCH3_N of the third latch L3 is transmitted to the node LATCH1_N of the first latch L1.

The data of the second latch L2 is transferred to the first latch L1 (S273). In this case, the first reset signal LATCH1_RST of the first latch L1 is applied at a high level to turn on the third NMOS transistor N3, and the second program signal LATCH2_PROG is applied at a high level to the seventh NMOS transistor. Do this by turning on (N7).

Each node is in a state as shown in Table 4 as a result of performing steps S271 and S273.

As shown in Table 4 above, the data of the node LATCH2_N of the second latch L2 is programmed in a page to which a copyback is programmed with each node set (S275). Program operation generally depends on program operation. Before performing the copyback program, a process of re-inputting data which has been error-corrected to externally output data may be included. In this case, since the error-corrected data is input only to the first page buffer 121 connected to the normal memory cell, the second and third page buffers 122 and 123 are not affected.

Accordingly, as shown in Table 4, nodes LATCH22_N of the second latch L2 of the second page buffer 122 connected to the failed memory cell and the third page buffer 123 connected to the unused redundancy memory cell, LATCH32_N) is all in '1' data state, so it is already in the program pass state.

Therefore, if only data of the second latch L2 of the first page buffer 121 connected to the normal memory cell is programmed, and only the node LATCH12_N of the second latch L2 is changed to '1', all the copyback programs The control unit 160 determines that this is completed, and can normally complete the copyback program.

When the copyback operation according to the above-described FIGS. 2A to 2D is performed, a difference in progress time as shown in Table 5 below appears.

Table 5 shows the operation time of a flash memory device including a multi-level cell, tR is a random read time, tRC is a read time of 1 byte, tWC is an IO write time of 1 byte, tPROG is a write time. K is the number of pages, and tSCAN is a column scan time of 1 byte, where tSCAN> = tRC.

As shown in Table 5, the copyback program according to the present invention can be confirmed that the overall time is reduced by reducing the column scanning time as compared to the general copyback program.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A is a block diagram illustrating the structure of a flash memory device.

FIG. 1B is a circuit diagram of the page buffer of FIG. 1A.

FIG. 1C is a block diagram illustrating the output signal generator of FIG. 1A.

2A is a flowchart illustrating a copyback program method according to an exemplary embodiment of the present invention.

FIG. 2B is a detailed operation flowchart of the copyback data reading step of FIG. 2A.

FIG. 2C is a detailed operation flowchart of the data scan and input / output steps of FIG. 2A.

FIG. 2D is a detailed operational flowchart of the copyback program step of FIG. 2A.

* Brief description of the main parts of the drawings *

100 flash memory device 110 memory cell array

120: page buffer unit 130: Y decoder

140: input and output control unit 150: X decoder

160: control unit

Claims (18)

A data reading step of reading data of the first page; Outputting the read data while sequentially scanning column addresses to detect bad column addresses and unused column addresses; Performing error correction on the read data; And A program step of programming the error corrected data on a second page Copyback program method of a nonvolatile memory device comprising a. The method of claim 1, The data reading step, Reading data of the first page into a second latch of a page buffer; Transferring data read in the second latch to a first latch of the page buffer; And Storing first logic level data with a third latch of the page buffer Copyback program method of a nonvolatile memory device comprising a. The method of claim 2, And wherein the first latch receives a data input and the second latch performs program verification. The method of claim 2, The data output scanning step, Outputting data of the first latch of the page buffer to the outside in the column order; Setting second logic level data in a first latch of a first page buffer coupled to a normal memory cell; Setting a first latch of a second page buffer connected to a failed memory cell except the first page buffer and a third page buffer connected to an unused redundancy memory cell as first logic level data; And Transferring data of the first latch to the second latch, and inverting and transmitting data of the first latch to the third latch; Copyback program method of a nonvolatile memory device comprising a. The method of claim 4, wherein The first to third page buffers are determined by determining whether the column address is a repair address. The method of claim 4, wherein The program step, And transferring data of the third latch to the first latch, successively transferring data of the second latch to the first latch, and performing a program. A data reading step of reading data of the first page; Outputting the read data while sequentially scanning column addresses to detect bad column addresses and unused column addresses; And A program step of programming the output data on a second page Copyback program method of a nonvolatile memory device comprising a. The method of claim 7, wherein The data reading step, Reading data of the first page into a second latch of a page buffer; Transferring data read in the second latch to a first latch of the page buffer; And Storing first logic level data with a third latch of the page buffer Copyback program method of a nonvolatile memory device comprising a. The method of claim 8, The data output scanning step, Outputting data of the first latch of the page buffer to the outside in the column order; Setting second logic level data in a first latch of a first page buffer coupled to a normal memory cell; Setting a first latch of a second page buffer connected to a failed memory cell except the first page buffer and a third page buffer connected to an unused redundancy memory cell as first logic level data; And Transferring data of the first latch to the second latch, and inverting and transmitting data of the first latch to the third latch; Copyback program method of a nonvolatile memory device comprising a. The method of claim 9, The first to third page buffers are determined by determining whether the column address is a repair address. The method of claim 7, wherein Error-correcting the output data and programming the second page in the second page. In the copyback program method of a nonvolatile memory device including a multi-level cell, A data reading step of reading data of a copyback page into a page buffer; Outputting data of the first latch of the page buffer to the outside in the order of the column address; Setting second logic level data in a first latch of a first page buffer connected to a normal memory cell among the memory cells; Setting a first latch of a second page buffer coupled to a failed memory cell except the first page buffer or an unused redundancy memory cell as first logic level data; Transferring data of the first latch to the second latch, and inverting and transmitting data of the first latch to the third latch; And Programming the data stored in the page buffer to a page other than the copyback page. Copyback program method of a nonvolatile memory device comprising a. In claim 12 The data reading step, Reading data of the copyback page into a second latch of a page buffer; Transferring data read in the second latch to a first latch of the page buffer; And Storing first logic level data with a third latch of the page buffer Copyback program method of a nonvolatile memory device comprising a. The method of claim 13, And wherein the first latch receives a data input and the second latch performs program verification. The method of claim 14, And the first or second page buffer is determined by determining whether the column address is a repair address. The method of claim 14, And outputting the data output in the order of the column address to perform error correction. The method of claim 16, And programming the error corrected data into the first page buffer. The method of claim 14, The program step, And transferring data of the third latch to the first latch, successively transferring data of the second latch to the first latch, and performing a program.

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